CN205539191U - Multi -functional signal parameter testing arrangement of digit based on FPGA and MSP430 - Google Patents
Multi -functional signal parameter testing arrangement of digit based on FPGA and MSP430 Download PDFInfo
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- CN205539191U CN205539191U CN201620176508.1U CN201620176508U CN205539191U CN 205539191 U CN205539191 U CN 205539191U CN 201620176508 U CN201620176508 U CN 201620176508U CN 205539191 U CN205539191 U CN 205539191U
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Abstract
The utility model relates to a multi -functional signal parameter testing arrangement of digit based on FPGA and MSP430, the adoption is given first place to with MSP430, the processing system frame of FPGA for assisting, regard MSP430F5529 as control processing core, FPGA is as signal processing unit, the high -speed computation ability that combines MSP430's high -efficient control system with FPGA, realized sinusoidal undulation frequency, the multi -functional signal parameter test of two way square signal time interval and rectangular pulse duty cycle, and carry out refreshing of data through the button, the troubles that the historical data hour recording that there's not enough time and bringing can be avoided, the whole number is according to refreshing through the button, device measuring result settling time is less than 2s.
Description
Technical field
This utility model relates to field programmable gate array (FPGA), microcomputer development technology, digital circuit technique, mould electricity circuit engineering, a kind of digital multi signal parameter based on FPGA Yu MSP430 test device.
Background technology
Signal parameter tester be measure circuit under test signal parameter test instrunment, weigh the Primary Reference of its quality according to mainly having: signal band width can be surveyed, signal voltage amplitude can be surveyed, parameter degree of accuracy can be surveyed, parameter function kind etc. can be surveyed.
In prior art with the application motion closest to one of which technical scheme be a kind of alternating current signal parameter testing device (patent publication No.: CN201413357Y), this device includes AD collecting unit, DSP data processing unit, CPLD control unit and display unit, described AD collecting unit is made up of ADC chip, input is test test pencil, and output sampled data is to DSP data processing unit；Described DSP data processing unit is made up of dsp chip and peripheral circuit, inputs the sampled data into AD collecting unit, output process after data and address, control information to CPLD control unit；Described CPLD control unit is made up of CPLD chip, and input is connected with DSP data processing unit, and output is connected with display unit；Described display unit is made up of four binary-coded decimal conversion chips and four LED seven segment digital tubes, and input is connected with CPLD control unit.This technical scheme can be by dialling the key control display amplitude of AC signal, average and frequency parameter.Test signal kinds and function singleness, can frequency measurement bandwidth (signal frequency range can be surveyed) narrower, test result precision is not high enough.
There is main technological deficiency in prior art.The first, this test device is in test signal kinds and function singleness, can only test the parameters such as the frequency of AC signal, amplitude；The second, this test device needs raising further in terms of certainty of measurement, and the collection that the program uses the mode of AD sampling to carry out signal judges with data, and owing to being limited by A/D chip sampling precision, the certainty of measurement of this device receives and greatly limits；Signal frequency range can be surveyed narrower；4th, this test device response time longer.
Summary of the invention
The purpose of this utility model is to provide a kind of digital multi signal parameter based on FPGA Yu MSP430 to test device, to overcome defect present in prior art.
nullFor achieving the above object，The technical solution of the utility model is: a kind of digital multi signal parameter based on FPGA Yu MSP430 test device，Including: for measuring the first interface circuit of sine wave freuqency，The amplifying circuit being connected with described first interface circuit，The shaping circuit being connected with described amplifying circuit，For measuring the second interface circuit of square wave time interval，The OPA847 circuit being connected with described second interface circuit，The first amplitude limiter circuit being connected with a described OPA847 circuit，For measuring pulse signal dutycycle the 3rd interface circuit，The 2nd OPA847 circuit being connected with described 3rd interface circuit，The second amplitude limiter circuit being connected with described 2nd OPA847 circuit，Respectively with described shaping circuit、The FPGA signal processing circuit that described first amplitude limiter circuit and described second amplitude limiter circuit are connected，The MSP430F5529 control being connected with described FPGA signal processing circuit processes circuit and processes keyboard circuit and the display screen circuit that circuit is connected respectively with described MSP430F5529 control.
In this utility model one embodiment, described amplifying circuit includes one the 3rd OPA847 circuit, and described shaping circuit also includes a comparator LM339 and the Schmidt trigger being sequentially connected, described comparator LM339 and described 3rd OPA847 Circuit Matching.
In this utility model one embodiment, described amplifying circuit also includes a comparator LM 393, and described shaping circuit also includes that one the 3rd amplitude limiter circuit, described 3rd amplitude limiter circuit are mated with described relatively device LM 393.
In this utility model one embodiment, described amplifying circuit also includes one the 4th OPA847 circuit and the 5th OPA847 circuit being sequentially connected, and described shaping circuit also includes one the 4th amplitude limiter circuit, described 4th amplitude limiter circuit and described 5th OPA847 Circuit Matching.
In this utility model one embodiment, described display screen circuit includes an OLED12864.
In this utility model one embodiment, described FPGA signal processing circuit is processed circuit with described MSP430F5529 control and is connected by spi bus.
Compared to prior art, this utility model have the advantages that this utility model use with MSP430 be main FPGA be auxiliary processing system framework, MSP430F5529 is processed core, FPGA as signal processing unit as control, utilize the high-speed computation ability of FPGA, it is achieved measure sine wave freuqency, square wave time interval, the function of pulse signal dutycycle.It is 1Hz ~ 50MHz that target can record the frequency range that virtual value voltage range is 50mV ~ 1V sine wave signal, and error is less than 10-4；Can record peak-to-peak value voltage range be 50mV ~ 1V, frequency range be the time interval scope of two-way square-wave signal of 10Hz ~ 1MHz be 0.1us ~ 100ms, error is less than 0.28%；Can record peak-to-peak value voltage range be 50mV ~ 1V, frequency range be the duty cycle range of 1Hz ~ 25MHz rectangular pulse signal be 10% to 90%, error is less than 1%.Can realize the measurement of advanced or delayed two-way square-wave signal time interval, max value of error is only 0.28% simultaneously.Using equal precision measuring frequency way, the time gate of measurement is 1s, and measuring speed is fast.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of digital multi signal parameter based on FPGA Yu MSP430 test device in this utility model.
Fig. 2 is two-stage OPA847 amplifier circuit schematic diagram in this utility model.
Fig. 3 is TTL squaring circuit schematic diagram in this utility model.
Fig. 4 is think of schmitt trigger shaping circuit in this utility model.
Main program flow chart when Fig. 5 is that in this utility model, digital multi signal parameter based on FPGA Yu MSP430 test device measures.
Fig. 6 is the RTL synthesis result figure of FPGA signal processing circuit in this utility model.
Fig. 7 is the program flow diagram of FPGA signal processing circuit in this utility model.
Fig. 8 is the situation oscillogram that untreated front second road signal is ahead of first via signal.
Fig. 9 is that untreated front second tunnel signal lag is in the situation oscillogram of first via signal.
Figure 10 be after the present embodiment the second tunnel signal lag in the oscillogram of the situation of first via signal.
Figure 11 is the oscillogram of the situation that the second road signal is ahead of first via signal after the present embodiment.
Detailed description of the invention
Below in conjunction with the accompanying drawings, the technical solution of the utility model is specifically described.
This utility model provides a kind of digital multi signal parameter based on FPGA Yu MSP430 test device, as shown in Figure 1, this device use with MSP430 be main FPGA be auxiliary processing system framework, MSP430F5529 is processed core, FPGA as signal processing unit as control, utilize the high-speed computation ability of FPGA, it is achieved measure sine wave freuqency, square wave time interval, the function of pulse signal dutycycle.nullIncluding: for measuring the first interface circuit of sine wave freuqency，The amplifying circuit being connected with first interface circuit，The shaping circuit being connected with amplifying circuit，For measuring the second interface circuit of square wave time interval，The OPA847 circuit being connected with the second interface circuit，The first amplitude limiter circuit being connected with an OPA847 circuit，For measuring pulse signal dutycycle the 3rd interface circuit，The 2nd OPA847 circuit being connected with the 3rd interface circuit，The second amplitude limiter circuit being connected with the 2nd OPA847 circuit，Respectively with shaping circuit、The FPGA signal processing circuit that first amplitude limiter circuit and the second amplitude limiter circuit are connected，The MSP430F5529 control being connected with FPGA signal processing circuit processes circuit and processes keyboard circuit and the display screen circuit that circuit is connected respectively with MSP430F5529 control.In the present embodiment, controller (MSP430 and FPGA) used by this programme is all the digital signal that can only identify 2v ~ 3.5v, so needing at signal access controller advance row number signal condition, script input signal conditioning is become controller discernible width section.
For improving the frequency measurement scope of this device, this device sets up low frequency measurement part separately, intermediate frequency measures part and high frequency measurement part.As shown in Fig. 2 ~ Fig. 4.
In the present embodiment, amplifying circuit includes one the 3rd OPA847 circuit, and shaping circuit also includes a comparator LM339 and a Schmidt trigger, comparator LM339 and the 3rd OPA847 Circuit Matching being sequentially connected.Small-signal is first nursed one's health to more than 200mV, the broadband operational amplifier OPA847 of employing by low frequency signal test and appraisal, then processes feeding FPGA frequency measurement by LM339 comparator and Schmidt trigger, so that it may measure accurate frequency.
Amplifying circuit also includes a comparator LM 393, and shaping circuit also includes one the 3rd amplitude limiter circuit, and the 3rd amplitude limiter circuit is mated with relatively device LM 393.Input signal is first carried out shaping through comparator LM393 by intermediate-freuqncy signal test and appraisal, and the waveform after shaping sends into FPGA by amplitude limit can carry out frequency measurement.
Amplifying circuit also includes one the 4th OPA847 circuit and the 5th OPA847 circuit being sequentially connected, and shaping circuit also includes one the 4th amplitude limiter circuit, the 4th amplitude limiter circuit and the 5th OPA847 Circuit Matching.High-frequency signal carries out gain by two-stage OPA847 and amplifies by sending into FPGA after amplitude limit, can carry out frequency measurement.
In this example it is shown that screen circuit includes an OLED12864.
In the present embodiment, FPGA signal processing circuit is connected by spi bus with MSP430F5529 control process circuit.
A kind of based on FPGA Yu MSP430 digital multi signal parameter test device that this utility model is proposed in order to allow those skilled in the art further appreciate that; illustrate below in conjunction with existing software and control method; existing software involved in this declarative procedure and control method are not the object that this utility model is protected, this utility model only protect this device device and between annexation.
Main program flow chart is as it is shown in figure 5, native system mainly has and surveys sine wave freuqency, surveys two-way square wave interval time, surveys the function of rectangular pulse dutycycle.When pressing respective keys, single-chip microcomputer carries out the process of correspondence by controlling FPGA to signal, to realize surveying sine wave freuqency, two-way square wave interval time, the measurement of rectangular pulse dutycycle.At the end of measuring, FPGA will transmit measured value to single-chip microcomputer by SPI communication mode, single-chip microcomputer finally calculate and OLED12864 shows.
MSP430F5529 single chip part is divided into four modules, is respectively as follows: initialization module, interrupt module, SPI module, display module exist.Single-chip microcomputer, as the core control centre of system, is carried out the selection of difference in functionality by key-press module, Single-chip Controlling FPGA carry out the measurement of different parameters, returns to after single-chip microcomputer OLED12864 liquid crystal screen display again.
FPGA portion mainly comprises top-level module, high frequency equal precision measurement module, time interval measurement module, high level time measurement module, low level time measurement module, SPI communication module etc., as shown in Figure 6, program flow diagram is as shown in Figure 7 for the RTL synthesis result of FPGA module.The effect of top-level module is mainly according to the data selective value that single-chip microcomputer is given, calling high frequency equal precision measurement module, time interval measurement module, high level time measurement module, low level time measurement module, data the most required are sent to single-chip microcomputer by SPI communication module.Owing to equal precision measurement is applicable to the sampling of high-frequency signal, and error is relatively big in terms of low frequency signal, and therefore this device uses the method that high frequency frequency measurement, low frequency survey week.
Start counting up between existing time interval measurement mode many employings first via signal (lower abbreviation signal A) low period, high level resets, and the method sending data during the second road signal (lower abbreviation signal B) trailing edge realizes the measurement to two-way square-wave signal time interval.Through theoretical validation and actual test, this kind of method could use in the case of may be only available for B signal is ahead of A signal, otherwise cannot correct measurement time interval.B is ahead of the situation of A and B lags behind the analog waveform figure of situation of A as shown in Fig. 8 and Fig. 9.This device uses the method first measuring two-way time interval again with 1.5 fractional frequency signal B, realizes the measurement to advanced or delayed two-way square-wave signal time interval with this, as shown in figs.10 and 11 simultaneously.
It is above preferred embodiment of the present utility model, all changes made according to technical solutions of the utility model, when produced function is without departing from the scope of technical solutions of the utility model, belong to protection domain of the present utility model.
Claims (6)
- null1. digital multi signal parameter based on FPGA Yu a MSP430 test device，It is characterized in that，Including: for measuring the first interface circuit of sine wave freuqency，The amplifying circuit being connected with described first interface circuit，The shaping circuit being connected with described amplifying circuit，For measuring the second interface circuit of square wave time interval，The OPA847 circuit being connected with described second interface circuit，The first amplitude limiter circuit being connected with a described OPA847 circuit，For measuring pulse signal dutycycle the 3rd interface circuit，The 2nd OPA847 circuit being connected with described 3rd interface circuit，The second amplitude limiter circuit being connected with described 2nd OPA847 circuit，Respectively with described shaping circuit、The FPGA signal processing circuit that described first amplitude limiter circuit and described second amplitude limiter circuit are connected，The MSP430F5529 control being connected with described FPGA signal processing circuit processes circuit and processes keyboard circuit and the display screen circuit that circuit is connected respectively with described MSP430F5529 control.
- Digital multi signal parameter based on FPGA Yu MSP430 the most according to claim 1 test device, it is characterized in that, described amplifying circuit includes one the 3rd OPA847 circuit, described shaping circuit also includes a comparator LM339 and the Schmidt trigger being sequentially connected, described comparator LM339 and described 3rd OPA847 Circuit Matching.
- Digital multi signal parameter based on FPGA Yu MSP430 the most according to claim 1 test device, it is characterised in that described amplifying circuit also includes a comparator LM 393, described shaping circuit also includes that one the 3rd amplitude limiter circuit, described 3rd amplitude limiter circuit are mated with described relatively device LM 393.
- Digital multi signal parameter based on FPGA Yu MSP430 the most according to claim 1 test device, it is characterized in that, described amplifying circuit also includes one the 4th OPA847 circuit and the 5th OPA847 circuit being sequentially connected, described shaping circuit also includes one the 4th amplitude limiter circuit, described 4th amplitude limiter circuit and described 5th OPA847 Circuit Matching.
- Digital multi signal parameter based on FPGA Yu MSP430 the most according to claim 1 test device, it is characterised in that described display screen circuit includes an OLED12864.
- Digital multi signal parameter based on FPGA Yu MSP430 the most according to claim 1 test device, it is characterised in that described FPGA signal processing circuit is processed circuit with described MSP430F5529 control and is connected by spi bus.
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| CN201620176508.1U CN205539191U (en) | 2016-03-09 | 2016-03-09 | Multi -functional signal parameter testing arrangement of digit based on FPGA and MSP430 |
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| CN201620176508.1U CN205539191U (en) | 2016-03-09 | 2016-03-09 | Multi -functional signal parameter testing arrangement of digit based on FPGA and MSP430 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106526462A (en) * | 2016-11-04 | 2017-03-22 | 上海航天测控通信研究所 | Digital circuit system test method |
| CN106771582A (en) * | 2016-11-21 | 2017-05-31 | 东南大学 | The method of testing and tester of high-frequency pulse signal |
| CN107229270A (en) * | 2017-06-02 | 2017-10-03 | 中国航发南方工业有限公司 | Power control box Auto-Test System |
| CN107255748A (en) * | 2017-06-16 | 2017-10-17 | 江苏理工学院 | A kind of data signal measurement and generator |
-
2016
- 2016-03-09 CN CN201620176508.1U patent/CN205539191U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106526462A (en) * | 2016-11-04 | 2017-03-22 | 上海航天测控通信研究所 | Digital circuit system test method |
| CN106526462B (en) * | 2016-11-04 | 2019-03-12 | 上海航天测控通信研究所 | A kind of test method of digital circuitry |
| CN106771582A (en) * | 2016-11-21 | 2017-05-31 | 东南大学 | The method of testing and tester of high-frequency pulse signal |
| CN107229270A (en) * | 2017-06-02 | 2017-10-03 | 中国航发南方工业有限公司 | Power control box Auto-Test System |
| CN107255748A (en) * | 2017-06-16 | 2017-10-17 | 江苏理工学院 | A kind of data signal measurement and generator |
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Granted publication date: 20160831 Termination date: 20190309 |
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| CF01 | Termination of patent right due to non-payment of annual fee |