CN207318701U - A kind of measuring device of computation chip reference voltage - Google Patents
A kind of measuring device of computation chip reference voltage Download PDFInfo
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- CN207318701U CN207318701U CN201721432564.8U CN201721432564U CN207318701U CN 207318701 U CN207318701 U CN 207318701U CN 201721432564 U CN201721432564 U CN 201721432564U CN 207318701 U CN207318701 U CN 207318701U
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- 238000012360 testing method Methods 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims description 7
- 238000012544 monitoring process Methods 0.000 abstract description 4
- 238000005259 measurement Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
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- 238000001514 detection method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 238000005070 sampling Methods 0.000 description 1
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Abstract
The utility model provides a kind of measuring device of computation chip reference voltage, SOP DIP converters are electrically connected using computation chip measuring circuit, computation chip to be measured is electrically connected to the surface of SOP DIP converters, pass through computation chip measuring circuit and SOP DIP converter testings computation chip to be measured, the performance of computation chip to be measured is monitored, realizes the batch testing to computation chip.The utility model realizes the core devices i.e. batch testing of computation chip to electric energy meter, the performance of the reference voltage value monitoring and metering chip by detecting computation chip, so as to ensure the measuring accuracy of electric energy meter and safeguard the vital interests of user and national grid.
Description
Technical field
It the utility model is related to the technical field of electric energy meter quality-monitoring, more particularly to a kind of computation chip reference voltage
Measuring device.
Background technology
Intelligent electric energy meter is the important equipment for establishing nationwide intelligent grid, its electrical energy measurement accuracy direct relation is used
Family and the vital interests of national grid.In order to carry out real-time control and monitoring to the quality of intelligent electric meter in process of production,
Need to evaluate and test the performance indicator of each key components of electric energy meter, and core of the computation chip as electric energy meter measurement loop
Component directly influences the measuring accuracy of electric energy meter, its main performance index is the reference voltage in A/D transfer processes.And mesh
It is preceding in production and R＆D process, still without the device tested for electric energy meter computation chip performance so that for
Ammeter can not be monitored for the performance of computation chip in process of production, this will cause the measuring accuracy of electric energy meter to have
Very big uncertainty, and then the measurement error and its consistency of batch products can be influenced.In the prior art at the same time, to electric energy
The test of the computation chip reference voltage of table is required to computation chip to be measured being welded in test circuit, and bulk article is carried out
Sampling Detection, a computation chip after tested can not reuse, and also can not carry out batch testing to multiple computation chips.For
The as above defect of the prior art, be badly in need of it is a set of can quickly, the test device of batch testing computation chip.
Utility model content
The defects of in order to solve in the prior art, the utility model provide a kind of measurement dress of computation chip reference voltage
Put, to realize that the computation chip to electric energy meter carries out rapid batch test.
To achieve these goals, the utility model embodiment provides a kind of measuring device of computation chip reference voltage,
Including：Computation chip measuring circuit and SOP-DIP converters；
The SOP-DIP converters are electrically connected the computation chip measuring circuit by multiple pins thereon；
Computation chip to be measured is electrically connected to the SOP-DIP converters upper surface, passes through the computation chip measuring circuit
The reference voltage of the computation chip to be measured is measured.
The beneficial effects of the utility model are：The utility model is electrically connected SOP-DIP using computation chip measuring circuit and turns
Computation chip to be measured, is electrically connected to the surface of SOP-DIP converters by parallel operation, passes through computation chip measuring circuit and SOP-DIP
Converter testing computation chip to be measured, monitors the performance of computation chip to be measured, realizes the batch testing to computation chip.This practicality
New realize undermines batch testing to quick, the nothing of the i.e. computation chip of core devices of electric energy meter.
Brief description of the drawings
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, other attached drawings can also be obtained according to these attached drawings.
Fig. 1 is the structure diagram of the measuring device of the utility model computation chip reference voltage；
Fig. 2 is the electrical block diagram for the measuring device that chip reference voltage is measured in one embodiment of the utility model.
Embodiment
The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without making creative work
All other embodiments obtained, shall fall within the protection scope of the present invention.
On " first " used herein, " second " ... etc., not especially censure the meaning of order or cis-position,
Also be not used to limit the utility model, its only for distinguish with constructed term description element or operation.
On " electric property coupling " used herein, can refer to two or multiple element mutually directly make entity or be electrically connected with
Touch, or mutually put into effect body or in electrical contact indirectly, and " electric property coupling " also can refer to two or more element mutual operations or dynamic
Make.
It is open term, i.e., on "comprising" used herein, " comprising ", " having ", " containing " etc.
Mean including but not limited to.
On it is used herein " and/or ", include the things any or all combination.
On direction term used herein, such as：Upper and lower, left and right, front or rear etc., are only to refer to annexed drawings
Direction.Therefore, the direction term used is intended to be illustrative and not intended to limit this case.
For defect existing in the prior art, the utility model provides a kind of measurement dress of computation chip reference voltage
Put, its structure diagram as shown in Figure 1, including：Computation chip measuring circuit and SOP-DIP converters 1.
Computation chip measuring circuit is the typical application circuit of computation chip test,
SOP-DIP converters 1 are surface patch encapsulation-dual-in-line package chip converters, have multiple pins, uniformly
The left and right sides for being distributed in SOP-DIP converters 1.SOP-DIP converters 1 are corresponded to by the multiple pins in the left and right sides thereon
Be electrically connected with computation chip measuring circuit.
Computation chip 2 to be measured is connected electrically by adhering on the upper surface of SOP-DIP converters 1, then passes through metering core
Piece measuring circuit measures the reference voltage of computation chip 2 to be measured.
The utility model substituted for computation chip to be detected using SOP-DIP converters 1, without by metering to be detected
Chip is soldered to computation chip measuring circuit, need to be only affixed on 1 surface of SOP-DIP converters, and detection speed is fast and to metering
Chip measuring circuit and computation chip are lossless, realize the measure batch for computation chip.
In one embodiment, turn as shown in Fig. 2, SOP-DIP converters 1 are surface patch encapsulation-dual-in-line package chips
Parallel operation, has the multiple pins for the left and right sides for being uniformly distributed in SOP-DIP converters 1.SOP-DIP converters 1 pass through it
On the multiple pins in the left and right sides corresponding be electrically connected with computation chip measuring circuit.
When it is implemented, as shown in Fig. 2, SOP-DIP converters 1 are the SOP-DIP converters of 16 pins, each side
8 pins.8, the left side pin of SOP-DIP converters 1 is from top to bottom followed successively by：OSCO pins 101, PF pins 102, QF pipes
Foot 103, AVDD pins 104, VIP pins 105, VIN pins 106, V2P pins 107 and V2N pins 108, and 8, right side pin
It is followed successively by from the bottom to top：V3P pins 109, V3N pins 110, REFV pins 111, TX pins 112, RX pins 113, GND pins
114th, DVDD pins 115 and OSCI pins 116, the utility model is not limited.
In one embodiment, as shown in Figure 1, computation chip measuring circuit includes：Clock module 3 and power supply module 5.
Wherein, clock module 3 is electrically connected with SOP-DIP converters 1 by pin, and it is metering to be measured that clock module 3, which is used for,
Chip 2 provides the time signal that clock square wave provides benchmark for computation chip.
Power supply module 5, for being provided by electrically connecting as the element in whole computation chip measuring circuit with DC power supply 6
Steady dc voltage.
When it is implemented, as shown in Fig. 2, there are power supply module 54 pins or so respectively to have two, left tubing feet numbering by
It is under：Pin 501 and pin 503, right side pin numbering are from top to bottom：Pin 502 and pin 504.Two pin of left side
Cathode is set to after connection to be electrically connected with the AVDD pins 104 of SOP-DIP converters 1, is to be set to anode after the connection of two pin of right side
It is electrically connected with the GND pins 114 of SOP-DIP converters 1.The anode of power supply module 5 can connect GND or AGND, this practicality
It is new to be not limited.
In another embodiment, as shown in Figure 1, computation chip measuring circuit includes：Clock module 3, power supply module 5 and at least
One pin expansion module 4.The pin and the pin of 1 side of SOP-DIP converters of 4 side of pin expansion revolving die block are one-to-one
It is electrically connected, the pin that pin expands 4 opposite side of revolving die block is electrically connected with computation chip measuring circuit, can also connect the expansion of remaining pin
The side pin of revolving die block 4.Pin expands the pin number that revolving die block 4 is used to extend SOP-DIP converters 1, is easy to implement metering
The electrical connection of multiple element in the measuring device of chip reference voltage.
When it is implemented, as shown in Fig. 2, the SOP-DIP converters 1 or so of 16 pins respectively connect the pin of 16 pins
Expand revolving die block 4.Pin expands revolving die block 4 or so two and is respectively uniformly distributed 8 pins, and left tubing feet numbering is from top to bottom：Pin
401 are from top to bottom to pin 408, right side pin numbering：Pin 409 is to pin 416.Positioned at the left side of SOP-DIP converters 1
Pin expands revolving die block 4 and corresponds electricity by pin 101 to the pin 108 of pin 409 to pin 416 and SOP-DIP converters 1
Connection, the pin positioned at the right side of SOP-DIP converters 1 expand revolving die block 4 and pass through pin 401 to pin 408 and SOP-DIP converters
1 pin 116 is corresponded to pin 109 and is electrically connected, from the pin number expanded function realized to SOP-DIP converters 1.
When it is implemented, as shown in Fig. 2, 404 pins of left tubing feet expansion module 4 by the resistance R1 of a 10k Ω with
The cathode of power supply module 5 is electrically connected, at the same be electrically connected with the anode of power supply module 5 by a 0.1uf filter capacitors C5 i.e. with
AGND connections.
412 pins of right side pin expansion module 4 are electrically connected by the pull-up resistor R2 and the cathode of power supply module 5 of a 1k Ω
Connect, 413 pins of right side pin expansion module 4 are electrically connected by the pull-up resistor R3 of a 1k Ω with the cathode of power supply module 5.It is right
The filter capacitor of 0.1uf and 1uf in parallel between 410 pins of side pipe foot expansion module 4 and 411 pins, right side pipe
410 pins of foot expansion module 4 are electrically connected with the cathode of power supply module 5,411 pins and the power supply of right side pin expansion module 4
The anode of module 5 is electrically connected.The filter capacitor that 414 pins of right side pin expansion module 4 pass through 0.1uf and 1uf
Anode after parallel connection with power supply module 5 is electrically connected.The anode of power supply module 5 is electrically connected with AGND.
In one embodiment, turn as shown in Fig. 2, SOP-DIP converters 1 are surface patch encapsulation-dual-in-line package chips
Parallel operation, has the multiple pins for the left and right sides for being uniformly distributed in SOP-DIP converters 1, and is corresponded to by its multiple pin
Be electrically connected with computation chip measuring circuit.Computation chip 2 to be measured by adhere on SOP-DIP converters 1 upper surface and its
It is electrically connected, then the reference voltage of computation chip 2 to be measured is measured by computation chip measuring circuit.Computation chip measurement electricity
Road includes：Clock module 3 and power supply module 5.Wherein clock module 3 includes：Crystal oscillator unit X1 and capacitance C1, C2.
After capacitance C1 is in parallel with crystal oscillator unit X1 after connecting with capacitance C2 form clock module 3, one end of clock module 3 with
OSCO pins 101 are electrically connected, and the other end is electrically connected with OSCI pins 116.
When it is implemented, as shown in Fig. 2, in computation chip measuring circuit, by the capacitance C2 of the capacitance C1 and 22p of 22p
Series connection, then composes in parallel clock module 3 with 3.35MHz crystal oscillator units X1 (crystal oscillator).One end of clock module 3 with
The OSCO pins 101 of SOP-DIP converters 1 are electrically connected, and the other end is electrically connected with the OSCI pins 116 of SOP-DIP converters 1.
Clock module 3 produces clock square wave by crystal oscillator unit X1, and reference clock is provided for computation chip 2 to be measured.
In one embodiment, as shown in Figure 1, the measuring device of computation chip reference voltage further includes：Direct voltage source 6 and ten thousand
With table 7.6 cathode of direct voltage source is electrically connected with the cathode of power supply module 5, and anode is electrically connected with the anode of power supply module 5, is used for
Steady dc voltage is provided for the element in whole computation chip measuring circuit.
When it is implemented, as shown in Fig. 2, pin 414 and SOP- that the positive test pencil of universal meter 7 passes through pin expansion module 4
The REFV pins 111 of DIP converters 1 are electrically connected, and bear pin 411 and SOP-DIP converter of the test pencil by pin expansion module 4
1 GND pins 114 are electrically connected, for reading the reference voltage value of computation chip to be measured.Direct voltage source 6 is 5V power supplys, general-purpose
Table 7 is six and half universal meters, and the utility model is not limited.
The utility model is electrically connected SOP-DIP converters 1 using computation chip measuring circuit, by the electricity of computation chip 2 to be measured
The surface of SOP-DIP converters 1 is connected to, metering core to be measured is tested by computation chip measuring circuit and SOP-DIP converters 1
Piece 2, monitors the performance of computation chip 2 to be measured, realizes the batch testing to computation chip.The utility model is realized to electric energy meter
Core devices, that is, computation chip batch testing, the property of the reference voltage value monitoring and metering chip by detecting computation chip
Can, so as to ensure the measuring accuracy of electric energy meter and safeguard the vital interests of user and national grid.
Specific embodiment is applied in the utility model to be set forth the principle and embodiment of the utility model, with
The explanation of upper embodiment is only intended to help the method and its core concept for understanding the utility model；Meanwhile for this area
Those skilled in the art, according to the thought of the utility model, there will be changes, comprehensive in specific embodiments and applications
Upper described, this specification content should not be construed as the limitation to the utility model.
Claims (6)
- A kind of 1. measuring device of computation chip reference voltage, it is characterised in that including：Computation chip measuring circuit and SOP- DIP converters；The SOP-DIP converters are electrically connected the computation chip measuring circuit by multiple pins thereon；Computation chip to be measured is electrically connected to the SOP-DIP converters upper surface, by the computation chip measuring circuit to institute The reference voltage for stating computation chip to be measured measures.
- 2. the measuring device of computation chip reference voltage according to claim 1, it is characterised in that the pin includes： OSCO pins, AVDD pins, REFV pins, GND pins and OSCI pins.
- 3. the measuring device of computation chip reference voltage according to claim 2, it is characterised in that the computation chip is surveyed Amount circuit includes：Clock module and power supply module；The clock module is electrically connected with the SOP-DIP converters, for providing clock square wave for the computation chip to be measured；The cathode of the power supply module is electrically connected with the AVDD pins, and anode is electrically connected with the GND pins, for be described Computation chip measuring circuit is powered.
- 4. the measuring device of computation chip reference voltage according to claim 3, it is characterised in that the computation chip is surveyed Amount circuit further includes：At least one pin expansion module；The pin of the pin expansion module side is electrically connected correspondingly with the pin of the SOP-DIP converters side； The pin expansion module is used for the number of pins for extending the SOP-DIP converters.
- 5. the measuring device of computation chip reference voltage according to claim 3, it is characterised in that the clock module bag Include：Crystal oscillator unit and capacitance；The crystal oscillator unit is electrically connected with one end after the capacitance parallel connection with the OSCO pins, the other end and the OSCI pins It is electrically connected.
- 6. the measuring device of computation chip reference voltage according to claim 3, it is characterised in that further include：Direct current Potential source and universal meter；Described direct voltage source one end is electrically connected with the cathode, and the other end is electrically connected with the anode；The positive test pencil of the universal meter is electrically connected with the REFV pins, and negative test pencil is electrically connected with the GND pins, for reading The reference voltage value of the computation chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721432564.8U CN207318701U (en) | 2017-10-31 | 2017-10-31 | A kind of measuring device of computation chip reference voltage |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721432564.8U CN207318701U (en) | 2017-10-31 | 2017-10-31 | A kind of measuring device of computation chip reference voltage |
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| CN207318701U true CN207318701U (en) | 2018-05-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656235A (en) * | 2017-10-31 | 2018-02-02 | 国网冀北电力有限公司电力科学研究院 | A kind of measurement apparatus and method of computation chip reference voltage |
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2017
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107656235A (en) * | 2017-10-31 | 2018-02-02 | 国网冀北电力有限公司电力科学研究院 | A kind of measurement apparatus and method of computation chip reference voltage |
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