CN207318701U - A kind of measuring device of computation chip reference voltage - Google Patents

Abstract

The utility model provides a kind of measuring device of computation chip reference voltage, SOP DIP converters are electrically connected using computation chip measuring circuit, computation chip to be measured is electrically connected to the surface of SOP DIP converters, pass through computation chip measuring circuit and SOP DIP converter testings computation chip to be measured, the performance of computation chip to be measured is monitored, realizes the batch testing to computation chip.The utility model realizes the core devices i.e. batch testing of computation chip to electric energy meter, the performance of the reference voltage value monitoring and metering chip by detecting computation chip, so as to ensure the measuring accuracy of electric energy meter and safeguard the vital interests of user and national grid.

Description

A Measuring Device for Metering Chip Reference Voltage

technical field

The utility model relates to the technical field of electric energy meter quality monitoring, in particular to a measuring device for measuring chip reference voltage.

Background technique

The smart energy meter is an important device for establishing a nationwide smart grid, and the accuracy of its energy measurement is directly related to the vital interests of users and the State Grid. In order to control and monitor the quality of the smart meter in real time during the production process, it is necessary to evaluate the performance indicators of the key components of the electric energy meter, and the metering chip, as the core component of the electric energy meter measurement circuit, directly affects the performance of the electric energy meter. Metering accuracy, its main performance index is the reference voltage in the A/D conversion process. At present, in the process of production and research and development, there is still no device for testing the performance of the metering chip of the electric energy meter, so that the performance of the metering chip cannot be monitored during the production process of the electric meter, which will make the metering accuracy of the electric energy meter have a very high level of accuracy. Large uncertainty, which in turn will affect the measurement error and consistency of batch products. At the same time, in the prior art, the test of the reference voltage of the metering chip of the electric energy meter needs to weld the metering chip to be tested into the test circuit, and carry out sampling inspection on batch products. A metering chip for batch testing. In view of the above defects of the prior art, there is an urgent need for a test device that can quickly and batch test metering chips.

Utility model content

In order to solve the defects in the prior art, the utility model provides a measuring device for measuring the reference voltage of the metering chip, so as to realize rapid batch testing of the metering chips of the electric energy meter.

In order to achieve the above purpose, the embodiment of the utility model provides a measurement device for measuring the reference voltage of the metering chip, including: a measuring circuit for the metering chip and a SOP-DIP converter;

The SOP-DIP converter is electrically connected to the metering chip measurement circuit through a plurality of pins on it;

The metering chip to be tested is electrically connected to the upper surface of the SOP-DIP converter, and the reference voltage of the metering chip to be tested is measured by the measuring circuit of the metering chip.

The beneficial effects of the utility model are: the utility model adopts the measurement chip measurement circuit to electrically connect the SOP-DIP converter, and the measurement chip to be measured is electrically connected to the surface of the SOP-DIP converter, and the measurement circuit and the SOP-DIP conversion are performed by the measurement chip. The device tests the metering chip to be tested, monitors the performance of the metering chip to be tested, and realizes the batch test of the metering chip. The utility model realizes fast, non-destructive and batch testing of the core device of the electric energy meter, that is, the metering chip.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are only some embodiments of the utility model, and those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the structural representation of the measuring device of the utility model metering chip reference voltage;

Fig. 2 is a schematic diagram of the circuit structure of the measuring device for measuring the reference voltage of the metering chip in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

The terms "first", "second", ... etc. used herein do not specifically refer to a sequence or sequence, nor are they used to limit the present invention, but are only used to distinguish elements described with the same technical terms or operation.

Regarding the "electrical coupling" used herein, it may refer to two or more elements that are in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and "electrical coupling" may also refer to Two or more elements operate or act on each other.

As used herein, "comprising", "comprising", "having", "comprising" and so on are all open terms, meaning including but not limited to.

As used herein, "and/or" includes any or all combinations of the stated things.

Regarding the directional terms used herein, such as: up, down, left, right, front or back, etc., they are only directions with reference to the attached drawings. Accordingly, the directional terms used are for illustration and not for limitation of the case.

Aiming at the defects existing in the prior art, the utility model provides a measuring device for measuring the reference voltage of a metering chip, the schematic diagram of which is shown in FIG. 1 , including: a metering chip measuring circuit and a SOP-DIP converter 1 .

Metering chip measurement circuit is a typical application circuit for metering chip testing.

The SOP-DIP converter 1 is a surface mount package-dual in-line package chip converter, with multiple pins evenly distributed on the left and right sides of the SOP-DIP converter 1 . The SOP-DIP converter 1 is electrically connected to the measurement circuit of the metering chip through a plurality of pins on the left and right sides thereof.

The metering chip 2 to be tested is electrically connected to the upper surface of the SOP-DIP converter 1 by pasting it, and then the reference voltage of the metering chip 2 to be tested is measured by the metering chip measuring circuit.

The utility model uses the SOP-DIP converter 1 to replace the metering chip to be tested, and does not need to weld the metering chip to be tested to the measuring circuit of the metering chip, but only needs to paste it on the surface of the SOP-DIP converter 1, and the detection speed is fast and It is non-destructive to the measurement circuit of the metering chip and the metering chip, and realizes the batch measurement of the metering chip.

In one embodiment, as shown in Figure 2, the SOP-DIP converter 1 is a surface mount package-dual in-line package chip converter, with a plurality of evenly distributed on the left and right sides of the SOP-DIP converter 1 pins. The SOP-DIP converter 1 is electrically connected to the measurement circuit of the metering chip through a plurality of pins on the left and right sides thereof.

During specific implementation, as shown in FIG. 2 , the SOP-DIP converter 1 is a 16-pin SOP-DIP converter, with 8 pins on the left and right sides. The 8 pins on the left side of SOP-DIP converter 1 are from top to bottom: OSCO pin 101, PF pin 102, QF pin 103, AVDD pin 104, VIP pin 105, VIN pin 106, V2P pin 107 and V2N pin 108, and the 8 pins on the right from bottom to top are: V3P pin 109, V3N pin 110, REFV pin 111, TX pin 112, RX pin 113, GND tube Pin 114, DVDD pin 115, and OSCI pin 116, the utility model is not limited thereto.

In one embodiment, as shown in FIG. 1 , the metering chip measurement circuit includes: a clock module 3 and a power supply module 5 .

Wherein, the clock module 3 is electrically connected to the SOP-DIP converter 1 through pins, and the clock module 3 is used to provide a clock square wave for the metering chip 2 to be tested and provide a reference time signal for the metering chip.

The power supply module 5 is used to provide a stable DC voltage for the components in the measurement circuit of the entire metering chip by being electrically connected to the DC power supply 6 .

During specific implementation, as shown in Figure 2, the power supply module 5 has four pins, two on the left and two on the left, and the pins on the left are numbered from top to bottom: pin 501 and pin 503, and the pins on the right are numbered from top to bottom. The bottom is: pin 502 and pin 504 . After the two pins on the left are connected, they are set as positive and electrically connected to AVDD pin 104 of SOP-DIP converter 1, and after the two pins on the right are connected, they are set as negative and electrically connected to GND pin 114 of SOP-DIP converter 1. . The negative electrode of the power supply module 5 can be connected to GND or AGND, and the present invention is not limited thereto.

In another embodiment, as shown in FIG. 1 , the metering chip measurement circuit includes: a clock module 3 , a power supply module 5 and at least one pin extension module 4 . The pins on one side of the pin expansion module 4 are electrically connected to the pins on one side of the SOP-DIP converter 1, and the pins on the other side of the pin expansion module 4 are electrically connected to the measurement circuit of the metering chip. The remaining pins can also be connected to one side pins of the extension module 4 . The pin extension module 4 is used to expand the number of pins of the SOP-DIP converter 1, so as to facilitate the electrical connection of multiple components in the measuring device for measuring the reference voltage of the chip.

During specific implementation, as shown in FIG. 2 , the left and right sides of the 16-pin SOP-DIP converter 1 are respectively connected with a 16-pin pin extension module 4 . There are 8 pins evenly distributed on the left and right sides of pin extension module 4. The pin numbers on the left side are: pin 401 to pin 408 from top to bottom, and the pin numbers on the right side are: pin 409 from top to bottom. to pin 416. The pin extension module 4 on the left side of the SOP-DIP converter 1 is electrically connected to the pins 101 to 108 of the SOP-DIP converter 1 through pins 409 to 416, and is located at the SOP-DIP converter The pin extension module 4 on the right side of the device 1 is electrically connected with the pin 116 to the pin 109 of the SOP-DIP converter 1 through the pin 401 to the pin 408, so as to realize the connection of the SOP-DIP converter 1 Pin number expansion function.

During specific implementation, as shown in Figure 2, the pin 404 of the left pin expansion module 4 is electrically connected to the positive pole of the power supply module 5 through a 10kΩ resistor R1, and is connected to the negative pole of the power supply module 5 through a 0.1uf filter capacitor C5. The electrical connection is to AGND.

The 412 pin of the right pin expansion module 4 is electrically connected to the positive electrode of the power supply module 5 through a 1kΩ pull-up resistor R2, and the 413 pin of the right pin expansion module 4 is connected to the power supply module through a 1kΩ pull-up resistor R3 The positive pole of 5 is electrically connected. A 0.1uf and a 1uf filter capacitor are connected in parallel between pin 410 and pin 411 of the right pin expansion module 4, and the 410 pin of the right pin expansion module 4 is electrically connected to the positive pole of the power supply module 5. The pin 411 of the pin extension module 4 is electrically connected to the negative pole of the power supply module 5 . The pin 414 of the right pin expansion module 4 is electrically connected to the negative electrode of the power supply module 5 through a 0.1uf and a 1uf filter capacitor connected in parallel. The negative pole of the power supply module 5 is electrically connected to AGND.

In one embodiment, as shown in Figure 2, the SOP-DIP converter 1 is a surface mount package-dual in-line package chip converter, with a plurality of evenly distributed on the left and right sides of the SOP-DIP converter 1 The pins are electrically connected to the measurement circuit of the metering chip through corresponding multiple pins. The metering chip 2 to be tested is electrically connected to the upper surface of the SOP-DIP converter 1 by pasting it, and then the reference voltage of the metering chip 2 to be tested is measured by the metering chip measuring circuit. The metering chip measuring circuit includes: a clock module 3 and a power supply module 5 . The clock module 3 includes: a crystal oscillator unit X1 and capacitors C1 and C2.

The capacitor C1 and the capacitor C2 are connected in series and connected in parallel with the crystal oscillator unit X1 to form a clock module 3 . One end of the clock module 3 is electrically connected to the OSCO pin 101 , and the other end is electrically connected to the OSCI pin 116 .

During specific implementation, as shown in FIG. 2 , in the metering chip measurement circuit, a 22p capacitor C1 and a 22p capacitor C2 are connected in series, and then connected in parallel with a 3.35MHz crystal oscillator unit X1 (crystal oscillator) to form a clock module 3 . One end of the clock module 3 is electrically connected to the OSCO pin 101 of the SOP-DIP converter 1 , and the other end is electrically connected to the OSCI pin 116 of the SOP-DIP converter 1 . The clock module 3 generates a clock square wave through the crystal oscillator unit X1 to provide a reference clock for the metering chip 2 to be tested.

In one embodiment, as shown in FIG. 1 , the measuring device for measuring the chip reference voltage further includes: a DC voltage source 6 and a multimeter 7 . The positive pole of the DC voltage source 6 is electrically connected to the positive pole of the power supply module 5 , and the negative pole is electrically connected to the negative pole of the power supply module 5 to provide stable DC voltage for the components in the measurement circuit of the entire metering chip.

During specific implementation, as shown in Figure 2, the positive meter pen of multimeter 7 is electrically connected with the REFV pin 111 of SOP-DIP converter 1 through the pin 414 of pin extension module 4, and the negative meter pen is connected through the tube of pin extension module 4. The pin 411 is electrically connected to the GND pin 114 of the SOP-DIP converter 1, and is used to read the reference voltage value of the metering chip to be tested. The DC voltage source 6 is a 5V power supply, and the multimeter 7 is a six-and-a-half-digit multimeter, and the utility model is not limited thereto.

The utility model adopts the metering chip measuring circuit to be electrically connected to the SOP-DIP converter 1, and the metering chip 2 to be tested is electrically connected to the surface of the SOP-DIP converter 1, and the metering chip measuring circuit and the SOP-DIP converter 1 are used to test the metering chip to be tested. The metering chip 2 monitors the performance of the metering chip 2 to be tested, so as to realize batch testing of the metering chips. The utility model realizes the batch testing of the core device of the electric energy meter, that is, the metering chip, and monitors the performance of the metering chip by detecting the reference voltage value of the metering chip, thereby ensuring the metering accuracy of the electric energy meter and maintaining the vital interests of users and the State Grid.

In the utility model, specific examples have been applied to explain the principle and implementation of the utility model, and the explanations of the above examples are only used to help understand the method of the utility model and its core idea; meanwhile, for those of ordinary skill in the art According to the idea of the present utility model, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be construed as a limitation of the present utility model.

Claims (6)

1. A kind of 1. measuring device of computation chip reference voltage, it is characterised in that including：Computation chip measuring circuit and SOP- DIP converters；

   The SOP-DIP converters are electrically connected the computation chip measuring circuit by multiple pins thereon；

   Computation chip to be measured is electrically connected to the SOP-DIP converters upper surface, by the computation chip measuring circuit to institute The reference voltage for stating computation chip to be measured measures.
2. 2. the measuring device of computation chip reference voltage according to claim 1, it is characterised in that the pin includes： OSCO pins, AVDD pins, REFV pins, GND pins and OSCI pins.
3. 3. the measuring device of computation chip reference voltage according to claim 2, it is characterised in that the computation chip is surveyed Amount circuit includes：Clock module and power supply module；

   The clock module is electrically connected with the SOP-DIP converters, for providing clock square wave for the computation chip to be measured；

   The cathode of the power supply module is electrically connected with the AVDD pins, and anode is electrically connected with the GND pins, for be described Computation chip measuring circuit is powered.
4. 4. the measuring device of computation chip reference voltage according to claim 3, it is characterised in that the computation chip is surveyed Amount circuit further includes：At least one pin expansion module；

   The pin of the pin expansion module side is electrically connected correspondingly with the pin of the SOP-DIP converters side； The pin expansion module is used for the number of pins for extending the SOP-DIP converters.
5. 5. the measuring device of computation chip reference voltage according to claim 3, it is characterised in that the clock module bag Include：Crystal oscillator unit and capacitance；

   The crystal oscillator unit is electrically connected with one end after the capacitance parallel connection with the OSCO pins, the other end and the OSCI pins It is electrically connected.
6. 6. the measuring device of computation chip reference voltage according to claim 3, it is characterised in that further include：Direct current Potential source and universal meter；

   Described direct voltage source one end is electrically connected with the cathode, and the other end is electrically connected with the anode；

   The positive test pencil of the universal meter is electrically connected with the REFV pins, and negative test pencil is electrically connected with the GND pins, for reading The reference voltage value of the computation chip.