CN107239376A - The automation adjustment method and device of a kind of server interconnection chip - Google Patents
The automation adjustment method and device of a kind of server interconnection chip Download PDFInfo
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- CN107239376A CN107239376A CN201710485192.3A CN201710485192A CN107239376A CN 107239376 A CN107239376 A CN 107239376A CN 201710485192 A CN201710485192 A CN 201710485192A CN 107239376 A CN107239376 A CN 107239376A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
Abstract
The invention provides a kind of automation adjustment method of server interconnection chip and device, this method includes：Pre-set at least one CPU configuration parameter；It is determined that CPU corresponding with interconnection chip to be debugged；According to the configuration parameter of at least one CPU, the CPU determined is debugged；The CPU after control debugging sets up the interconnection that communicates with the interconnection chip to be debugged；According to the corresponding configuration parameters of the CPU after debugging, the mode of operation to the interconnection chip to be debugged is adjusted.This programme can improve the debugging efficiency of interconnection chip.
Description
Technical field
The present invention relates to field of computer technology, the automation adjustment method of more particularly to a kind of server interconnection chip and
Device.
Background technology
With the development of computer technology, people are to the performance requirement of server also more and more higher.Chip is interconnected as many
Path processor shares the acp chip of main storage system, is increasingly used widely.In order to ensure interconnecting the performance of chip, make
Before debugging and verification need to be carried out to interconnection chip, wherein, correct build of debugging enironment is the guarantee for carrying out chip checking.
At present, when building the debugging enironment of interconnection chip, mainly using manual type, i.e., adjusted first by staff
The CPU of section interconnection chip subordinate server configuration parameter, is debugged to CPU, and further according to CPU configuration parameter, regulation is mutual
Join the mode of operation of chip, so that the mode of operation of CPU configuration parameter and interconnection chip matches, complete taking for debugging enironment
Build.
Because CPU configuration parameter and the mode of operation species of interconnection chip are more, using manual type progress
That matches somebody with somebody is less efficient, so as to cause the debugging efficiency for interconnecting chip relatively low.
The content of the invention
The embodiments of the invention provide a kind of automation adjustment method of server interconnection chip and device, interconnection can be improved
The debugging efficiency of chip.
In a first aspect, the embodiments of the invention provide the automation adjustment method that a kind of server interconnects chip, including：
Pre-set at least one CPU configuration parameter；
It is determined that CPU corresponding with interconnection chip to be debugged；
According to the configuration parameter of at least one CPU, the CPU determined is debugged；
The CPU after control debugging sets up the interconnection that communicates with the interconnection chip to be debugged；
According to the corresponding configuration parameters of the CPU after debugging, the mode of operation to the interconnection chip to be debugged is carried out
Regulation.
Preferably,
Further comprise：The configuration parameter for pre-setting each CPU distinguishes corresponding operating time；
Then,
At least one CPU configuration parameter described in the basis, is debugged to the CPU determined, including：
Circulation performs S1 to S3, until the configuration parameter of the CPU in the absence of not selected mistake；
S1：From the configuration parameter of at least one CPU described in pre-setting, determine that the current of not selected mistake is matched somebody with somebody
Put parameter；
S2：According to the current configuration parameters, the running status of the CPU is controlled, and records the CPU in the operation
Operation duration under state；
S3：When the operation duration reaches operating time corresponding with the current configuration parameters, S1 is performed.
Preferably,
The CPU after described S1, S2 and S3, and the control debugging is set up with the interconnection chip to be debugged to communicate
Interconnection, including：
From at least one described CPU configuration parameter, it is current configuration parameters to determine the first configuration parameter, is worked as according to described
Preceding configuration parameter, controls the corresponding quick interconnecting channels QPI of the CPU to be run with lower-speed state, and records the QPI to exist
The first operation duration under the lower-speed state；
When first operation duration reaches the first operating time corresponding with first configuration parameter, from it is described to
In a few CPU configuration parameter, the second configuration parameter of selection is used as current configuration parameters；
According to the current configuration parameters, the QPI is controlled to be run with fast state, and record the QPI in height
The second operation duration under fast state；
When second operation duration reaches the second operating time corresponding with second configuration parameter, from it is described to
In a few CPU configuration parameter, the 3rd configuration parameter of selection is used as current configuration parameters；
According to the current configuration parameters, the CPU is controlled to set up the interconnection that communicates with the interconnection chip to be debugged.
Preferably,
The corresponding configuration parameters of the CPU according to after debugging, to the mode of operation of the interconnection chip to be debugged
It is adjusted, including：
According to the 3rd configuration parameter, the running parameter of the register of the interconnection chip to be debugged is adjusted；
According to the running parameter of the register, the mode of operation of the interconnection chip to be debugged is determined.
Preferably,
In the corresponding configuration parameters of the CPU according to after debugging, to the Working mould of the interconnection chip to be debugged
After formula is adjusted, further comprise：
It is determined that with the corresponding checking system of the interconnection chip to be debugged, and control the checking system to start.
Second aspect, the embodiments of the invention provide the automation debugging apparatus that a kind of server interconnects chip, including：If
Put unit, CPU debugging units and chip debugging unit；Wherein,
The setting unit, the configuration parameter for pre-setting at least one CPU；
The CPU debugging units, for determining CPU corresponding with interconnection chip to be debugged, and according to the setting unit
At least one CPU set configuration parameter, is debugged to the CPU determined；
The chip debugging unit, for being joined according to the corresponding configurations of the CPU after CPU debugging units debugging
Number, the mode of operation to the interconnection chip to be debugged is adjusted.
Preferably,
The setting unit, is further used for setting each CPU configuration parameter to distinguish corresponding operating time；
The CPU debugging units include：Determination subelement, control subelement and judgment sub-unit；Wherein,
The determination subelement, for from the configuration parameter of at least one CPU described in pre-setting, determining one not
The current configuration parameters being selected；
The control subelement, for the current configuration parameters determined according to the determination subelement, controls the CPU
Running status, and record operation durations of the CPU under the running status；Work as when the operation duration reaches with described
During the corresponding operating time of preceding configuration parameter, the judgment sub-unit is triggered；
The judgment sub-unit, the configuration parameter of the CPU for judging whether not selected mistake, if it is,
The determination subelement is then triggered, the chip debugging unit is otherwise triggered.
Preferably,
The determination subelement, for from least one described CPU configuration parameter, it to be current to determine the first configuration parameter
Configuration parameter；When receiving the first time triggering of the control subelement, the second configuration parameter is regard as current configuration parameters；Connect
When receiving second of triggering of the control subelement, using the 3rd configuration parameter as current configuration parameters, and the core is triggered
Piece debugging unit；
The control subelement, for when first configuration parameter is as the current configuration parameters, control to be described
The corresponding quick interconnecting channels QPI of CPU are run with lower-speed state, and record of the QPI under the lower-speed state
One operation duration；When first operation duration reaches the first operating time corresponding with first configuration parameter, first
The secondary triggering determination subelement；When second configuration parameter is as the current configuration parameters, the QPI is controlled with height
Fast state is run, and records the second operation durations of the QPI at high speeds；When second operation duration reaches
During the second operating time corresponding with second configuration parameter, the determination subelement is triggered for the second time；
The chip debugging unit, for when receiving the triggering of the determination subelement, being currently configured according to described
Parameter, controls the CPU to set up the interconnection that communicates with the interconnection chip to be debugged.
Preferably,
The chip debugging unit, for according to the 3rd configuration parameter, to the deposit to be debugged for interconnecting chip
The running parameter of device is adjusted, and according to the running parameter of the register, determines the work of the interconnection chip to be debugged
Pattern.
Preferably,
The chip debugging unit, is further used for that it is adjusted in the mode of operation to the interconnection chip to be debugged
Afterwards, it is determined that with the corresponding checking system of the interconnection chip to be debugged, and control the checking system to start.
The embodiments of the invention provide a kind of server interconnection chip automation adjustment method and device, determine with
After the corresponding CPU of interconnection chip to be debugged, according at least one default CPU configuration parameter, the CPU determined is carried out
Debugging, and control the CPU after debugging to set up the interconnection that communicates with interconnection chip to be debugged, it is then corresponding according to the CPU after debugging
Configuration parameter, the mode of operation to interconnection chip to be debugged is adjusted.The automation debugging of interconnection chip is realized with this, and
Without being matched again using manual type to the mode of operation of CPU configuration parameter and interconnection chip, so as to improve interconnection
The debugging efficiency of chip.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is a kind of flow of the automation adjustment method for server interconnection chip that one embodiment of the invention is provided
Figure；
Fig. 2 is a kind of flow of the automation adjustment method for server interconnection chip that another embodiment of the present invention is provided
Figure；
Fig. 3 is that a kind of structure of the automation debugging apparatus for server interconnection chip that one embodiment of the invention is provided is shown
It is intended to；
Fig. 4 is a kind of structure of the automation debugging apparatus for server interconnection chip that another embodiment of the present invention is provided
Schematic diagram.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments, based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained on the premise of creative work is not made, belongs to the scope of protection of the invention.
As shown in figure 1, the embodiments of the invention provide the automation adjustment method that a kind of server interconnects chip, this method
It may comprise steps of：
Step 101：Pre-set at least one CPU configuration parameter；
Step 102：It is determined that CPU corresponding with interconnection chip to be debugged；
Step 103：According to the configuration parameter of at least one CPU, the CPU determined is debugged；
Step 104：The CPU after control debugging sets up the interconnection that communicates with the interconnection chip to be debugged；
Step 105：According to the corresponding configuration parameters of the CPU after debugging, the work to the interconnection chip to be debugged
Pattern is adjusted.
In above-described embodiment, determine with after the corresponding CPU of interconnection chip to be debugged, according to it is default at least one
CPU configuration parameter, is debugged to the CPU determined, and controls the CPU after debugging to be communicated with interconnection chip foundation to be debugged
Interconnection, then according to the corresponding configuration parameters of CPU after debugging, the mode of operation to interconnection chip to be debugged is adjusted.With
This realizes the automation debugging of interconnection chip, without again using manual type is to CPU configuration parameter and interconnects chip
Mode of operation is matched, so as to improve the debugging efficiency of interconnection chip.
In one embodiment of the invention, it may further include：Pre-set each CPU configuration parameter difference
Corresponding operating time；
Then the embodiment of step 103, can include：
Circulation performs S1 to S3, until the configuration parameter of the CPU in the absence of not selected mistake；
S1：From the configuration parameter of at least one CPU described in pre-setting, determine that the current of not selected mistake is matched somebody with somebody
Put parameter；
S2：According to the current configuration parameters, the running status of the CPU is controlled, and records the CPU in the operation
Operation duration under state；
S3：When the operation duration reaches operating time corresponding with the current configuration parameters, S1 is performed.
Herein, from least one default CPU configuration parameter, option and installment parameter, and according to matching somebody with somebody for selecting
State modulator CPU running status is put, and records operation durations of the CPU under the running status, it is long when it is operated to reach pair
During operating time corresponding to the configuration parameter answered, the configuration of a not selected mistake is selected from default configuration parameter again
Parameter, CPU running status is changed with this, until all default configuration parameters are chosen.Thus, it can be matched somebody with somebody according to default
Parameter is put, control CPU runs certain time length under different conditions, realizes the automatic debugging to CPU, pass through without staff
Manual type is debugged one by one to CPU working condition, so as to be conducive to improving the debugging efficiency of interconnection chip.
Specifically, in one embodiment of the invention, the embodiment of step 103 and step 104 can include：
From at least one described CPU configuration parameter, it is current configuration parameters to determine the first configuration parameter, is worked as according to described
Preceding configuration parameter, controls the corresponding quick interconnecting channels QPI of the CPU to be run with lower-speed state, and records the QPI to exist
The first operation duration under the lower-speed state；
When first operation duration reaches the first operating time corresponding with first configuration parameter, from it is described to
In a few CPU configuration parameter, the second configuration parameter of selection is used as current configuration parameters；
According to the current configuration parameters, the QPI is controlled to be run with fast state, and record the QPI in height
The second operation duration under fast state；
When second operation duration reaches the second operating time corresponding with second configuration parameter, from it is described to
In a few CPU configuration parameter, the 3rd configuration parameter of selection is used as current configuration parameters；
According to the current configuration parameters, the CPU is controlled to set up the interconnection that communicates with the interconnection chip to be debugged.
For example, it is former using field programmable gate array (Field-Programmable Gate Array, FPGA)
When type verification technique is verified to interconnection chip, server is started shooting first upper electric, and loaded FPGA bit streams, be then based on
Intel requirement, CPU operating rate is set using the first configuration parameter, its QPI is operated in low-speed mode, is recorded simultaneously
Its first operation duration.When the first operation duration reaches first operating time corresponding with the first configuration parameter, is utilized
Two configuration parameters set CPU operating rate, its QPI is operated in fast mode.Wherein, QPI operation duration can lead in advance
Experiment is crossed to determine, specifically, when being debugged using manual type to CPU, whenever switchover operation state is needed, server
Input-output system can export corresponding prompt message, now need staff to change CPU configurations according to this prompt message, many
It is secondary that staff can obtain the empirical value of the corresponding operation duration of every kind of working condition with postponing, can using this empirical value as with
The corresponding operating time of parameter is put to be pre-set.
In the process, the corresponding QPI of CPU switch to fast state by lower-speed state, and CPU starting state can be made more steady
Fixed, this is also beneficial to CPU and remains on stabilization during interconnection chip checking, so as to be conducive to interconnecting accurately testing for chip
Card.In addition, when QPI the second operation duration reaches the second operating time, CPU is configured using the 3rd configuration parameter,
It may include CPU processing check figure and memory capacity etc. in this configuration parameter, CPU and interconnection core to be debugged controlled after the completion of configuration
Piece sets up communication interconnection, herein under interconnection state, can treat tune according to configuration parameters such as CPU processing check figures and memory capacity
The mode of operation of examination interconnection chip is debugged.Thus it may be such that CPU enters in stable running status with interconnection chip to be debugged
Row communication interconnection, so as to be conducive to accurately debugging interconnection chip.
In one embodiment of the invention, the embodiment of step 105 can include：
According to the 3rd configuration parameter, the registers parameter to the interconnection chip to be debugged is adjusted；
According to the running parameter of the register, the mode of operation of the interconnection chip to be debugged is determined.
For example, the CPU configured according to the 3rd configuration parameter processing check figure is 8 cores, inside saves as 4096MB, then can root
The 3rd configuration parameter, the running parameter of the register of interconnection chip to be debugged is adjusted, i.e., by the work of register accordingly
Parameter be also adjusted to it is corresponding with 8 core processors and internal memory 4096MB, then according to the running parameter of the register after regulation,
Interconnection chip to be debugged is adjusted to mode of operation correspondingly, with this CPU Auto-matching after realizing and adjusting, so as to carry
The debugging efficiency of height interconnection chip.
In one embodiment of the invention, after step 105, it may further include：
It is determined that with the corresponding checking system of the interconnection chip to be debugged, and control the checking system to start.
In the present embodiment, after interconnection chip to be debugged is adjusted, automatically control and interconnection chip pair to be debugged
The checking system answered starts, and then automatically begins to verify interconnection chip, so as to improve the verification efficiency of interconnection chip.
As shown in Fig. 2 the embodiments of the invention provide the automation adjustment method that a kind of server interconnects chip, this method
It may comprise steps of：
Step 201：Pre-set 3 CPU configuration parameter, and the corresponding operating time of each configuration parameter.
For example, 3 CPU configuration parameter is respectively configuration parameter A, configuration parameter B and configuration parameter C, wherein, configuration ginseng
Number A correspondence lower-speed states, configuration parameter B correspondence fast states, configuration parameter C correspondences CPU attribute information for example handles check figure
With memory size etc..
Step 202：It is determined that CPU corresponding with interconnection chip to be debugged.
Herein, it is determined that the interconnection that communicates need to be set up with interconnection chip to be debugged, and interconnection chip checking is carried out with this
CPU。
Step 203：From 3 configuration parameters set in advance, option and installment parameter A, and according to configuration parameter A, control
The corresponding QPI of CPU are run with lower-speed state, and record first operation durations of the QPI under lower-speed state.
For example, when being verified using FPGA prototype verification technology to interconnection chip, server is started shooting first on
Electricity, and FPGA bit streams have been loaded, intel requirement is then based on, CPU operating rate is set using configuration parameter A, makes it
QPI operates in low-speed mode, while recording its first operation duration.
Step 204：When the first operation duration reaches the first operating time corresponding with configuration parameter A, from presetting
3 configuration parameters in, option and installment parameter B, and according to configuration parameter B, control QPI is run with fast state, and records QPI
The second run time at high speeds.
Herein, the corresponding QPI of CPU switch to fast state by lower-speed state, and CPU starting state can be made more stable,
This is also beneficial to CPU and remains on stabilization during interconnection chip checking.
Step 205：When the second run time reaches the second operating time corresponding with configuration parameter B, from default 3
In configuration parameter, option and installment parameter C, and the interconnection that communicates is set up with interconnection chip to be debugged according to configuration parameter C, control CPU.
When QPI the second operation duration reaches the second operating time, CPU is configured using configuration parameter C, this matches somebody with somebody
Putting may include CPU processing check figure and memory capacity etc. in parameter, control CPU to be built with interconnection chip to be debugged after the completion of configuration
Vertical communication interconnection, can be according to configuration parameters such as CPU processing check figures and memory capacity, to be debugged mutual herein under interconnection state
The mode of operation of connection chip is debugged.
Step 206：According to configuration parameter C, the registers parameter to the interconnection chip to be debugged is adjusted, and
According to the running parameter of the register, the mode of operation of the interconnection chip to be debugged is determined.
For example, be 8 cores according to the configuration parameter C CPU configured processing check figure, inside save as 4096MB, then can basis
This 3rd configuration parameter, the running parameter of register is also adjusted to it is corresponding with 8 core processors and internal memory 4096MB, then
According to the running parameter of the register after regulation, interconnection chip to be debugged is adjusted to mode of operation correspondingly, with this reality
Now with the CPU Auto-matchings after regulation.
Step 207：It is determined that with the corresponding checking system of the interconnection chip to be debugged, and control the checking system to open
It is dynamic.
After interconnection chip to be debugged is adjusted, automatically controls checking system corresponding with interconnection chip to be debugged and open
It is dynamic, then automatically begin to verify interconnection chip, so as to improve the verification efficiency of interconnection chip.
Method in the present embodiment can at least be realized by following procedure：
########################################
Echo " Boot Step1=>BIOS_1:Begin"
## configures cpu scripts for the first time
./BIOS_1.txt
Echo " Boot Step1=>BIOS_1:Done and Wait 35s"
## latency values according to experiment, it is necessary to be adjusted
sleep 35
########
Echo " Boot Step2=>BIOS_2:Begin"
Second of configuration cpu script of ###
./BIOS_2.txt
Echo " Boot Step2=>BIOS_2:Done and Wait 180s"
## latency values according to experiment, it is necessary to be adjusted
sleep 180
########################################
Echo " Boot Step3=>QPI LINK:Begin"
## starts qpi interfaces of the cpu with interconnecting chip
./qpi_link.txt
Echo " Boot Step3=>QPI LINK:Done and check"
########################################
########################################
Echo " Boot Step4=>NC Config:Begin"
## interconnects the register configuration of chip
./nc_config.txt
Echo " Boot Step4=>NC Config:Done"
########################################
In the above-described embodiments, after CPU corresponding with interconnection chip to be debugged is determined, according to default 3 CPU
Configuration parameter, the CPU determined debugged, and controls the CPU after debugging to be set up with interconnection chip to be debugged communicate mutual
Connection, then according to the corresponding configuration parameters of CPU after debugging, the mode of operation to interconnection chip to be debugged is adjusted.With this
The automation debugging of interconnection chip is realized, without again using work of the manual type to CPU configuration parameter and interconnection chip
Operation mode is matched, so as to improve the debugging efficiency of interconnection chip.
As shown in figure 3, the embodiments of the invention provide the automation debugging apparatus that a kind of server interconnects chip, including：
Setting unit 301, CPU debugging units 302 and chip debugging unit 303；Wherein,
The setting unit 301, the configuration parameter for pre-setting at least one CPU；
The CPU debugging units 302, set single for determining CPU corresponding with interconnection chip to be debugged, and according to described
The configuration parameter at least one CPU that member 301 is set, is debugged to the CPU determined；
The chip debugging unit 303, for matching somebody with somebody according to the CPU after the CPU debugging units 302 debugging is corresponding
Parameter is put, the mode of operation to the interconnection chip to be debugged is adjusted.
In above-described embodiment, determine with after the corresponding CPU of interconnection chip to be debugged, according to it is default at least one
CPU configuration parameter, is debugged to the CPU determined, and controls the CPU after debugging to be communicated with interconnection chip foundation to be debugged
Interconnection, then according to the corresponding configuration parameters of CPU after debugging, the mode of operation to interconnection chip to be debugged is adjusted.With
This realizes the automation debugging of interconnection chip, without again using manual type is to CPU configuration parameter and interconnects chip
Mode of operation is matched, so as to improve the debugging efficiency of interconnection chip.
As shown in figure 4, in one embodiment of the invention, the setting unit 301 is further used for setting described in each
CPU configuration parameter distinguishes corresponding operating time；
The CPU debugging units 302 include：Determination subelement 401, control subelement 402 and judgment sub-unit 403；Its
In,
The determination subelement 401, for from the configuration parameter of at least one CPU described in pre-setting, determining one
The current configuration parameters of individual not selected mistake；
The control subelement 402, for the current configuration parameters determined according to the determination subelement 401, control
The running status of the CPU, and record operation durations of the CPU under the running status；When the operation duration reaches
During operating time corresponding with the current configuration parameters, the judgment sub-unit 403 is triggered；
The judgment sub-unit 403, the configuration parameter of the CPU for judging whether not selected mistake, if
It is then to trigger the determination subelement 401, otherwise triggers the chip debugging unit 303.
Herein, from least one default CPU configuration parameter, option and installment parameter, and according to matching somebody with somebody for selecting
State modulator CPU running status is put, and records operation durations of the CPU under the running status, it is long when it is operated to reach pair
During operating time corresponding to the configuration parameter answered, the configuration of a not selected mistake is selected from default configuration parameter again
Parameter, CPU running status is changed with this, until all default configuration parameters are chosen.Thus, it can be matched somebody with somebody according to default
Parameter is put, control CPU runs certain time length under different conditions, realizes the automatic debugging to CPU, pass through without staff
Manual type is debugged one by one to CPU working condition, so as to be conducive to improving the debugging efficiency of interconnection chip.
Specifically, in one embodiment of the invention, the determination subelement 401, for being configured from least one described CPU
In parameter, it is current configuration parameters to determine the first configuration parameter；When receiving the first time triggering of the control subelement 402,
It regard the second configuration parameter as current configuration parameters；When receiving second of triggering of the control subelement 402, the 3rd is matched somebody with somebody
Parameter is put as current configuration parameters, and triggers the chip debugging unit 303；
The control subelement 402, for when first configuration parameter is as the current configuration parameters, controlling institute
State the corresponding quick interconnecting channels QPI of CPU to be run with lower-speed state, and record the QPI under the lower-speed state
First operation duration；When first operation duration reaches the first operating time corresponding with first configuration parameter, the
Once trigger the determination subelement 401；When second configuration parameter is as the current configuration parameters, control is described
QPI is run with fast state, and records the second operation durations of the QPI at high speeds；When the described second operation
When duration reaches the second operating time corresponding with second configuration parameter, the determination subelement 401 is triggered for the second time；
The chip debugging unit 303, for when receiving the triggering of the determination subelement 401, being worked as according to described
Preceding configuration parameter, controls the CPU to set up the interconnection that communicates with the interconnection chip to be debugged.
For example, it is former using field programmable gate array (Field-Programmable Gate Array, FPGA)
When type verification technique is verified to interconnection chip, server is started shooting first upper electric, and loaded FPGA bit streams, be then based on
Intel requirement, CPU operating rate is set using the first configuration parameter, its QPI is operated in low-speed mode, is recorded simultaneously
Its first operation duration.When the first operation duration reaches first operating time corresponding with the first configuration parameter, is utilized
Two configuration parameters set CPU operating rate, its QPI is operated in fast mode.Wherein, QPI operation duration can lead in advance
Experiment is crossed to determine, specifically, when being debugged using manual type to CPU, whenever switchover operation state is needed, server
Input-output system can export corresponding prompt message, now need staff to change CPU configurations according to this prompt message, many
It is secondary that staff can obtain the empirical value of the corresponding operation duration of every kind of working condition with postponing, can using this empirical value as with
The corresponding operating time of parameter is put to be pre-set.
In the process, the corresponding QPI of CPU switch to fast state by lower-speed state, and CPU starting state can be made more steady
Fixed, this is also beneficial to CPU and remains on stabilization during interconnection chip checking, so as to be conducive to interconnecting accurately testing for chip
Card.In addition, when QPI the second operation duration reaches the second operating time, CPU is configured using the 3rd configuration parameter,
It may include CPU processing check figure and memory capacity etc. in this configuration parameter, CPU and interconnection core to be debugged controlled after the completion of configuration
Piece sets up communication interconnection, herein under interconnection state, can treat tune according to configuration parameters such as CPU processing check figures and memory capacity
The mode of operation of examination interconnection chip is debugged.Thus it may be such that CPU enters in stable running status with interconnection chip to be debugged
Row communication interconnection, so as to be conducive to accurately debugging interconnection chip.
In one embodiment of the invention, the chip debugging unit 303, for according to the 3rd configuration parameter, to institute
The running parameter for stating the register of interconnection chip to be debugged is adjusted, and according to the running parameter of the register, determines institute
State the mode of operation of interconnection chip to be debugged.
For example, the CPU configured according to the 3rd configuration parameter processing check figure is 8 cores, inside saves as 4096MB, then can root
The 3rd configuration parameter, the running parameter of the register of interconnection chip to be debugged is adjusted, i.e., by the work of register accordingly
Parameter be also adjusted to it is corresponding with 8 core processors and internal memory 4096MB, then according to the running parameter of the register after regulation,
Interconnection chip to be debugged is adjusted to mode of operation correspondingly, with this CPU Auto-matching after realizing and adjusting, so as to carry
The debugging efficiency of height interconnection chip.
In one embodiment of the invention, the chip debugging unit 303 is further used for the interconnection core to be debugged
After the mode of operation of piece is adjusted, it is determined that with the corresponding checking system of the interconnection chip to be debugged, and test described in controlling
Card system starts.
In the present embodiment, after interconnection chip to be debugged is adjusted, automatically control and interconnection chip pair to be debugged
The checking system answered starts, and then automatically begins to verify interconnection chip, so as to improve the verification efficiency of interconnection chip.
The contents such as the information exchange between each unit, implementation procedure in said apparatus, due to implementing with the inventive method
Example is based on same design, and particular content can be found in the narration in the inventive method embodiment, and here is omitted.
Present invention also offers a kind of computer-readable recording medium, including execute instruction, when described in the computing device of storage control
During execute instruction, the storage control performs the method that any of the above-described embodiment of the invention is provided.
In addition, present invention also offers a kind of storage control, including：Processor, memory and bus；The memory
For storing execute instruction, the processor is connected with the memory by the bus, when storage control operation
When, the execute instruction of memory storage described in the computing device, so that the storage control is performed in the present invention
The method that any embodiment offer is provided.
In summary, each embodiment of the invention at least has the advantages that：
1st, in embodiments of the present invention, determine with after the corresponding CPU of interconnection chip to be debugged, according to it is default extremely
Few CPU configuration parameter, is debugged to the CPU determined, and controls the CPU after debugging to be built with interconnection chip to be debugged
Vertical communication interconnection, then according to the corresponding configuration parameters of CPU after debugging, the mode of operation to interconnection chip to be debugged is adjusted
Section.The automation debugging of interconnection chip is realized with this, without again using manual type to CPU configuration parameter and interconnection core
The mode of operation of piece is matched, so as to improve the debugging efficiency of interconnection chip.
2nd, in embodiments of the present invention, from least one default CPU configuration parameter, option and installment parameter, and root
CPU running status is controlled according to the configuration parameter selected, and records operation durations of the CPU under the running status, when its fortune
When row duration reaches the operating time corresponding to corresponding configuration parameter, again from default configuration parameter select one not by
The configuration parameter selected, CPU running status is changed with this, until all default configuration parameters are chosen.Thus, may be used
According to default configuration parameter, control CPU runs certain time length under different conditions, realizes the automatic debugging to CPU, without
Staff is debugged one by one by manual type to CPU working condition, so as to be conducive to improving the debugging of interconnection chip
Efficiency.
3rd, in embodiments of the present invention, CPU operating rate is set using the first configuration parameter, operates in its QPI low
Fast mode, while recording its first operation duration.When the first operation duration reaches first work corresponding with the first configuration parameter
When making duration, CPU operating rate is set using the second configuration parameter, its QPI is operated in fast mode.In the process,
The corresponding QPI of CPU switch to fast state by lower-speed state, and CPU starting state can be made more stable, and this is also beneficial to CPU and existed
Stabilization is remained on during interconnection chip checking, so as to be conducive to interconnecting the accurate validation of chip.
4th, in embodiments of the present invention, when QPI the second operation duration reaches the second operating time, the 3rd configuration is utilized
Parameter is configured to CPU, controls CPU to set up the interconnection that communicates with interconnection chip to be debugged after the completion of configuration, state is interconnected herein
Under, the mode of operation to interconnection chip to be debugged is debugged.Thus may be such that CPU stable running status with it is to be debugged mutually
Join chip and carry out communication interconnection, so as to be conducive to accurately debugging interconnection chip.
5th, in embodiments of the present invention, according to corresponding 3rd configuration parameters of CPU, to the register of interconnection chip to be debugged
Running parameter be adjusted, then according to the running parameter of the register after regulation, by it is to be debugged interconnection chip adjust to
This corresponding mode of operation, with this CPU Auto-matching after realizing and adjusting, so as to improve the debugging efficiency of interconnection chip.
6th, in embodiments of the present invention, after interconnection chip to be debugged is adjusted, automatically control and interconnection to be debugged
The corresponding checking system of chip starts, and then automatically begins to verify interconnection chip, so as to improve testing for interconnection chip
Demonstrate,prove efficiency.
It should be noted that herein, such as first and second etc relational terms are used merely to an entity
Or operation makes a distinction with another entity or operation, and not necessarily require or imply exist between these entities or operation
Any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant be intended to it is non-
It is exclusive to include, so that process, method, article or equipment including a series of key elements not only include those key elements,
But also other key elements including being not expressly set out, or also include solid by this process, method, article or equipment
Some key elements.In the absence of more restrictions, the key element limited by sentence " including one ", is not arranged
Except also there is other identical factor in the process including the key element, method, article or equipment.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above method embodiment can pass through
Programmed instruction related hardware is completed, and foregoing program can be stored in the storage medium of embodied on computer readable, the program
Upon execution, the step of including above method embodiment is performed；And foregoing storage medium includes：ROM, RAM, magnetic disc or light
Disk etc. is various can be with the medium of store program codes.
It is last it should be noted that：Presently preferred embodiments of the present invention is the foregoing is only, the skill of the present invention is merely to illustrate
Art scheme, is not intended to limit the scope of the present invention.Any modification for being made within the spirit and principles of the invention,
Equivalent substitution, improvement etc., are all contained in protection scope of the present invention.
Claims (10)
1. a kind of server interconnects the automation adjustment method of chip, it is characterised in that including：
Pre-set at least one CPU configuration parameter；
It is determined that CPU corresponding with interconnection chip to be debugged；
According to the configuration parameter of at least one CPU, the CPU determined is debugged；
The CPU after control debugging sets up the interconnection that communicates with the interconnection chip to be debugged；
According to the corresponding configuration parameters of the CPU after debugging, the mode of operation to the interconnection chip to be debugged is adjusted.
2. according to the method described in claim 1, it is characterised in that including：
Further comprise：The configuration parameter for pre-setting each CPU distinguishes corresponding operating time；
Then,
At least one CPU configuration parameter described in the basis, is debugged to the CPU determined, including：
Circulation performs S1 to S3, until the configuration parameter of the CPU in the absence of not selected mistake；
S1：From the configuration parameter of at least one CPU described in pre-setting, determine not selected mistake is currently configured ginseng
Number；
S2：According to the current configuration parameters, the running status of the CPU is controlled, and records the CPU in the running status
Under operation duration；
S3：When the operation duration reaches operating time corresponding with the current configuration parameters, S1 is performed.
3. method according to claim 2, it is characterised in that
The CPU after described S1, S2 and S3, and the control debugging is set up with the interconnection chip to be debugged to communicate mutually
Connection, including：
From at least one described CPU configuration parameter, it is current configuration parameters to determine the first configuration parameter, is currently matched somebody with somebody according to described
Parameter is put, controls the corresponding quick interconnecting channels QPI of the CPU to be run with lower-speed state, and record the QPI described
The first operation duration under lower-speed state；
When first operation duration reaches the first operating time corresponding with first configuration parameter, from described at least one
In individual CPU configuration parameters, the second configuration parameter of selection is used as current configuration parameters；
According to the current configuration parameters, the QPI is controlled to be run with fast state, and record the QPI in high speed shape
The second operation duration under state；
When second operation duration reaches the second operating time corresponding with second configuration parameter, from described at least one
In individual CPU configuration parameters, the 3rd configuration parameter of selection is used as current configuration parameters；
According to the current configuration parameters, the CPU is controlled to set up the interconnection that communicates with the interconnection chip to be debugged.
4. method according to claim 3, it is characterised in that
The corresponding configuration parameters of the CPU according to after debugging, the mode of operation to the interconnection chip to be debugged is carried out
Regulation, including：
According to the 3rd configuration parameter, the running parameter of the register of the interconnection chip to be debugged is adjusted；
According to the running parameter of the register, the mode of operation of the interconnection chip to be debugged is determined.
5. according to any described method in Claims 1-4, it is characterised in that
In the corresponding configuration parameters of the CPU according to after debugging, the mode of operation to the interconnection chip to be debugged is entered
After row regulation, further comprise：
It is determined that with the corresponding checking system of the interconnection chip to be debugged, and control the checking system to start.
6. a kind of server interconnects the automation debugging apparatus of chip, it is characterised in that including：Setting unit, CPU debugging units
With chip debugging unit；Wherein,
The setting unit, the configuration parameter for pre-setting at least one CPU；
The CPU debugging units, for determining CPU corresponding with interconnection chip to be debugged, and are set according to the setting unit
At least one CPU configuration parameter, the CPU determined is debugged；
The chip debugging unit, it is right for according to the corresponding configuration parameters of the CPU after CPU debugging units debugging
The mode of operation of the interconnection chip to be debugged is adjusted.
7. device according to claim 6, it is characterised in that
The setting unit, is further used for setting each CPU configuration parameter to distinguish corresponding operating time；
The CPU debugging units include：Determination subelement, control subelement and judgment sub-unit；Wherein,
The determination subelement, for from the configuration parameter of at least one CPU described in pre-setting, determining that one is not chosen
The current configuration parameters selected；
The control subelement, for the current configuration parameters determined according to the determination subelement, controls the fortune of the CPU
Row state, and record operation durations of the CPU under the running status；Currently match somebody with somebody with described when the operation duration reaches
When putting the corresponding operating time of parameter, the judgment sub-unit is triggered；
The judgment sub-unit, the configuration parameter of the CPU for judging whether not selected mistake, if it is, touching
Send out determination subelement described, otherwise trigger the chip debugging unit.
8. device according to claim 7, it is characterised in that
The determination subelement, for from least one described CPU configuration parameter, determining that the first configuration parameter is to be currently configured
Parameter；When receiving the first time triggering of the control subelement, the second configuration parameter is regard as current configuration parameters；Receive
During second of triggering of the control subelement, using the 3rd configuration parameter as current configuration parameters, and the chip tune is triggered
Try unit；
The control subelement, for when first configuration parameter is as the current configuration parameters, controlling described CPU pairs
The quick interconnecting channels QPI answered is run with lower-speed state, and records first operations of the QPI under the lower-speed state
Duration；When first operation duration reaches the first operating time corresponding with first configuration parameter, trigger for the first time
The determination subelement；When second configuration parameter is as the current configuration parameters, the QPI is controlled with fast state
Run, and record the second operation durations of the QPI at high speeds；When second operation duration reach with it is described
During corresponding second operating time of the second configuration parameter, the determination subelement is triggered for the second time；
The chip debugging unit, for when receiving the triggering of the determination subelement, according to the current configuration parameters,
The CPU is controlled to set up the interconnection that communicates with the interconnection chip to be debugged.
9. device according to claim 8, it is characterised in that
The chip debugging unit, for according to the 3rd configuration parameter, to the register to be debugged for interconnecting chip
Running parameter is adjusted, and according to the running parameter of the register, determines the mode of operation of the interconnection chip to be debugged.
10. according to any described device in claim 6 to 9, it is characterised in that
The chip debugging unit, is further used for after the mode of operation of the interconnection chip to be debugged is adjusted,
It is determined that with the corresponding checking system of the interconnection chip to be debugged, and control the checking system to start.
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