CN107204322A - Multi-chip integrated form CQFP ceramic packages and preparation method thereof - Google Patents
Multi-chip integrated form CQFP ceramic packages and preparation method thereof Download PDFInfo
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- CN107204322A CN107204322A CN201710305163.4A CN201710305163A CN107204322A CN 107204322 A CN107204322 A CN 107204322A CN 201710305163 A CN201710305163 A CN 201710305163A CN 107204322 A CN107204322 A CN 107204322A
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- insulativity
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- 239000000919 ceramic Substances 0.000 title claims abstract description 58
- 238000002360 preparation method Methods 0.000 title abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052573 porcelain Inorganic materials 0.000 claims abstract description 23
- 238000007747 plating Methods 0.000 claims abstract description 19
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010931 gold Substances 0.000 claims abstract description 14
- 229910052737 gold Inorganic materials 0.000 claims abstract description 14
- 238000005245 sintering Methods 0.000 claims abstract description 14
- 239000013081 microcrystal Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000005476 soldering Methods 0.000 claims abstract description 9
- 239000000126 substance Substances 0.000 claims abstract description 6
- 238000003466 welding Methods 0.000 claims abstract description 6
- 239000002002 slurry Substances 0.000 claims description 18
- SWPMTVXRLXPNDP-UHFFFAOYSA-N 4-hydroxy-2,6,6-trimethylcyclohexene-1-carbaldehyde Chemical compound CC1=C(C=O)C(C)(C)CC(O)C1 SWPMTVXRLXPNDP-UHFFFAOYSA-N 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 9
- 239000011261 inert gas Substances 0.000 claims description 9
- 238000003475 lamination Methods 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 238000007766 curtain coating Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 4
- 210000000988 bone and bone Anatomy 0.000 claims description 4
- 238000005219 brazing Methods 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 239000010930 yellow gold Substances 0.000 claims description 4
- 229910001097 yellow gold Inorganic materials 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010276 construction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 206010020741 Hyperpyrexia Diseases 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
The present invention, which is that high-insulativity is low, draws line capacitance multi-chip integrated form CQFP ceramic packages and preparation method thereof, its construction profile size is 25.4mm × 25.4mm × 3.0mm, internal cavity size is 21.8 × 21.8 × 1.25mm, outside lead pitch is 1.27mm, and inner lead spacing is 0.1mm ~ 0.15mm.Porcelain piece part is altogether comprising 8 layers of wiring.Manufacture method, including 1）Use with high insulating microcrystals ceramics as base material；2）It is sintered under sintering schedule；3）Porcelain piece after sintering is subjected to chemical nickel plating；4）Metal lead wire and metal framework are welded on to the relevant position of porcelain piece by ceramic die respectively；5）The shell good to soldering carries out electronickelling plating gold；6）Identical product chip region and lead are realized by localised protection, weld-ring region gold plating thickness is different.Advantage：The ceramic package shell of making can meet different chip welding and the requirement being bonded, and with good air-tightness and reliability, meet the property indices requirement of national military standard.
Description
Technical field
The present invention relates to a kind of high-insulativity high density multi-chip integrated form CQFP ceramic packages and preparation method thereof,
It is to be directed to high-density packages manufacture of casing, belongs to HTCC multi-layer ceramics technical fields.
Background technology
HTCC（HTCC）Technology is that the refractory metal slurrying material such as tungsten is printed in 92%~96% by a kind of use
Aluminum oxide curtain coating green band on, then by lamination, after lamination, burn at a high temperature of 1500 DEG C~1600 DEG C and be integrated altogether
Technology.HTCC（HTCC）With LTCC（LTCC）Compared to high mechanical strength, chemical property is steady
Fixed, coefficient of heat transfer is high and the advantages of the cost of material is low.
Required with the increase of device function and to packing forms are multifarious, occur in that high density multi-chip integrated form is sealed
Assembling structure.The structure can realize multi-chip integrative packaging, and can realize digital-analog integrated function, substantially reduce group
The volume of part, realize miniaturization with it is integrated, packing density is greatly increased, thus obtains the popularization of large area quickly,
And application in the industry is increased.
With the continuous propulsion that electronic component is thinned, minimized, its internal wiring of multi-chip integrated form package casing
Design becomes increasingly complex, and usually requires that higher insulaion resistance draws line capacitance with relatively low, and this is for the selection of material, wiring
Design, processing technology is all greatly to challenge.Using conventional alumina material and multi-layer ceramics technique, break-make is easily caused
Failure, insulaion resistance is relatively low, draws the problem of line capacitance is higher, it would be highly desirable to solve.Simultaneously for the requirement of multi-chip integration packaging,
The coating of chip weld zone and its lead, the coating of weld-ring require different and select coating technology to meet together, it is necessary to develop same layer choosing
The different requirements of one enclosure different zones coating.
The content of the invention
It is proposed by the present invention that to be that a kind of high-insulativity is low draw line capacitance multi-chip integrated form CQFP ceramic packages and its system
Make method, its purpose is to obtain a kind of while having high-insulativity and the multi-chip integrated form CQFP of low lead capacitance ceramics
Shell, improves the electrical property of such high-density packages shell.
The technical solution of the present invention：High-insulativity is low to draw line capacitance multi-chip integrated form CQFP ceramic packages, its
Structure is that appearance and size is 25.4mm × 25.4mm × 3.0mm, and internal cavity size is 21.8 × 21.8 × 1.25mm, and outside is drawn
String pitch is 1.27mm, and inner lead spacing is 0.1mm ~ 0.15mm, and CQFP ceramic package shell porcelain pieces part includes altogether 8 layers
Screen layer between wiring, all 0.12mm apertures of interior bone, signal wire is connected up using grid, and is used between clathrum
Dislocation arrangement wiring, improves insulaion resistance between product wire, while the electric capacity between screen layer is reduced, to reach reduction lead
Between electric capacity purpose.
The low preparation method for drawing line capacitance multi-chip integrated form CQFP ceramic packages of high-insulativity, including following technique step
Suddenly：
1）Use with high insulating microcrystals ceramics as base material, be adapted to the curtain coating green band of HTCC techniques, while using special low resistance
Rate tungsten printing slurry is successively punched, filling perforation as Metal slurry according to resultant metal cabling requirement, printing, is begun to speak,
Operation is cut in lamination, lamination, life；
2）Green part is sintered in the case where being adapted to the sintering schedule that insulating microcrystals ceramics burn altogether with low-resistivity tungsten printing slurry,
Sintering temperature is 1500 DEG C~1600 DEG C（Hydrogen shield）；
3）Porcelain piece after sintering is subjected to chemical nickel plating, nickel layer thickness is 0.7 μm~1.5 μm, is then heat-treated, most hyperpyrexia
Treatment temperature is 780 DEG C~850 DEG C（Inert gas or reducibility gas protection）；Simultaneously by metal lead wire and metal framework in spy
It is heat-treated under fixed heat treating regime, heat treatment temperature is 1000 DEG C~1200 DEG C（Inert gas or reducibility gas are protected
Shield）, furnace cooling；
4）Metal lead wire and metal framework are welded on to the relevant position of porcelain piece by ceramic die respectively, solder is yellow gold
Solder, brazing temperature is 780 DEG C~850 DEG C, and soldering atmosphere is that inert gas or reducibility gas are protected；
5）The shell good to soldering carries out electronickelling plating gold, according to product cavity bonding or the difference of chip welding manner, leads to
Cross by the way of plating Protection glue carries out localised protection plating, realize the chip region nickel layer thickness of inner chamber figure for 1.3 μm~
8.9 μm, layer gold thickness is 0.1 μm~0.5 μm；Lead, weld-ring area nickel layer thickness is 1.3 μm~8.9 μm, and layer gold thickness is 1.3 μ
M~5.7 μm.
Beneficial effects of the present invention：
The integrated CQFP types ceramic package shell of the low lead capacitance high density multi-chip of high-insulativity, CQFP ceramics envelopes can be made
Casing inner lead spacing is that insulaion resistance is more than 1 × 10 between 0.15mm, wire10Ω（500V）, radio-frequency head transmission resistance
Less than 100m Ω, draw line capacitance less than 8pF, different chip welding and the requirement being bonded can be met simultaneously, and with good
Air-tightness and reliability, meet the property indices requirement of national military standard.
Brief description of the drawings
Fig. 1 is multi-chip integrated form CQFP ceramic package front views.
Fig. 2-1,2-2,2-3,2-4,2-5,2-6,2-7,2-8 are multi-chip integrated form CQFP ceramic package wires designs
Figure, 2-1 is the 7th layer of porcelain band wiring diagram；2-2 is the 6th layer of porcelain band wiring diagram；2-3 is the 5th layer of porcelain band wiring diagram；2-4 is the 4th layer
Porcelain band wiring diagram；2-5 is the 3rd layer of porcelain band wiring diagram；2-6 is the 2nd layer of porcelain band wiring diagram；2-7 is the 1st layer of porcelain band wiring diagram；2-8
For the 0th layer of porcelain band wiring diagram.
Embodiment
High-insulativity is low to draw line capacitance multi-chip integrated form CQFP ceramic packages, and its structure is CQFP ceramic package shells
Appearance and size is 25.4mm × 25.4mm × 3.0mm, and internal cavity size is 21.8 × 21.8 × 1.25mm, outside lead pitch
For 1.27mm, inner lead spacing is 0.1mm ~ 0.15mm, as shown in Figure 1.
CQFP ceramic package shell porcelain pieces part is altogether comprising 8 layers of wiring, all 0.12mm apertures of interior bone, signal
Each layer where line uses the screen layer between conventional HTCC Wiring design methods, signal wire to be connected up using grid, and clathrum
Between using dislocation arrangement wiring, at utmost improve product wire between insulaion resistance, while reduce screen layer between electricity
Hold, to reach that the purpose of line capacitance is drawn in reduction, the wiring of crucial figure layer is as shown in Figure 2.
CQFP ceramic package enclosures wire pitch is more than 1 × 10 for insulaion resistance between wire10Ω（500V）, radio frequency
End transmission resistance is less than 100m Ω, draws line capacitance less than 8pF, can meet simultaneously with high-insulativity and can be by big electricity
The requirement of stream, and with good air-tightness and reliability, meet the property indices requirement of national military standard.
The low manufacture method for drawing line capacitance multi-chip integrated form CQFP ceramic packages of high-insulativity, comprises the following steps：
1）Use with high insulating microcrystals ceramics as base material, be adapted to the curtain coating green band of HTCC techniques, while using special low resistance
Rate tungsten printing slurry is successively punched, filling perforation as Metal slurry according to resultant metal cabling requirement, printing, is begun to speak,
Operation is cut in lamination, lamination, life；
2）Green part is sintered in the case where being adapted to the sintering schedule that insulating microcrystals ceramics burn altogether with low-resistivity tungsten printing slurry,
Sintering temperature is 1500 DEG C~1600 DEG C（Hydrogen shield）；
3）Porcelain piece after sintering is subjected to chemical nickel plating, nickel layer thickness is 0.7 μm~1.5 μm, is then heat-treated, most hyperpyrexia
Treatment temperature is 780 DEG C~850 DEG C（Inert gas or reducibility gas protection）；Simultaneously by metal lead wire and metal framework in spy
It is heat-treated under fixed heat treating regime, heat treatment temperature is 1000 DEG C~1200 DEG C（Inert gas or reducibility gas are protected
Shield）, furnace cooling；
4）Metal lead wire and metal framework are welded on to the relevant position of porcelain piece by ceramic die respectively, solder is yellow gold
Solder, brazing temperature is 780 DEG C~850 DEG C, and soldering atmosphere is（Inert gas or reducibility gas protection）；
5）The shell good to soldering carries out electronickelling plating gold, according to product cavity bonding or the difference of chip welding manner, leads to
Cross by the way of plating Protection glue carries out localised protection plating, realize the chip region nickel layer thickness of inner chamber figure for 1.3 μm~
8.9 μm, layer gold thickness is 0.1 μm~0.5 μm；Lead, weld-ring area nickel layer thickness is 1.3 μm~8.9 μm, and layer gold thickness is 1.3 μ
M~5.7 μm；
Described high insulation fine ceramics is black low-loss ceramics, and its dielectric loss is less than 9 × 10-3（DC~40GHz）；
Described low-resistivity tungsten printing slurry is Metal slurry that can be with high insulation fine ceramics co-fire match, and its sheet resistance is small
In 6m Ω/.
Embodiment
High-insulativity is low to draw line capacitance multi-chip integrated form CQFP ceramic packages, and its structure is CQFP ceramic package shells
Appearance and size is 25.4mm × 25.4mm × 3.0mm, and internal cavity size is 21.8 × 21.8 × 1.25mm, outside lead pitch
For 1.27mm, inner lead spacing is 0.15mm, as shown in Figure 1.
CQFP ceramic package shell porcelain pieces part is altogether comprising 8 layers of wiring, all 0.12mm apertures of interior bone, signal
Each layer where line uses the screen layer between conventional HTCC Wiring design methods, signal wire to be connected up using grid, and clathrum
Between using dislocation arrangement wiring, at utmost improve product wire between insulaion resistance, while reduce screen layer between electricity
Hold, to reach that the purpose of line capacitance is drawn in reduction, the wiring of crucial figure layer is as shown in Figure 2.
CQFP ceramic package enclosures wire pitch is more than 1 × 10 for insulaion resistance between wire10Ω（500V）, radio frequency
End transmission resistance is less than 100m Ω, draws line capacitance less than 8pF, can meet simultaneously with high-insulativity and can be by big electricity
The requirement of stream, air-tightness≤1 × 10-3Pa•cm-3/ s, other property indices meet GJB1420B-2011 requirement.
The low manufacture method for drawing line capacitance multi-chip integrated form CQFP ceramic packages of high-insulativity, comprises the following steps：
1）Use with high insulating microcrystals ceramics as base material, be adapted to the curtain coating green band of HTCC techniques, while using special low resistance
Rate tungsten printing slurry is successively punched, filling perforation as Metal slurry according to resultant metal cabling requirement, printing, is begun to speak,
Operation is cut in lamination, lamination, life；
2）Green part is sintered in the case where being adapted to the sintering schedule that insulating microcrystals ceramics burn altogether with low-resistivity tungsten printing slurry,
Sintering temperature is 1500 DEG C~1600 DEG C（Hydrogen shield）；
3）Porcelain piece after sintering is subjected to chemical nickel plating, nickel layer thickness is 0.7 μm~1.5 μm, is then heat-treated, most hyperpyrexia
Treatment temperature is 800 DEG C~850 DEG C（Hydrogen）；Metal lead wire and metal framework are carried out under specific heat treating regime simultaneously
Heat treatment, heat treatment temperature is 1000 DEG C~1200 DEG C（Hydrogen shield）, furnace cooling；
4）Metal lead wire and metal framework are welded on to the relevant position of porcelain piece by ceramic die respectively, solder is yellow gold
Solder, brazing temperature is 800 DEG C~850 DEG C, and soldering protective atmosphere is nitrogen；
5）The shell good to soldering carries out electronickelling plating gold, according to product cavity bonding or the difference of chip welding manner, leads to
Cross by the way of plating Protection glue carries out localised protection plating, realize the chip region nickel layer thickness of inner chamber figure for 1.3 μm~
8.9 μm, layer gold thickness is 0.1 μm~0.3 μm；Lead, weld-ring area nickel layer thickness is 1.3 μm~8.9 μm, and layer gold thickness is 1.3 μ
M~5.7 μm；
Described high insulation fine ceramics is black low-loss ceramics, and its dielectric loss is less than 9 × 10~3（DC~40GHz）；
Described low-resistivity tungsten printing slurry is Metal slurry that can be with high insulation fine ceramics co-fire match, and its sheet resistance is small
In 6m Ω/.
Claims (6)
1. high-insulativity is low to draw line capacitance multi-chip integrated form CQFP ceramic packages, it is characterized in that outside CQFP ceramic package shells
Shape size is 25.4mm × 25.4mm × 3.0mm, and internal cavity size is 21.8 × 21.8 × 1.25mm, and outside lead pitch is
1.27mm, inner lead spacing is 0.1mm ~ 0.15mm.
2. high-insulativity according to claim 1 is low to draw line capacitance multi-chip integrated form CQFP ceramic packages, its feature
It is that CQFP ceramic package shell porcelain pieces part is connected up altogether comprising 8 layers, all 0.12mm apertures of interior bone, signal wire place
Each layer uses the screen layer between conventional HTCC Wiring design methods, signal wire to be connected up using grid, and is adopted between clathrum
With dislocation arrangement wiring.
3. high-insulativity according to claim 1 is low to draw line capacitance multi-chip integrated form CQFP ceramic packages, its feature
It is that CQFP ceramic package enclosures wire pitch is more than 1 × 10 for insulaion resistance between wire10Ω（500V）, radio-frequency head transmission
Resistance is less than 100m Ω, draws line capacitance less than 8pF, at the same meet with high-insulativity and can by the requirement of high current,
And with good air-tightness and reliability, meet the property indices requirement of national military standard.
4. the low manufacturer for drawing line capacitance multi-chip integrated form CQFP ceramic packages of high-insulativity as claimed in claim 1
Method, it is characterized in that comprising the following steps：
1）Use with high insulating microcrystals ceramics as base material, be adapted to the curtain coating green band of HTCC techniques, while using low-resistivity tungsten
Printing slurry is successively punched, filling perforation as Metal slurry according to resultant metal cabling requirement, printing, is begun to speak, and is folded
Operation is cut in piece, lamination, life；
2）Green part is sintered in the case where being adapted to the sintering schedule that insulating microcrystals ceramics burn altogether with low-resistivity tungsten printing slurry,
Sintering temperature be 1500 DEG C~1600 DEG C, hydrogen shield；
3）Porcelain piece after sintering is subjected to chemical nickel plating, nickel layer thickness is 0.7 μm~1.5 μm, is then heat-treated, and is heat-treated
Temperature is 780 DEG C~850 DEG C, inert gas or reducibility gas protection；While by metal lead wire with metal framework specific
It is heat-treated under heat treating regime, heat treatment temperature is 1000 DEG C~1200 DEG C, inert gas or reducibility gas protection, with
Stove is cooled down；
4）Metal lead wire and metal framework are welded on to the relevant position of porcelain piece by ceramic die respectively, solder is yellow gold
Solder, brazing temperature is 780 DEG C~850 DEG C, and soldering atmosphere is that inert gas or reducibility gas are protected；
5）The shell good to soldering carries out electronickelling plating gold, according to product cavity bonding or the difference of chip welding manner, leads to
Cross by the way of plating Protection glue carries out localised protection plating, realize the chip region nickel layer thickness of inner chamber figure for 1.3 μm~
8.9 μm, layer gold thickness is 0.1 μm~0.5 μm；Lead, weld-ring area nickel layer thickness is 1.3 μm~8.9 μm, and layer gold thickness is 1.3 μ
M~5.7 μm.
5. the low manufacturer for drawing line capacitance multi-chip integrated form CQFP ceramic packages of high-insulativity as claimed in claim 4
Method, it is characterized in that described high insulating microcrystals ceramics are black low-loss ceramics, its dielectric loss is less than 9 × 10-3（DC~
40GHz）.
6. the low manufacturer for drawing line capacitance multi-chip integrated form CQFP ceramic packages of high-insulativity as claimed in claim 4
Method, it is characterized in that Metal slurry of the described low-resistivity tungsten printing slurry for the fine ceramics co-fire match that can be insulated with height,
Its sheet resistance is less than 6m Ω/.
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| CN201710305163.4A CN107204322A (en) | 2017-05-03 | 2017-05-03 | Multi-chip integrated form CQFP ceramic packages and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109457103A (en) * | 2018-11-09 | 2019-03-12 | 中国电子科技集团公司第五十五研究所 | A kind of electronic encapsulation shell lead fatigue resistance Enhancement Method |
| CN109494198A (en) * | 2018-12-05 | 2019-03-19 | 河北中瓷电子科技有限公司 | Ceramic package shell preparation method and ceramic package shell |
| CN111106070A (en) * | 2019-12-04 | 2020-05-05 | 中国电子科技集团公司第十三研究所 | Ceramic packaging shell convenient for electroplating and electroplating method |
| CN113345842A (en) * | 2021-04-20 | 2021-09-03 | 中国电子科技集团公司第十三研究所 | Ceramic four-side flat package shell and ceramic four-side flat package device |
| CN114184841A (en) * | 2021-11-11 | 2022-03-15 | 中国电子科技集团公司第五十五研究所 | Method for measuring lead resistance of packaging shell |
| CN115283774A (en) * | 2022-07-29 | 2022-11-04 | 中国电子科技集团公司第五十五研究所 | Treatment process of Cu-Cr-Zr alloy lead for packaging shell |
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| CN109494198A (en) * | 2018-12-05 | 2019-03-19 | 河北中瓷电子科技有限公司 | Ceramic package shell preparation method and ceramic package shell |
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| CN114184841A (en) * | 2021-11-11 | 2022-03-15 | 中国电子科技集团公司第五十五研究所 | Method for measuring lead resistance of packaging shell |
| CN114184841B (en) * | 2021-11-11 | 2023-11-24 | 中国电子科技集团公司第五十五研究所 | Method for measuring lead resistance of packaging shell |
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