CN107181403A - Differential charge pump circuit - Google Patents
Differential charge pump circuit Download PDFInfo
- Publication number
- CN107181403A CN107181403A CN201710395952.1A CN201710395952A CN107181403A CN 107181403 A CN107181403 A CN 107181403A CN 201710395952 A CN201710395952 A CN 201710395952A CN 107181403 A CN107181403 A CN 107181403A
- Authority
- CN
- China
- Prior art keywords
- fet
- electric capacity
- clock signal
- signal input
- charge pump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003071 parasitic effect Effects 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 claims abstract description 10
- 230000000694 effects Effects 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 4
- 230000005611 electricity Effects 0.000 description 9
- 230000001052 transient effect Effects 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a kind of differential charge pump circuit, including Input voltage terminal, first clock signal input terminal, second clock signal input part, the first FET being connected respectively with Input voltage terminal, second FET, 3rd FET and the 4th FET, the first electric capacity and the 3rd electric capacity being connected with the first clock signal input terminal, the second electric capacity and the 4th electric capacity being connected with second clock signal input part, 5th FET, 6th FET, output capacitance and output voltage terminal, first clock signal input terminal and second clock signal input part input a pair of differential clock signals, differential charge pump circuit passes through the first FET of driving and the grid of the second FET, reduce the size of parasitic capacitance, can also be that the 5th FET and the 6th FET provide stable driving voltage simultaneously, improve the output voltage of output voltage terminal, output current and conversion efficiency.The present invention can export bigger voltage, electric current and Geng Gao conversion efficiency.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of differential charge pump circuit.
Background technology
Charge pump circuit is commonly used to produce the output voltage higher than input voltage, or for providing negative voltage.Charge pump
Circuit structure is simple, area is smaller, and efficiency is higher.Nowadays, how to improve output voltage, output current and conversion efficiency is electric charge
The developing direction of pump circuit design.
Differential charge pump circuit is developed into from most basic charge pump circuit, its current driving ability is doubled.It is existing
Often parasitic capacitance is larger, electric charge has more loss and controlling switch tube voltage is changed for some differential charge pump circuits, so that
Cause to reduce output voltage, output current and conversion efficiency.Particularly in negative voltage charge pump circuit, if electric from input
Pressure side, which comes in first to switch, to be realized with p-type FET (PMOS), and its usual breadth length ratio (W/L) is all than larger, therefore
There is bigger influence to output voltage, output current and conversion efficiency.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of differential charge pump circuit.
The purpose of the present invention is achieved through the following technical solutions：A kind of differential charge pump circuit, including input electricity
Pressure side, the first clock signal input terminal, second clock signal input part, first effect being connected respectively with the Input voltage terminal
Ying Guan, the second FET, the 3rd FET and the 4th FET, be connected with first clock signal input terminal
One electric capacity and the 3rd electric capacity, the second electric capacity and the 4th electric capacity that are connected with the second clock signal input part and described first
The 5th connected FET of electric capacity, the 6th FET being connected with second electric capacity and the 5th FET and
The connected output capacitance of 6th FET and output voltage terminal, first clock signal input terminal and when described second
Clock signal input part input a pair of differential clock signals, the differential charge pump circuit by drive first FET and
The grid of second FET, reduces the size of parasitic capacitance, is the 5th FET and the 6th field-effect
Pipe provides stable driving voltage, improves output voltage, output current and the higher conversion efficiency of output voltage terminal.
First clock signal input terminal is connected with one end of first electric capacity and one end of the 3rd electric capacity, institute
Second clock signal input part is stated with one end of second electric capacity and one end of the 4th electric capacity to be connected.
The draining of the other end of first electric capacity and first FET, the drain electrode of the 5th FET and
The grid of 6th FET is connected；It is the draining of the other end of second electric capacity and second FET, described
The drain electrode of the grid of 5th FET and the 6th FET is connected.
The other end of 3rd electric capacity and the grid of second FET, the drain electrode of the 3rd FET,
The grid of 4th FET is connected；It is the other end of 4th electric capacity and the grid of first FET, described
The drain electrode of the grid of 3rd FET and the 4th FET is connected.
Source electrode, the source electrode of the 3rd FET of the source electrode of first FET and second FET
And the source electrode of the 4th FET connects the Input voltage terminal jointly；The source electrode of 5th FET and described the
One end of the source electrode of six FETs and the output capacitance connects the output voltage terminal jointly, the output capacitance it is another
End ground connection.
First FET, second FET, the 3rd FET and the 4th FET
For p-type FET, the 5th FET is N-type FET with the 6th FET.
The beneficial effects of the invention are as follows：The influence of node parasitic capacitance on main driving path can be substantially reduced, speed is more
It hurry up, the control voltage of Simultaneous Switching pipe will not be fallen so that the impedance of switching tube is always held at minimum value, under the same conditions
Bigger voltage, electric current and conversion efficiency can be exported.
Brief description of the drawings
Fig. 1 is the particular circuit configurations figure of differential charge pump circuit of the present invention.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in figure 1, differential charge pump circuit of the present invention includes Input voltage terminal VIN, the first clock signal input terminal
CLK, second clock signal input part CLKB, the first FET M1 being connected respectively with Input voltage terminal VIN, the second field-effect
Pipe M2, the 3rd FET M3 and the 4th FET M4, the first electric capacity C1 being connected with the first clock signal input terminal CLK and
3rd electric capacity C3, the second electric capacity C2 and the 4th electric capacity C4 that are connected with second clock signal input part CLKB and the first electric capacity C1
Connected the 5th FET M5, the 6th FET M6 being connected with the second electric capacity C2, with the 5th FET M5 and the 6th
Output capacitance C5 and output voltage terminal VOUT connected FET M6.Wherein, during the first clock signal input terminal CLK and second
Clock signal input part CLKB inputs a pair of differential clock signals.
The physical circuit annexation of differential charge pump circuit of the present invention is as follows：First clock signal input terminal CLK and
One electric capacity C1 one end and the 3rd electric capacity C3 one end are connected, second clock signal input part CLKB and the second electric capacity C2 one end
And the 4th electric capacity C4 one end be connected；The first electric capacity C1 other end and the first FET M1 drain electrode, the 5th FET
M5 drain electrode and the 6th FET M6 grid are connected, and tie point is node n1；The second electric capacity C2 other end and second
Effect pipe M2 drain electrode, the drain electrode of the 5th FET M5 grid and the 6th FET M6 are connected, and tie point is node n2；
The 3rd electric capacity C3 other end and the second FET M2 grid, the 3rd FET M3 drain electrode, the 4th FET M4
Grid be connected, tie point be node n3；The 4th electric capacity C4 other end and the first FET M1 grid, the 3rd field-effect
Pipe M3 grid and the 4th FET M4 drain electrode are connected, and tie point is node n4；First FET M1 source electrode and
Two FET M2 source electrode, the 3rd FET M3 source electrode and the 4th FET M4 source electrode connects input voltage jointly
Hold VIN；5th FET M5 source electrode is connected defeated jointly with the 6th FET M6 source electrode and output capacitance C5 one end
Go out voltage end VOUT, output capacitance C5 other end ground connection.
Wherein, in the present embodiment, the first FET M1, the second FET M2, the 3rd FET M3 and the 4th
FET M4 is p-type FET, and the 5th FET M5 and the 6th FET M6 are N-type FET, in other realities
Apply in example, above-mentioned FET can realize the component of identical function for other structures, however it is not limited to this.
The operation principle of differential charge pump circuit of the present invention is as follows：
In original state, the first clock signal input terminal CLK input low level clock signals, second clock signal input part
CLKB input high level clock signals, now, Input voltage terminal VIN, output voltage terminal VOUT, at node n1, n2, n3, n4
Voltage is identical, and initial voltage is 0V.
When the first clock signal input terminal CLK voltage clock signal rises, second clock signal input part CLKB's
The voltage of clock signal declines, because the second electric capacity C2 and the 4th electric capacity C4 two ends voltage are unable to transient changing, when second
When clock signal input part CLKB voltage is driven to 0V, the voltage at node n2, n4 is forced to drop to negative clock power electricity
Pressure-VCC；Because the parasitic capacitance at node n2 is reduced, the parasitism electricity that its magnitude of voltage can be at closer-VCC, and node n4
Appearance is smaller, negative supply voltage-VDD can be faster reached so that the first FET M1 fast conductings, the voltage at node n1
Move Input voltage terminal VIN level to；So that conducting quick and stable the 6th FET M6, so that the negative electricity at node n2
Lotus is transferred to output capacitance C5；Output voltage terminal VOUT negative voltage is gradually risen, and the negative voltage at node n2 is gradually reduced, directly
Voltage to node n2 is equal with output voltage terminal VOUT voltage；Simultaneously because the voltage at node n4 will not follow node
Voltage reduction at n2, can be always maintained at the first FET M1 and the 6th FET M6 conduction impedance in minimum value not
Become.
When the first clock signal input terminal CLK voltage clock signal declines, second clock signal input part CLKB's
The voltage of clock signal rises, because the first electric capacity C1 and the 3rd electric capacity C3 two ends voltage are unable to transient changing, when first
When clock signal input part CLK voltage is driven to 0V, the voltage at node n1, n3 is forced to drop to-VCC；Due to node n1
The parasitic capacitance at place is reduced, and the parasitic capacitance that its magnitude of voltage can be at closer-VCC, and node n3 is smaller, can faster arrive
Up to-VCC so that the second FET M2 fast conductings, the voltage at node n2 is moved to Input voltage terminal VIN level；So that
Conducting quick and stable 5th FET M5, so that the negative electrical charge at node n1 is transferred to output capacitance C5；Output electricity
Pressure side VOUT negative voltage is gradually risen, and the negative voltage at node n1 is gradually reduced, the voltage at node n1 and output electricity
Pressure side VOUT voltage is equal；Simultaneously because the voltage at node n3 will not follow the voltage at node n1 to reduce, can be always
Keep the second FET M2 and the 5th FET M5 conduction impedance constant in minimum value.Arrived when next clock cycle
When again repeat above step.
As seen from the above analysis, differential charge pump circuit of the present invention reduces the parasitic capacitance at node n1, n2, often
One clock cycle electric charge of transfer is：
Wherein, C1 represents the first electric capacity C1 capacitance, and C2 represents the first electric capacity C2 capacitance, and VCC represents clock electricity
Source voltage, Cn1 represents the parasitic capacitance value at node n1, and Cn2 represents the parasitic capacitance value at node n2.It can thus be seen that
Reduce after the parasitic capacitance value at node n1, n2, the electric charge of a clock cycle transfer is more.
And in differential charge pump circuit of the present invention, voltage at node n3, n4 will not with output voltage terminal VOUT electricity
Buckling and change, so as to provide stable driving voltage to the first FET M1 and the second FET M2 so that node
Voltage at n1, n2 is equal all with Input voltage terminal VIN voltage, and then to the 5th FET M5 and the 6th FET M6
Stable driving voltage is provided.
Differential charge pump circuit of the present invention is by increasing an auxiliary branch, the first FET M1 of driving and second effect
Should pipe M2 grid, reducing the voltage at the size of parasitic capacitance at main driving path node n1, n2, node n3, n4 will not fall
Fall, keep the first FET M1 and the second FET M2 conduction impedance always to be minimum value, so as to improve output electricity
Pressure, output current and conversion efficiency.
In summary, differential charge pump circuit of the present invention can substantially reduce the influence of parasitic capacitance, speed faster, simultaneously
The control voltage of switching tube will not be fallen so that the impedance of switching tube is always held at minimum value, under the same conditions can be with defeated
Go out bigger voltage, electric current and conversion efficiency.
Claims (6)
1. a kind of differential charge pump circuit, it is characterised in that：The differential charge pump circuit includes Input voltage terminal, the first clock
Signal input part, second clock signal input part, the first FET being connected respectively with the Input voltage terminal, second effect
Ying Guan, the 3rd FET and the 4th FET, the first electric capacity and the 3rd being connected with first clock signal input terminal
Electric capacity, the second electric capacity being connected with the second clock signal input part and the 4th electric capacity, be connected with first electric capacity
Five FETs, the 6th FET being connected with second electric capacity and the 5th FET and the 6th effect
Connected output capacitance and output voltage terminal, first clock signal input terminal and the second clock signal input part should be managed
A pair of differential clock signals are inputted, the differential charge pump circuit is by driving first FET and second effect
Should pipe grid, reduce the size of parasitic capacitance, be that the 5th FET and the 6th FET are provided stably
Driving voltage, improves output voltage, output current and the higher conversion efficiency of output voltage terminal.
2. differential charge pump circuit according to claim 1, it is characterised in that：First clock signal input terminal and institute
State one end of the first electric capacity and one end of the 3rd electric capacity to be connected, the second clock signal input part and second electric capacity
One end and the 4th electric capacity one end be connected.
3. differential charge pump circuit according to claim 2, it is characterised in that：The other end of first electric capacity with it is described
The grid of the draining of first FET, the drain electrode of the 5th FET and the 6th FET is connected；Described
The draining of the other end of two electric capacity and second FET, the grid of the 5th FET and the 6th field-effect
The drain electrode of pipe is connected.
4. differential charge pump circuit according to claim 3, it is characterised in that：The other end of 3rd electric capacity with it is described
The grid of second FET, the draining of the 3rd FET, the grid of the 4th FET are connected；Described 4th
Grid, the grid and the 4th FET of the 3rd FET of the other end of electric capacity and first FET
Drain electrode be connected.
5. differential charge pump circuit according to claim 4, it is characterised in that：The source electrode of first FET and institute
The source electrode, the source electrode of the 3rd FET and the source electrode of the 4th FET for stating the second FET connect institute jointly
State Input voltage terminal；The one of the source electrode of 5th FET and the source electrode of the 6th FET and the output capacitance
End connects the output voltage terminal, the other end ground connection of the output capacitance jointly.
6. differential charge pump circuit according to claim 1, it is characterised in that：First FET, described second
FET, the 3rd FET are p-type FET, the 5th FET and institute with the 4th FET
The 6th FET is stated for N-type FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710395952.1A CN107181403A (en) | 2017-05-31 | 2017-05-31 | Differential charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710395952.1A CN107181403A (en) | 2017-05-31 | 2017-05-31 | Differential charge pump circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107181403A true CN107181403A (en) | 2017-09-19 |
Family
ID=59835161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710395952.1A Pending CN107181403A (en) | 2017-05-31 | 2017-05-31 | Differential charge pump circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107181403A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003284325A (en) * | 2002-03-20 | 2003-10-03 | Sanyo Electric Co Ltd | Charge pump circuit and display unit having charge pump circuit |
| US20050213781A1 (en) * | 2004-03-26 | 2005-09-29 | Sanyo Electric Co., Ltd. | Charge pump circuit |
| CN1914574A (en) * | 2003-12-19 | 2007-02-14 | 爱特梅尔股份有限公司 | High efficiency, low cost, charge pump circuit |
| CN104796171A (en) * | 2015-03-25 | 2015-07-22 | 广州钧衡微电子科技有限公司 | Control circuit applied to SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) radiofrequency switches |
| US20160118879A1 (en) * | 2014-10-23 | 2016-04-28 | Infineon Technologies Ag | Charge pump |
| CN106341041A (en) * | 2015-07-07 | 2017-01-18 | 三星电子株式会社 | Charge pump, image sensor and control method thereof |
| CN206878701U (en) * | 2017-05-31 | 2018-01-12 | 成都锐成芯微科技股份有限公司 | Differential charge pump circuit |
-
2017
- 2017-05-31 CN CN201710395952.1A patent/CN107181403A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003284325A (en) * | 2002-03-20 | 2003-10-03 | Sanyo Electric Co Ltd | Charge pump circuit and display unit having charge pump circuit |
| CN1914574A (en) * | 2003-12-19 | 2007-02-14 | 爱特梅尔股份有限公司 | High efficiency, low cost, charge pump circuit |
| US20050213781A1 (en) * | 2004-03-26 | 2005-09-29 | Sanyo Electric Co., Ltd. | Charge pump circuit |
| US20160118879A1 (en) * | 2014-10-23 | 2016-04-28 | Infineon Technologies Ag | Charge pump |
| CN104796171A (en) * | 2015-03-25 | 2015-07-22 | 广州钧衡微电子科技有限公司 | Control circuit applied to SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) radiofrequency switches |
| CN106341041A (en) * | 2015-07-07 | 2017-01-18 | 三星电子株式会社 | Charge pump, image sensor and control method thereof |
| CN206878701U (en) * | 2017-05-31 | 2018-01-12 | 成都锐成芯微科技股份有限公司 | Differential charge pump circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104167918A (en) | DC-DC converter of high transformation ratio | |
| CN207442695U (en) | A kind of charge pump sequential control circuit and charge pump circuit | |
| CN103532375B (en) | Boosting type charge pump | |
| CN108429445A (en) | A kind of soft starting circuit applied to charge pump | |
| CN101976940A (en) | Drive bootstrap circuit for switching tube of switching power supply converter | |
| CN107707117A (en) | A kind of charge pump sequential control circuit and charge pump circuit | |
| CN109921779B (en) | Half-bridge circuit through protection circuit | |
| CN108809084B (en) | Charge pump circuit | |
| CN206878701U (en) | Differential charge pump circuit | |
| CN109194126A (en) | A kind of power supply switch circuit | |
| CN101557221A (en) | Drive integrated circuit and motor driver comprising the circuit | |
| CN108322043A (en) | A kind of single-stage active impedance network DC-DC converter | |
| CN107493022B (en) | Low-voltage efficient charge pump | |
| CN208623548U (en) | A kind of charge pump circuit | |
| CN207150411U (en) | One kind input Pressure and Control circuit | |
| CN107181403A (en) | Differential charge pump circuit | |
| CN104811033A (en) | Charge pump circuit suitable for low voltage operation | |
| CN101213460B (en) | A peak or zero current comparator | |
| CN102571069B (en) | Single-power-supply positive and negative logic conversion circuit | |
| CN109787612A (en) | A kind of novel wide scope sub-threshold level shifter circuit | |
| CN107482884A (en) | One kind input Pressure and Control circuit | |
| CN108429454A (en) | A kind of biswitch DC-DC converter | |
| CN101212221B (en) | Buffer in ultra-low power consumption integrated circuit | |
| CN105227166B (en) | A kind of metal-oxide-semiconductor back gate voltage control circuit | |
| CN107546976A (en) | Charge pump circuit and charge pump |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170919 |
|
| WD01 | Invention patent application deemed withdrawn after publication |