CN103532375B - Boosting type charge pump - Google Patents
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- CN103532375B CN103532375B CN201310431444.6A CN201310431444A CN103532375B CN 103532375 B CN103532375 B CN 103532375B CN 201310431444 A CN201310431444 A CN 201310431444A CN 103532375 B CN103532375 B CN 103532375B
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Abstract
A kind of boosting type charge pump comprises that at least one first electric charge draws unit, one second electric charge draws unit and export storage capacitance, first electric charge draws unit and comprises the first charge pump capacitor, the first output PMOS transistor and at least one charging clock signal end, and the second electric charge draws unit and comprises the second charge pump capacitor, the second output PMOS transistor and at least one charging clock signal end; First output PMOS transistor and second exports PMOS transistor and interacts, and conducting or cut-out according to charging clock signal respectively, thus first, second charge pump capacitor is periodically to the charging of output storage capacitance.Drawn in unit by each electric charge and export the mutual ingenious connection of PMOS transistor, effectively reduce design complexities, obtain identical output voltage performance simultaneously, effectively meet designing points requirement; In one-period, at least twice to the charging of output storage capacitance, and its ripple is more much smaller than traditional structure, obtains more excellent output characteristic.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, particularly relate to a kind of structure simple, the boosting type charge pump of excellent performance.
Background technology
Charge pump circuit is widely used in analog circuit, and it is primarily of electric capacity, switch, and non-overlapping clock and level shifting circuit composition, wherein the most important thing is the realization of electric capacity and switch.As shown in Figure 1, adopt electric capacity and diode to realize, ck1, ck2 are a pair non-overlapping clock to existing simple charge pump.The operation principle of this charge pump is: suppose that the conducting voltage of diode is vt, as ck1=0, and D1 conducting, va=vin-vt when stable state; Work as ck1=vin, ck2=0, va=2vin-vt, simultaneously D2 conducting, vb=2vin-2vt when stable state.Va, vb, vcp voltage is progressively elevated in this way, can select the number of electric capacity and diode according to actual needs.This structural circuit is simple, but circuit loss is larger, and every one-level fixed voltage loss is vt.
As shown in Figure 2, the switch of this charge pump MOS switch replaces diode to the 2 times of type charge pump constructions improved, and can have less voltage loss and settling time faster like this.The operation principle of this charge pump is: pm1, nm1 conducting, va=vin, vb=0; Pm2, pm3 conducting, vb=vin, because electric capacity c1 voltage can not suddenly change, va=2vin conducting, therefore va is charged to electric capacity c2 by pm2, and during stable state, vcp=2vin(supposes do not have load here, under MOS switch does not have lossy situation).
There is following difficult point in the design of 2 times of type charge pump constructions of this improvement:
1. the consideration of reliability: because internal node exists instantaneous pressure, therefore needs duration and the amplitude of considering this node high pressure conditions, ensures that each coupled device is all operated in safe bias state;
2. the selection of substrate electric potential: pm1, pm2 are PMOS switch, its substrate electric potential will select maximum potential to be connected, but vin, va, the process that vcp voltage relationship is set up at charge pump is uncertain, therefore need adopt voltage selector to select maximum potential supply pm1 and pm2(as shown in Figure 2 voltage selector be made up of a comparator comp and two switch sw1, a sw2);
The control of the grid-control voltage of 3.MOS switch: vb voltage range 0 ~ vin, therefore pm3 and nm1 needs the voltage transmitting and block to be 0 ~ vin, the logic that its grid voltage adopts 0 ~ vin to control; Pm1 needs to transmit vin, blocks 2vin, and therefore its grid control logic needs 0 ~ 2vin; Pm2 is also similar; Therefore need extra level shift circuit to realize the logic control of grid different potentials.
As can be seen from above-mentioned analysis, 2 times of type charge pumps of existing improvement need extra circuit to meet designing points requirement, so not only increase design difficulty and too increase design cost and power consumption, this structure is providing for single capacitor is powered between charged region for load simultaneously, and therefore ripple is relative also larger.Therefore, need a kind of design complexities that can simplify charge pump, obtain identical output voltage performance and the charge pump construction of less output ripple simultaneously.
Summary of the invention
Technical problem to be solved by this invention is, a kind of boosting type charge pump is provided, the design solving charge pump in prior art needs extra circuit to meet designing points requirement, increases design difficulty and too increases design cost and power consumption, and the problem that ripple is relative also larger.
In order to solve the problem, the invention provides a kind of boosting type charge pump, comprise that at least one first electric charge draws unit, one second electric charge draws unit and export storage capacitance, described first electric charge draws unit and comprises the first charge pump capacitor, the first output PMOS transistor and at least one charging clock signal end, and described second electric charge draws unit and comprises the second charge pump capacitor, the second output PMOS transistor and at least one charging clock signal end; Described first exports the source electrode of PMOS transistor is connected with described first charge pump capacitor, and grid is connected with described second charge pump capacitor, and draining is connected with described output storage capacitance connects charge pump voltage output simultaneously, and substrate is connected with a voltage selecting circuit; Described second source electrode exporting PMOS transistor is connected with described second charge pump capacitor and is connected to the grid that described first exports PMOS transistor, described second grid exporting PMOS transistor is connected with described first charge pump capacitor and is connected to the source electrode that described first exports PMOS transistor, described second drain electrode exporting PMOS transistor is connected with described output storage capacitance and connects described charge pump voltage output simultaneously, and the described second substrate exporting PMOS transistor is connected with described voltage selecting circuit and the described first substrate exporting PMOS transistor respectively; When described first exports PMOS transistor according to charging clock signal conduction, described second exports PMOS transistor cuts off, and the first charge pump capacitor is to the charging of output storage capacitance; When described second exports PMOS transistor according to charging clock signal conduction, described first exports PMOS transistor cuts off, and the second charge pump capacitor exports storage capacitance charging.
The invention has the advantages that, drawn in unit by each electric charge and export the mutual ingenious connection of PMOS transistor, effectively reduce design complexities, obtain identical output voltage performance simultaneously, effectively meet designing points requirement; And repeatedly to the charging of output storage capacitance in one-period, its ripple is also much smaller than traditional structure, obtains more excellent output characteristic.
Accompanying drawing explanation
Fig. 1, the circuit diagram of existing simple charge pump;
Fig. 2, the circuit diagram of 2 times of type charge pumps of improvement;
Fig. 3, the circuit diagram of an execution mode of boosting type charge pump of the present invention.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to boosting type charge pump provided by the invention.
With reference to accompanying drawing 3, the circuit diagram of an execution mode of boosting type charge pump of the present invention, described boosting type charge pump comprises at least one first electric charge and draws unit 1,1 second electric charge and draw unit 2, export storage capacitance C4 and voltage selecting circuit 3.Wherein, the crosspoint that in figure, wire is connected adds black circle and represents.
Described first electric charge draws unit 1 and comprises the first charge pump capacitor c1, the first output PMOS transistor pm3 and at least one charging clock signal end 11, and described second electric charge draws unit 2 and comprises the second charge pump capacitor c2, the second output PMOS transistor pm4 and at least one charging clock signal end 21.
Described first source electrode exporting PMOS transistor pm3 is connected with described first charge pump capacitor c1, grid is connected with described second charge pump capacitor c2, drain electrode is connected with described output storage capacitance c4 and meets charge pump voltage output vcp simultaneously, and substrate is connected with voltage selecting circuit 3.After clock signal end 11 receives charging clock signal when charging, first exports PMOS transistor pm3 conducting, first charge pump capacitor c1 exports PMOS transistor pm3 to output storage capacitance c4 charging by first, thus the output voltage of charge pump voltage output vcp is raised.
Described second source electrode exporting PMOS transistor pm4 is connected with described second charge pump capacitor c2 and is connected to the grid that described first exports PMOS transistor pm3, described second grid exporting PMOS transistor pm4 is connected with described first charge pump capacitor c1 and is connected to the source electrode that described first exports PMOS transistor pm3, described second drain electrode exporting PMOS transistor pm4 is connected with described output storage capacitance c4 and meets described charge pump voltage output vcp simultaneously, described second substrate exporting PMOS transistor pm4 is connected with described voltage selecting circuit 3 and the described first substrate exporting PMOS transistor pm3 respectively.After clock signal end 21 receives charging clock signal when charging, second exports PMOS transistor pm4 conducting, second charge pump capacitor c2 exports PMOS transistor pm4 to output storage capacitance c4 charging by second, thus the output voltage of charge pump voltage output vcp is raised.
When described first exports PMOS transistor pm3 according to charging clock signal conduction, described second exports PMOS transistor pm4 cuts off, and the first charge pump capacitor c1 is to output storage capacitance c4 charging; When described second exports PMOS transistor pm4 according to charging clock signal conduction, described first exports PMOS transistor pm3 cuts off, and the second charge pump capacitor c2 exports storage capacitance c4 charging.Also namely described first output PMOS transistor pm3 and described second exports PMOS transistor pm4 conducting or cut-out according to charging clock signal respectively, thus the first charge pump capacitor c1 and the second charge pump capacitor c2 periodically charges to exporting storage capacitance c4.Export the ingenious of PMOS transistor pm4 by described first output PMOS transistor pm3 and described second to be connected, effectively reduce design complexities, obtain identical output voltage performance simultaneously; And due to boosting type charge pump of the present invention in one-period repeatedly to output storage capacitance c4 charging, its ripple is also much smaller than traditional structure, obtains more excellent output characteristic.
Described first electric charge draws unit 1 and comprises one first nmos switch nm1 further, the source electrode of described first nmos switch nm1 is connected with substrate and accesses charge pump voltage input vin, grid is connected with described second charge pump capacitor c2, drains and to be connected with described first charge pump capacitor c1 and to be connected to the source electrode that described first exports PMOS transistor pm3.The substrate of the first nmos switch nm1 is connected to its source, in the steady state, source all can be considered potential minimum, and in process of establishing, there is forward bias and conducting in substrate and drain terminal diode, but this diode leakage current promotes that drain terminal voltage accelerates close to input terminal voltage, is therefore useful diode leakage current, allow to exist at circuit establishment stage.
Described first electric charge draws unit 1 and comprises one first PMOS switch pm1 and the 3rd nmos switch nm3 further; The source electrode of described first PMOS switch pm1 is connected with substrate and accesses charge pump voltage input vin, grid is connected with a charging clock signal end ck_pm1, drains and to be connected with the drain electrode of described 3rd nmos switch nm3 and to be connected to by described first charge pump capacitor c1 the source electrode that described first exports PMOS transistor pm3; The source electrode of described 3rd nmos switch nm3 is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal end ck_nm3, drains and to be connected with the drain electrode of described first PMOS switch pm1 and to be connected to the drain electrode of described first nmos switch nm1 by described first charge pump capacitor c1.The voltage change range of the drain electrode of the first PMOS switch pm1 and the drain electrode of the 3rd nmos switch nm3 is between 0 ~ input voltage, therefore, first PMOS switch pm1 and the 3rd nmos switch nm3 separately grid adopts 0 ~ vin(input voltage) logic control, there is not reliability consideration.Output voltage after described first output PMOS transistor pm3 can well transmit boosting when conducting to exporting storage capacitance c4, and cuts off source and drain two ends when turning off, and can realize the logic control of grid without the need to extra storage battery shift circuit.
Described second electric charge draws unit 2 and comprises one second nmos switch nm2 further, the source electrode of described second nmos switch nm2 is connected with substrate and accesses charge pump voltage input vin, grid is connected with described first charge pump capacitor c1, drains and to be connected with described second charge pump capacitor c2 and to be connected to the source electrode that described second exports PMOS transistor pm4.The substrate of the second nmos switch nm2 is connected to its source, in the steady state, source all can be considered potential minimum, and in process of establishing, there is forward bias and conducting in substrate and drain terminal diode, but this diode leakage current promotes that drain terminal voltage accelerates close to input terminal voltage, is therefore useful diode leakage current, allow to exist at circuit establishment stage.
Described second electric charge draws unit 2 and comprises one second PMOS switch pm2 and the 4th nmos switch nm4 further; The source electrode of described second PMOS switch pm2 is connected with substrate and accesses charge pump voltage input vin, grid is connected with a charging clock signal end ck_pm2, drains and to be connected with the drain electrode of described 4th nmos switch nm4 and to be connected to by described second charge pump capacitor c2 the source electrode that described second exports PMOS transistor pm4; The source electrode of described 4th nmos switch nm4 is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal end ck_nm4, drains and to be connected with the drain electrode of described second PMOS switch pm2 and to be connected to the drain electrode of described second nmos switch nm2 by described second charge pump capacitor c2.The voltage change range of the drain electrode of the second PMOS switch and the drain electrode of the 4th nmos switch is between 0 ~ input voltage, and therefore, the second PMOS switch pm2 and the 4th nmos switch nm4 separately grid adopts the logic control of 0 ~ vin, there is not reliability consideration.Output voltage after described second output PMOS transistor pm4 can well transmit boosting when conducting to exporting storage capacitance c4, and cuts off source and drain two ends when turning off, and can realize the logic control of grid without the need to extra level shift circuit.
As preferred embodiment, described voltage selecting circuit 3 comprises one the 5th PMOS switch pm5, one a 6th PMOS switch pm6 and substrate electric potential storage capacitance c3, and described 5th PMOS switch pm5 and the 6th PMOS switch pm6 is drain electrode and substrate connects and accesses equipotential end by described substrate electric potential storage capacitance c3, the source electrode of described 5th PMOS switch pm5 is connected to the grid that described first exports PMOS transistor pm3 respectively, second exports the source electrode of PMOS transistor pm4 and the grid of the 6th PMOS switch pm6, the grid of described 5th PMOS switch pm5 is connected to the source electrode that described first exports PMOS transistor pm3 respectively, second exports the grid of PMOS transistor pm4 and the source electrode of the 6th PMOS switch pm6, the drain electrode of described 5th PMOS switch pm5 is connected to the substrate that described first exports PMOS transistor pm3 respectively, second exports the substrate of PMOS transistor pm4 and the drain electrode of the 6th PMOS switch pm6.
During the first output PMOS transistor pm3 conducting, the 6th PMOS switch pm6 also conducting; During the second output PMOS transistor pm4 conducting, the 5th PMOS switch pm5 also conducting; The current potential of in store ceiling voltage all the time on substrate electric potential storage capacitance c3 like this, ensure that first, second exports PMOS transistor pm3, pm4, five, the 6th PMOS switch pm5, pm6 substrate are connected on ceiling voltage all the time, avoid charge pump output voltage to cause first, second to export PMOS transistor pm3, pm4 substrate variations.
Working method of the present invention is provided below in conjunction with accompanying drawing 3.
The present embodiment is for 2 times of charge pumps, vin is input voltage, and vcp is output voltage, and metal-oxide-semiconductor pm1, nm1, pm3, nm3 and charge pump capacitor c1 form an electric charge and draw unit, pm3 is as output PMOS transistor, and when conducting, c1 is for exporting storage capacitance c4 charging; Metal-oxide-semiconductor pm2, nm2, pm4, nm4 and charge pump capacitor c2 form an electric charge and draw unit, and pm4 is as output PMOS transistor, and when conducting, c2 is for exporting storage capacitance c4 charging.The operation principle that two electric charges draw unit is identical, conducting or cut-out according to charging clock signal respectively, thus c1, c2 are periodically to output storage capacitance c4 charging, thus when stable state, vcp=2vin.
For c1, when nm1, nm3 conducting, vb=vin, va=0, c1 are in charged state; Work as pm1, during pm3 conducting, va=vin, because capacitance voltage can not suddenly change, vb=2vin, c1 are charged to c4 by pm3.When pm3 closes, pm4, pm2 conducting, vd=2vin, c2 are charged to c4 by pm4.Therefore c1, c2 are alternately for c4 charges like this, and under stable state, c4=2vin, is also vcp=2vin, thus realizes 2 times of charge pump functions.
The voltage change range of va, vc is at 0 ~ vin, and therefore, pm1, pm2, nm3, nm4 separately grid adopt the logic control of 0 ~ vin, there is not reliability consideration.
When nm1 conducting, now nm3, pm2, pm4 conducting, vd=2vin, namely the grid voltage of nm1 is 2vin, and source voltage vin can be delivered to vb smoothly; When nm1 turns off, pm1, nm2, nm4 conducting, the grid voltage of vb=2vin, vd=vin, nm1 is vin, and source-drain voltage is respectively vin and 2vin, and therefore nm1 is in off state, cannot open.The substrate of nm1 is connected to its source (being namely connected with vin), in the steady state, and vb or be approximately equal to vin, or equal 2vin, source all can be considered potential minimum; And in process of establishing, vb<vin, causes nm1 substrate and drain terminal diode to there is forward bias and conducting, but this diode leakage current promotes that vb accelerates close to vin, therefore be useful diode leakage current, allow to exist at circuit establishment stage.Nm2 operation principle is similar.During pm3 conducting, pm1, nm2 conducting, vb=2vin, vd=vin, namely the grid voltage of pm3 is vin, and source voltage terminal is 2vin, and therefore 2vin can be delivered to and export on storage capacitance c4 by pm3.When pm3 turns off, the grid of vb=vin, vd=2vin, pm3 and drain electrode approximately equal, be all 2vin, source class is vin, and such pm3 can well cut off source and drain two ends.Pm4 operation principle is similar.Also namely the grid-control voltage of MOS switch well can realize logic control without the need to extra level shift circuit.
In order to avoid boosting type charge pump output voltage causes pm3, pm4 substrate variations, have employed the current potential that voltage selecting circuit decides substrate.In the present embodiment, described voltage selecting circuit comprises metal-oxide-semiconductor pm5, pm6, and substrate electric potential storage capacitance c3.During pm3 conducting, pm6 is conducting also, therefore ve=vb=2vin; During pm4 conducting, pm5 is conducting also, therefore ve=vd=2vin, and the current potential of in store ceiling voltage all the time on c3, ensures that pm3 ~ pm6 substrate is connected on ceiling voltage all the time like this.
As can be seen here, boosting type charge pump described in the present embodiment had both achieved the object of 2 times of charge pumps, did not also increase too much design cost and difficulty; There is not reliability consideration, and well can realize the logic control of the grid-control voltage of MOS switch without the need to extra level shift circuit; Voltage selecting circuit is made up of metal-oxide-semiconductor and electric capacity, is convenient to integrated; Meanwhile, in one-period, described boosting type charge pump charges to output storage capacitance for twice, and its ripple is also much smaller than traditional structure, obtains more excellent output characteristic.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a boosting type charge pump, comprise that at least one first electric charge draws unit, one second electric charge draws unit and export storage capacitance, it is characterized in that, described first electric charge draws unit and comprises the first charge pump capacitor, the first output PMOS transistor and at least one charging clock signal end, and described second electric charge draws unit and comprises the second charge pump capacitor, the second output PMOS transistor and at least one charging clock signal end;
Described first exports the source electrode of PMOS transistor is connected with described first charge pump capacitor, and grid is connected with described second charge pump capacitor, and draining is connected with described output storage capacitance connects charge pump voltage output simultaneously, and substrate is connected with a voltage selecting circuit;
Described second source electrode exporting PMOS transistor is connected with described second charge pump capacitor and is connected to the grid that described first exports PMOS transistor, described second grid exporting PMOS transistor is connected with described first charge pump capacitor and is connected to the source electrode that described first exports PMOS transistor, described second drain electrode exporting PMOS transistor is connected with described output storage capacitance and connects described charge pump voltage output simultaneously, and the described second substrate exporting PMOS transistor is connected with described voltage selecting circuit and the described first substrate exporting PMOS transistor respectively;
When described first exports PMOS transistor according to charging clock signal conduction, described second exports PMOS transistor cuts off, and the first charge pump capacitor is to the charging of output storage capacitance;
When described second exports PMOS transistor according to charging clock signal conduction, described first exports PMOS transistor cuts off, and the second charge pump capacitor is to the charging of output storage capacitance.
2. boosting type charge pump according to claim 1, it is characterized in that, described voltage selecting circuit comprises one the 5th PMOS switch, one the 6th PMOS switch and a substrate electric potential storage capacitance, and described 5th PMOS switch and the 6th PMOS switch are drain electrode and substrate connects and accesses equipotential end by described substrate electric potential storage capacitance; The source electrode of described 5th PMOS switch is connected to the described first grid, second exporting PMOS transistor respectively and exports the source electrode of PMOS transistor and the grid of the 6th PMOS switch, the grid of described 5th PMOS switch is connected to the described first source electrode, second exporting PMOS transistor respectively and exports the grid of PMOS transistor and the source electrode of the 6th PMOS switch, and the drain electrode of described 5th PMOS switch is connected to the described first substrate, second exporting PMOS transistor respectively and exports the substrate of PMOS transistor and the drain electrode of the 6th PMOS switch.
3. boosting type charge pump according to claim 1 and 2, it is characterized in that, described first electric charge draws unit and comprises one first nmos switch further, the source electrode of described first nmos switch is connected with substrate and accesses charge pump voltage input, grid is connected with described second charge pump capacitor, drains and to be connected with described first charge pump capacitor and to be connected to the source electrode that described first exports PMOS transistor.
4. boosting type charge pump according to claim 3, is characterized in that, described first electric charge draws unit and comprises one first PMOS switch and one the 3rd nmos switch further; The source electrode of described first PMOS switch is connected with substrate and accesses charge pump voltage input, grid is connected with a charging clock signal end, drains and to be connected with the drain electrode of described 3rd nmos switch and to be connected to by described first charge pump capacitor the source electrode that described first exports PMOS transistor; The source electrode of described 3rd nmos switch is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal end, drains and to be connected with the drain electrode of described first PMOS switch and to be connected to the drain electrode of described first nmos switch by described first charge pump capacitor.
5. boosting type charge pump according to claim 1 and 2, it is characterized in that, described second electric charge draws unit and comprises one second nmos switch further, the source electrode of described second nmos switch is connected with substrate and accesses charge pump voltage input, grid is connected with described first charge pump capacitor, drains and to be connected with described second charge pump capacitor and to be connected to the source electrode that described second exports PMOS transistor.
6. boosting type charge pump according to claim 5, is characterized in that, described second electric charge draws unit and comprises one second PMOS switch and one the 4th nmos switch further; The source electrode of described second PMOS switch is connected with substrate and accesses charge pump voltage input, grid is connected with a charging clock signal end, drains and to be connected with the drain electrode of described 4th nmos switch and to be connected to by described second charge pump capacitor the source electrode that described second exports PMOS transistor; The source electrode of described 4th nmos switch is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal end, drains and to be connected with the drain electrode of described second PMOS switch and to be connected to the drain electrode of described second nmos switch by described second charge pump capacitor.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10447153B2 (en) * | 2017-04-24 | 2019-10-15 | Texas Instruments Incorporated | VBOOST signal generation |
| CN109361384B (en) * | 2018-12-20 | 2023-09-19 | 上海艾为电子技术股份有限公司 | Analog switch circuit |
| US10924112B2 (en) * | 2019-04-11 | 2021-02-16 | Ememory Technology Inc. | Bandgap reference circuit |
| CN110149046B (en) * | 2019-05-27 | 2024-03-08 | 南京芯耐特半导体有限公司 | CMOS charge pump with relatively constant output based on wide range of input voltages |
| CN111525790B (en) * | 2020-03-25 | 2022-04-15 | 东南大学 | Charge pump circuit |
| CN111865075B (en) * | 2020-07-27 | 2021-11-05 | 合肥工业大学 | Boost conversion circuit suitable for light energy collection structure |
| CN113825057B (en) * | 2021-08-16 | 2024-02-27 | 广东朝阳电子科技股份有限公司 | Bluetooth headset charging box boost circuit |
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| CN1703824A (en) * | 2002-11-18 | 2005-11-30 | 株式会社瑞萨科技 | Booster circuit |
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| CN203554284U (en) * | 2013-09-22 | 2014-04-16 | 江苏芯创意电子科技有限公司 | Voltage-boosting type charge pump |
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| CN1703824A (en) * | 2002-11-18 | 2005-11-30 | 株式会社瑞萨科技 | Booster circuit |
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Denomination of invention: Low ripple wave boosting type charge pump Effective date of registration: 20200110 Granted publication date: 20150930 Pledgee: Nanjing Bank Co.,Ltd. Nanjing North Branch Pledgor: NANJING XINNAITE SEMICONDUCTOR CO.,LTD. Registration number: Y2020320000035 |
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