CN103532375A - Boosting charge pump - Google Patents
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- CN103532375A CN103532375A CN201310431444.6A CN201310431444A CN103532375A CN 103532375 A CN103532375 A CN 103532375A CN 201310431444 A CN201310431444 A CN 201310431444A CN 103532375 A CN103532375 A CN 103532375A
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Abstract
The invention discloses a boosting charge pump. The boosting charge pump comprises at least one first charge drawing unit, a second charge drawing unit and an output storage capacitor, wherein the first charge drawing unit comprises a first charge pump capacitor, a first output P-channel metal oxide semiconductor (PMOS) transistor and at least one charging clock signal end; the second charge drawing unit comprises a second charge pump capacitor, a second output PMOS transistor and at least one charging clock signal end; the first output PMOS transistor and the second output PMOS transistor interact with each other and are respectively turned on or off according to a charging clock signal, so that the first charge pump capacitor and the second charge pump capacitor periodically charge the output storage capacitor. By ingenious connection between the output PMOS transistors in each charge drawing unit, the design complexity is effectively reduced, the same output voltage performance is obtained, and requirements of design key points are effectively met; the output storage capacitor is charged in a period for at least two times. Compared with a conventional structure, the structure of the boosting charge pump has the advantages that the ripple is much smaller; better output characteristics are obtained.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, relate in particular to a kind of simple in structure, the boosting type charge pump of excellent performance.
Background technology
Charge pump circuit is widely used in analog circuit, and it is mainly by electric capacity, switch, and non-overlapping clock and level shifting circuit form, and wherein the most important thing is the realization of electric capacity and switch.Existing simple charge pump as shown in Figure 1, adopts electric capacity and diode to realize, and ck1, ck2 are a pair of non-overlapping clock.The operation principle of this charge pump is: the conducting voltage of supposing diode is vt, when ck1=0, and D1 conducting, va=vin-vt in the time of stable state; Work as ck1=vin, ck2=0, va=2vin-vt, D2 conducting simultaneously, vb=2vin-2vt in the time of stable state.Va in this way, vb, vcp voltage is progressively elevated, and can select according to actual needs the number of electric capacity and diode.This structural circuit is simple, but circuit loss is larger, and every one-level fixed voltage loss is vt.
As shown in Figure 2, the switch of this charge pump replaces diode with MOS switch to improved 2 times of type charge pump constructions, can have so less voltage loss and settling time faster.The operation principle of this charge pump is: pm1, nm1 conducting, va=vin, vb=0; Pm2, pm3 conducting, vb=vin, because electric capacity c1 voltage can not suddenly change, va=2vin conducting, so va charges to electric capacity c2 by pm2, during stable state, vcp=2vin(supposes not have load here, MOS switch does not have in lossy situation).
There is following difficult point in the design of this improved 2 times of type charge pump constructions:
1. the consideration of reliability: because internal node exists instantaneous pressure, therefore need to consider duration and the amplitude of this node high pressure conditions, guarantee that each coupled device is all operated in safe bias state;
2. the selection of substrate electric potential: pm1, pm2 are PMOS switches, its substrate electric potential will select maximum potential to be connected, but vin, va, the process that vcp voltage correlation is set up at charge pump is uncertain, therefore need to adopt voltage selector select maximum potential supply with pm1 and pm2(as shown in Figure 2 voltage selector by a comparator comp and two switch sw1, sw2, formed);
The control of the grid-control voltage of 3.MOS switch: vb voltage range 0 ~ vin, so the voltage that pm3 and nm1 need to transmit and block is 0 ~ vin, the logic that its grid voltage adopts 0 ~ vin to control; Pm1 need to transmit vin, blocking-up 2vin, so its grid control logic needs 0 ~ 2vin; Pm2 is also similar; Therefore need extra level shift circuit to realize the logic control of grid different potentials.
By above-mentioned analysis, can be found out, existing improved 2 times of type charge pumps need extra circuit to meet the requirement of design main points, so not only increase design difficulty and also increased design cost and power consumption, this structure is single capacitor power supply providing for load between charged region simultaneously, so ripple is relatively also larger.Therefore, need a kind of design complexities that can simplify charge pump, obtain the charge pump construction of identical output voltage performance and less output ripple simultaneously.
Summary of the invention
Technical problem to be solved by this invention is, a kind of boosting type charge pump is provided, the design that solves charge pump in prior art needs extra circuit to meet the requirement of design main points, and increase design difficulty and also increased design cost and power consumption, and the relative also larger problem of ripple.
In order to address the above problem, the invention provides a kind of boosting type charge pump, comprise that at least one the first electric charge draws unit, one second electric charge draws unit and output storage capacitance, described the first electric charge draws unit and comprises the first charge pump electric capacity, the first output PMOS transistor and at least one charging clock signal terminal, and described the second electric charge draws unit and comprises the second charge pump electric capacity, the second output PMOS transistor and at least one charging clock signal terminal; The transistorized source electrode of described the first output PMOS is connected with described the first charge pump electric capacity, and grid is connected with described the second charge pump electric capacity, and drain electrode is connected and connects charge pump voltage output simultaneously with described output storage capacitance, and substrate is connected with a voltage selecting circuit; The transistorized source electrode of described the second output PMOS is connected with described the second charge pump electric capacity and is connected to the transistorized grid of described the first output PMOS, the transistorized grid of described the second output PMOS is connected with described the first charge pump electric capacity and is connected to the transistorized source electrode of described the first output PMOS, the transistorized drain electrode of described the second output PMOS is connected and connects described charge pump voltage output simultaneously with described output storage capacitance, and the transistorized substrate of described the second output PMOS is connected with described voltage selecting circuit and the transistorized substrate of described the first output PMOS respectively; When described first exports PMOS transistor according to the conducting of charging clock signal, described the second output PMOS transistor cuts off, and the first charge pump electric capacity charges to output storage capacitance; When described second exports PMOS transistor according to the conducting of charging clock signal, described the first output PMOS transistor cuts off, and the second charge pump electric capacity output storage capacitance is charged.
The invention has the advantages that, by each electric charge, draw in unit and export the mutual ingenious connection of PMOS transistor, effectively reduce design complexities, obtain identical output voltage performance simultaneously, effectively meet the requirement of design main points; And repeatedly to the charging of output storage capacitance, its ripple is also much smaller than traditional structure, has obtained more excellent output characteristic in one-period.
Accompanying drawing explanation
Fig. 1, the circuit diagram of existing simple charge pump;
Fig. 2, the circuit diagram of improved 2 times of type charge pumps;
Fig. 3, the circuit diagram of an execution mode of boosting type charge pump of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of boosting type charge pump provided by the invention is elaborated.
With reference to accompanying drawing 3, the circuit diagram of an execution mode of boosting type charge pump of the present invention, described boosting type charge pump comprises that at least one the first electric charge draws unit 1, one second electric charge draws unit 2, output storage capacitance C4 and voltage selecting circuit 3.Wherein, in figure, the connected crosspoint of wire adds black circle and represents.
Described the first electric charge draws unit 1 and comprises the first charge pump electric capacity c1, the first output PMOS transistor pm3 and at least one charging clock signal terminal 11, and described the second electric charge draws unit 2 and comprises the second charge pump electric capacity c2, the second output PMOS transistor pm4 and at least one charging clock signal terminal 21.
The source electrode of described the first output PMOS transistor pm3 is connected with described the first charge pump electric capacity c1, grid is connected with described the second charge pump electric capacity c2, drain electrode is connected and meets charge pump voltage output vcp simultaneously with described output storage capacitance c4, and substrate is connected with voltage selecting circuit 3.When charging clock signal terminal 11 receives after charging clock signal, the first output PMOS transistor pm3 conducting, the first charge pump electric capacity c1 charges to output storage capacitance c4 by the first output PMOS transistor pm3, thereby the output voltage of charge pump voltage output vcp is raise.
The source electrode of described the second output PMOS transistor pm4 is connected with described the second charge pump electric capacity c2 and is connected to the described first grid of exporting PMOS transistor pm3, the grid of described the second output PMOS transistor pm4 is connected with described the first charge pump electric capacity c1 and is connected to the described first source electrode of exporting PMOS transistor pm3, the drain electrode of described the second output PMOS transistor pm4 is connected and meets described charge pump voltage output vcp simultaneously with described output storage capacitance c4, the substrate of described the second output PMOS transistor pm4 is connected with the substrate of described voltage selecting circuit 3 and described the first output PMOS transistor pm3 respectively.When charging clock signal terminal 21 receives after charging clock signal, the second output PMOS transistor pm4 conducting, the second charge pump electric capacity c2 charges to output storage capacitance c4 by the second output PMOS transistor pm4, thereby the output voltage of charge pump voltage output vcp is raise.
When described first exports PMOS transistor pm3 according to the conducting of charging clock signal, described the second output PMOS transistor pm4 cuts off, and the first charge pump electric capacity c1 charges to output storage capacitance c4; When described second exports PMOS transistor pm4 according to the conducting of charging clock signal, described the first output PMOS transistor pm3 cuts off, and the second charge pump electric capacity c2 output storage capacitance c4 charges.Also be described the first output PMOS transistor pm3 with described the second output PMOS transistor pm4 respectively according to charging clock signal and conducting or cut-out, thereby the first charge pump electric capacity c1 periodically charges to exporting storage capacitance c4 with the second charge pump electric capacity c2.Ingenious connection by described the first output PMOS transistor pm3 with described the second output PMOS transistor pm4, effectively reduces design complexities, obtains identical output voltage performance simultaneously; And because boosting type charge pump of the present invention repeatedly charges to output storage capacitance c4 in one-period, its ripple is also much smaller than traditional structure, has obtained more excellent output characteristic.
Described the first electric charge draws unit 1 and further comprises one first nmos switch nm1, the source electrode of described the first nmos switch nm1 is connected with substrate and accesses charge pump voltage input vin, grid is connected with described the second charge pump electric capacity c2, the source electrode that drains and be connected with described the first charge pump electric capacity c1 and be connected to described the first output PMOS transistor pm3.The substrate of the first nmos switch nm1 is connected to its source, under stable state, source all can be considered potential minimum, and in process of establishing, there is forward bias and conducting in substrate and drain terminal diode, but this diode leakage current promotes drain terminal voltage to accelerate to approach input terminal voltage, is therefore useful diode leakage current, allow to exist at circuit establishment stage.
Described the first electric charge draws unit 1 and further comprises one the one PMOS switch pm1 and one the 3rd nmos switch nm3; The source electrode of a described PMOS switch pm1 is connected with substrate and accesses charge pump voltage input vin, grid is connected with a charging clock signal terminal ck_pm1, the source electrode that drains and be connected with the drain electrode of described the 3rd nmos switch nm3 and be connected to described the first output PMOS transistor pm3 by described the first charge pump electric capacity c1; The source electrode of described the 3rd nmos switch nm3 is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal terminal ck_nm3, the drain electrode that drains and be connected with the drain electrode of a described PMOS switch pm1 and be connected to described the first nmos switch nm1 by described the first charge pump electric capacity c1.The change in voltage scope of the one drain electrode of PMOS switch pm1 and the drain electrode of the 3rd nmos switch nm3 is between 0 ~ input voltage, therefore, the one PMOS switch pm1 and the 3rd nmos switch nm3 separately grid adopt 0 ~ vin(input voltage) logic control, there is not reliability consideration.Described the first output PMOS transistor pm3 can well transmit output voltage after boosting to exporting storage capacitance c4 when conducting, and when turn-offing leakage two ends, partition source, without extra storage battery shift circuit, can realize the logic control of grid.
Described the second electric charge draws unit 2 and further comprises one second nmos switch nm2, the source electrode of described the second nmos switch nm2 is connected with substrate and accesses charge pump voltage input vin, grid is connected with described the first charge pump electric capacity c1, the source electrode that drains and be connected with described the second charge pump electric capacity c2 and be connected to described the second output PMOS transistor pm4.The substrate of the second nmos switch nm2 is connected to its source, under stable state, source all can be considered potential minimum, and in process of establishing, there is forward bias and conducting in substrate and drain terminal diode, but this diode leakage current promotes drain terminal voltage to accelerate to approach input terminal voltage, is therefore useful diode leakage current, allow to exist at circuit establishment stage.
Described the second electric charge draws unit 2 and further comprises one the 2nd PMOS switch pm2 and one the 4th nmos switch nm4; The source electrode of described the 2nd PMOS switch pm2 is connected with substrate and accesses charge pump voltage input vin, grid is connected with a charging clock signal terminal ck_pm2, the source electrode that drains and be connected with the drain electrode of described the 4th nmos switch nm4 and be connected to described the second output PMOS transistor pm4 by described the second charge pump electric capacity c2; The source electrode of described the 4th nmos switch nm4 is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal terminal ck_nm4, the drain electrode that drains and be connected with the drain electrode of described the 2nd PMOS switch pm2 and be connected to described the second nmos switch nm2 by described the second charge pump electric capacity c2.The change in voltage scope of the drain electrode of the drain electrode of the 2nd PMOS switch and the 4th nmos switch is between 0 ~ input voltage, and therefore, the 2nd PMOS switch pm2 and the 4th nmos switch nm4 be the logic control of grid employing 0 ~ vin separately, does not have reliability consideration.Described the second output PMOS transistor pm4 can well transmit output voltage after boosting to exporting storage capacitance c4 when conducting, and when turn-offing leakage two ends, partition source, without extra level shift circuit, can realize the logic control of grid.
As preferred embodiment, described voltage selecting circuit 3 comprises one the 5th PMOS switch pm5, one the 6th PMOS switch pm6 and a substrate electric potential storage capacitance c3, and described the 5th PMOS switch pm5 and the 6th PMOS switch pm6 are drain electrode and substrate joins and access equipotential end by described substrate electric potential storage capacitance c3, the source electrode of described the 5th PMOS switch pm5 is connected to respectively the grid of described the first output PMOS transistor pm3, the source electrode of the second output PMOS transistor pm4 and the grid of the 6th PMOS switch pm6, the grid of described the 5th PMOS switch pm5 is connected to respectively the source electrode of described the first output PMOS transistor pm3, the grid of the second output PMOS transistor pm4 and the source electrode of the 6th PMOS switch pm6, the drain electrode of described the 5th PMOS switch pm5 is connected to respectively the substrate of described the first output PMOS transistor pm3, the substrate of the second output PMOS transistor pm4 and the drain electrode of the 6th PMOS switch pm6.
During the first output PMOS transistor pm3 conducting, the 6th also conducting of PMOS switch pm6; During the second output PMOS transistor pm4 conducting, the 5th also conducting of PMOS switch pm5; The current potential of in store ceiling voltage all the time on substrate electric potential storage capacitance c3 like this, guarantee first, second output PMOS transistor pm3, pm4, five, the 6th PMOS switch pm5, pm6 substrate are connected on ceiling voltage all the time, avoid charge pump output voltage to cause first, second output PMOS transistor pm3, pm4 substrate variations.
Below in conjunction with accompanying drawing 3, provide working method of the present invention.
It is example that the present embodiment be take 2 times of charge pumps, vin is input voltage, and vcp is output voltage, and metal-oxide-semiconductor pm1, nm1, pm3, nm3 and charge pump electric capacity c1 form an electric charge and draw unit, pm3 is as output PMOS transistor, and when conducting, c1 is output storage capacitance c4 charging; Metal-oxide-semiconductor pm2, nm2, pm4, nm4 and charge pump electric capacity c2 form an electric charge and draw unit, and pm4 is as output PMOS transistor, and when conducting, c2 is output storage capacitance c4 charging.The operation principle that two electric charges draw unit is identical, respectively according to charging clock signal and conducting or cut-out, thereby c1, c2 periodically to output storage capacitance c4 charging, thereby when stable state, vcp=2vin.
Take c1 as example, when nm1, nm3 conducting, vb=vin, va=0, c1 is in charged state; Work as pm1, during pm3 conducting, va=vin, because capacitance voltage can not suddenly change, vb=2vin, c1 charges to c4 by pm3.When pm3 closes, pm4, pm2 conducting, vd=2vin, c2 charges to c4 by pm4.Therefore c1, c2 are alternately for c4 charges like this, and under stable state, c4=2vin, is also vcp=2vin, thereby realizes 2 times of charge pump functions.
Va, the change in voltage scope of vc is at 0 ~ vin, and therefore, pm1, pm2, nm3, nm4 be the logic control of grid employing 0 ~ vin separately, does not have reliability consideration.
When nm1 conducting, now nm3, pm2, pm4 conducting, vd=2vin, namely the grid voltage of nm1 is 2vin, source voltage vin can be delivered to vb smoothly; When nm1 turn-offs, pm1, nm2, nm4 conducting, vb=2vin, vd=vin, the grid voltage of nm1 is vin, source-drain voltage is respectively vin and 2vin, so nm1 is in off state, cannot open.The substrate of nm1 is connected to its source (being connected with vin), under stable state, and vb or be approximately equal to vin, or equal 2vin, source all can be considered potential minimum; And in process of establishing, vb < vin, causes nm1 substrate and drain terminal diode to have forward bias and conducting, but this diode leakage current promotes vb to accelerate to approach vin, is therefore useful diode leakage current, allows to exist at circuit establishment stage.Nm2 operation principle is similar.During pm3 conducting, pm1, nm2 conducting, vb=2vin, vd=vin, namely the grid voltage of pm3 is vin, and source voltage terminal is 2vin, so pm3 can be delivered to 2vin on output storage capacitance c4.When pm3 turn-offs, vb=vin, vd=2vin, the grid of pm3 and drain electrode approximately equal, be all 2vin, and source class is vin, and pm3 can well leakage two ends, partition source like this.Pm4 operation principle is similar.Also the grid-control voltage that is MOS switch can well be realized logic control without extra level shift circuit.
For fear of boosting type charge pump output voltage, cause pm3, pm4 substrate variations, has adopted voltage selecting circuit to decide the current potential of substrate.In the present embodiment, described voltage selecting circuit comprises metal-oxide-semiconductor pm5, pm6, and substrate electric potential storage capacitance c3.During pm3 conducting, pm6 is conducting also, so ve=vb=2vin; During pm4 conducting, pm5 is conducting also, so ve=vd=2vin, and the current potential of in store ceiling voltage all the time on c3, guarantees that pm3 ~ pm6 substrate is connected on ceiling voltage all the time like this.
As can be seen here, boosting type charge pump had both been realized the object of 2 times of charge pumps described in the present embodiment, did not also increase too much design cost and difficulty; There is not reliability consideration, and without extra level shift circuit, can well realize the logic control of the grid-control voltage of MOS switch; Voltage selecting circuit is comprised of metal-oxide-semiconductor and electric capacity, is convenient to integrated; Meanwhile, twice pair of output storage capacitance of described boosting type charge pump charging in one-period, its ripple is also much smaller than traditional structure, has obtained more excellent output characteristic.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a boosting type charge pump, comprise that at least one the first electric charge draws unit, one second electric charge draws unit and output storage capacitance, it is characterized in that, described the first electric charge draws unit and comprises the first charge pump electric capacity, the first output PMOS transistor and at least one charging clock signal terminal, and described the second electric charge draws unit and comprises the second charge pump electric capacity, the second output PMOS transistor and at least one charging clock signal terminal;
The transistorized source electrode of described the first output PMOS is connected with described the first charge pump electric capacity, and grid is connected with described the second charge pump electric capacity, and drain electrode is connected and connects charge pump voltage output simultaneously with described output storage capacitance, and substrate is connected with a voltage selecting circuit;
The transistorized source electrode of described the second output PMOS is connected with described the second charge pump electric capacity and is connected to the transistorized grid of described the first output PMOS, the transistorized grid of described the second output PMOS is connected with described the first charge pump electric capacity and is connected to the transistorized source electrode of described the first output PMOS, the transistorized drain electrode of described the second output PMOS is connected and connects described charge pump voltage output simultaneously with described output storage capacitance, and the transistorized substrate of described the second output PMOS is connected with described voltage selecting circuit and the transistorized substrate of described the first output PMOS respectively;
When described first exports PMOS transistor according to the conducting of charging clock signal, described the second output PMOS transistor cuts off, and the first charge pump electric capacity charges to output storage capacitance; When described second exports PMOS transistor according to the conducting of charging clock signal, described the first output PMOS transistor cuts off, and the second charge pump electric capacity output storage capacitance is charged.
2. boosting type charge pump according to claim 1, it is characterized in that, described voltage selecting circuit comprises one the 5th PMOS switch, one the 6th PMOS switch and a substrate electric potential storage capacitance, and described the 5th PMOS switch and the 6th PMOS switch are drain electrode and substrate joins and access equipotential end by described substrate electric potential storage capacitance;
The source electrode of described the 5th PMOS switch is connected to respectively the grid of the transistorized grid of described the first output PMOS, the second output transistorized source electrode of PMOS and the 6th PMOS switch, the grid of described the 5th PMOS switch is connected to respectively the source electrode of the transistorized source electrode of described the first output PMOS, the second output transistorized grid of PMOS and the 6th PMOS switch, and the drain electrode of described the 5th PMOS switch is connected to respectively the drain electrode of the transistorized substrate of described the first output PMOS, the second output transistorized substrate of PMOS and the 6th PMOS switch.
3. boosting type charge pump according to claim 1 and 2, it is characterized in that, described the first electric charge draws unit and further comprises one first nmos switch, the source electrode of described the first nmos switch is connected with substrate and accesses charge pump voltage input, grid is connected with described the second charge pump electric capacity, and drain electrode is connected with described the first charge pump electric capacity and is connected to the transistorized source electrode of described the first output PMOS.
4. boosting type charge pump according to claim 3, is characterized in that, described the first electric charge draws unit and further comprises one the one PMOS switch and one the 3rd nmos switch;
The source electrode of a described PMOS switch is connected with substrate and accesses charge pump voltage input, grid is connected with a charging clock signal terminal, and drain electrode is connected with the drain electrode of described the 3rd nmos switch and is connected to the transistorized source electrode of described the first output PMOS by described the first charge pump electric capacity;
The source electrode of described the 3rd nmos switch is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal terminal, the drain electrode that drains and be connected with the drain electrode of a described PMOS switch and be connected to described the first nmos switch by described the first charge pump electric capacity.
5. boosting type charge pump according to claim 1 and 2, it is characterized in that, described the second electric charge draws unit and further comprises one second nmos switch, the source electrode of described the second nmos switch is connected with substrate and accesses charge pump voltage input, grid is connected with described the first charge pump electric capacity, and drain electrode is connected with described the second charge pump electric capacity and is connected to the transistorized source electrode of described the second output PMOS.
6. boosting type charge pump according to claim 5, is characterized in that, described the second electric charge draws unit and further comprises one the 2nd PMOS switch and one the 4th nmos switch;
The source electrode of described the 2nd PMOS switch is connected with substrate and accesses charge pump voltage input, grid is connected with a charging clock signal terminal, and drain electrode is connected with the drain electrode of described the 4th nmos switch and is connected to the transistorized source electrode of described the second output PMOS by described the second charge pump electric capacity;
The source electrode of described the 4th nmos switch is connected with substrate and accesses equipotential end, grid is connected with a charging clock signal terminal, the drain electrode that drains and be connected with the drain electrode of described the 2nd PMOS switch and be connected to described the second nmos switch by described the second charge pump electric capacity.
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| CN110149046A (en) * | 2019-05-27 | 2019-08-20 | 南京芯耐特半导体有限公司 | Relative constant CMOS charge pump is exported based on wide-range input voltage |
| CN110149046B (en) * | 2019-05-27 | 2024-03-08 | 南京芯耐特半导体有限公司 | CMOS charge pump with relatively constant output based on wide range of input voltages |
| CN111525790A (en) * | 2020-03-25 | 2020-08-11 | 东南大学 | Charge pump circuit |
| CN111525790B (en) * | 2020-03-25 | 2022-04-15 | 东南大学 | Charge pump circuit |
| CN111865075A (en) * | 2020-07-27 | 2020-10-30 | 合肥工业大学 | Boost conversion circuit suitable for light energy collection structure |
| CN113825057A (en) * | 2021-08-16 | 2021-12-21 | 广东朝阳电子科技股份有限公司 | Bluetooth headset charging box boost circuit |
| CN113825057B (en) * | 2021-08-16 | 2024-02-27 | 广东朝阳电子科技股份有限公司 | Bluetooth headset charging box boost circuit |
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