CN107180812A - 晶圆级芯片尺寸封装及其形成方法 - Google Patents

晶圆级芯片尺寸封装及其形成方法 Download PDF

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Publication number
CN107180812A
CN107180812A CN201611140300.5A CN201611140300A CN107180812A CN 107180812 A CN107180812 A CN 107180812A CN 201611140300 A CN201611140300 A CN 201611140300A CN 107180812 A CN107180812 A CN 107180812A
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China
Prior art keywords
layer
passivation layer
conducting element
joint sheet
conductive
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CN201611140300.5A
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Inventor
季彦良
熊明仁
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MediaTek Inc
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MediaTek Inc
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Publication of CN107180812A publication Critical patent/CN107180812A/zh
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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Abstract

本发明实施例提供了一种晶圆级芯片尺寸封装及其形成方法。其中该封装包括：半导体结构；接合垫，形成于该半导体结构上并且包括：多个导电片段；导电元件，形成于该半导体结构上，并且与该接合垫相邻；钝化层，形成于该半导体结构、该接合垫及该导电元件上，其中该钝化层露出该接合垫的导电片段的一部分；导电的重分布层，形成于该钝化层以及该接合垫的导电片段从该钝化层露出的部分上；平坦化层，形成于该钝化层和该导电的重分布层上，并且露出该导电的重分布层的一部分；凸块下金属层，形成于该平坦化层以及该导电的重分布层从该平坦化层露出的部分上；以及导电凸块，形成于该凸块下金属层上。本发明实施例，可以进一步降低封装的尺寸。

Description

晶圆级芯片尺寸封装及其形成方法
技术领域
本发明涉及封装技术，尤其涉及一种WLCSP(Wafer-Level Chip-Size Package，晶圆级芯片尺寸封装)及其形成方法。
背景技术
使电子产品小、轻和高性能的愿望已经转变为使电子部件小、轻和高性能的愿望。此种愿望已导致各种封装技术连同与半导体设计与制造有关的技术的发展。传统的封装技术例如包括：基于区域阵列及表面黏着(surface-mount)封装的BGA(Ball Grid Array，球栅阵列)、倒装芯片以及CSP(Chip-Size Package，芯片尺寸封装)。
于上述中，CSP是一种亟待开发的能够使得封装与实际的芯片具有大致相同尺寸的封装技术。特别地，在WLCSP中，在晶圆级中进行封装以显著地降低每颗芯片的封装成本。一般地，WLCSP包括：RDL(redistribution layer，重分布层)布线(wiring trace)、用于形成凸块的UBM(Under Bump Metallurgy，凸块下金属)层，以及保护电路的钝化层。
发明内容
有鉴于此，本发明实施例提供了一种晶圆级芯片尺寸封装及其形成方法，可以缩小晶圆级芯片尺寸封装的尺寸。
本发明提供了一种晶圆级芯片尺寸封装，包括：半导体结构；接合垫，形成于该半导体结构上并且包括：多个导电片段；导电元件，形成于该半导体结构上，并且与该接合垫相邻；钝化层，形成于该半导体结构、该接合垫及该导电元件上，其中该钝化层露出该导电片段的一部分；导电的重分布层，形成于该钝化层以及该导电片段从该钝化层露出的部分上；平坦化层，形成于该钝化层和该导电的重分布层上，并且露出该导电的重分布层的一部分；凸块下金属层，形成于该平坦化层以及该导电的重分布层从该平坦化层露出的部分上；以及导电凸块，形成于该凸块下金属层上。
其中，该导电元件设置在两个该导电片段之间、或者该导电元件设置在多个该导电片段的左侧处、或者该导电元件设置在多个该导电片段的右侧处。
其中，该钝化层包括：介电材料；及/或，该平坦化层包括：聚酰亚胺，聚苯并恶唑或者苯环丁烯。
其中，该凸块下金属层形成于该重分布层上，其中该该凸块下金属层不位于该导电片段自该钝化层露出的部分的上方。
其中，该导电片段从该钝化层露出的部分的尺寸介于2μm～90μm之间；及/或，该导电片段从该钝化层露出的部分为圆形、带状或者多边形。
其中，俯视时该导电元件具有带状构造。
本发明提供了一种形成晶圆级芯片尺寸封装的方法，包括：提供其上形成有接合垫和导电元件的半导体结构，其中该接合垫包括：多个导电片段，并且该导电元件相邻该接合垫；于该半导体结构、该接合垫及该导电元件上形成钝化层，其中该钝化层露出该导电片段的部分；于该钝化层和该导电片段自该钝化层露出的部分上形成导电的重分布层；于该钝化层和该导电的重分布层上形成平坦化层，并且该平坦化层露出该导电的重分布层的一部分；于该平坦化层以及该导电的重分布层自该平坦化层露出的部分上形成凸块下金属层；以及于该凸块下金属层上形成导电凸块。
其中，该钝化层的形成步骤包括：于该半导体结构、该接合垫及该导电元件上形成该钝化层；以及在该钝化层中形成多个开口并且该多个开口分别露出多个该导电片段的部分。
其中，该平坦化层的形成步骤包括：于该钝化层和该导电的重分布层上形成该平坦化层；以及在该平坦化层的一部分中形成开口，以露出该导电的重分布层的一部分。
其中，该导电片段自该钝化层露出的部分具有圆形、带状或多边形；及/或，该导电片段自该钝化层露出的部分的尺寸介于2μm～90μm之间；及/或，俯视时该导电元件具有带状构造。
本发明实施例的有益效果是：
本发明实施例，由钝化层来露出接合垫的导电片段的一部分，因此不需要接合垫具有大尺寸构造，从而能够减少导电片段的尺寸以使得接合垫附近能够有额外的空间来设置导电元件，从而增加了元件布置密度，进而缩小晶圆级芯片尺寸封装(如其中的集成电路)的尺寸。
附图说明
通过阅读接下来的详细描述以及参考附图所做的示例，可以更全面地理解本发明，其中：
图1为根据本发明实施例的WLCSP的横截面示意图；
图2～8为用于示意根据本发明实施例的形成WLCSP的方法的横截面示意图；
图9为图8中的WLCSP的区域的俯视图；
图10为根据本发明另一实施例的WLCSP的横截面示意图；
图11为图10中的WLCSP的区域的俯视图；
图12为根据本发明另一实施例的WLCSP的横截面示意图；
图13为图12中的WLCSP的区域的俯视图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
以下描述为实现本发明的较佳预期模式。该描述仅做为说明本发明的一般原理的目的，而不应被视为限制。本发明的范围最好参考所附的权利要求来确定。
图1是根据本发明实施例的WLCSP(晶圆级芯片尺寸封装)的横截面示意图。
如图1所示，该WLCSP包括：半导体结构100，接合垫102，钝化层104，第一平坦化(planarization)层106，第二平坦化层112，导电的RDL(redistribution layer，重分布层)110，UBM(凸块下金属)层116和导电凸块118。
此中，出于简化附图的目的，将该半导体结构100示意为具有平坦的顶面。需要注意的是，该半导体结构100可以为具有形成于其上的多个半导体装置及互连结构(均未示出)的晶圆级半导体基底。其中，形成在该半导体基底100上的半导体装置例如为晶体管或者二极管等有源装置，及/或电容、电阻和导体等无源装置。该半导体结构100中的互连结构可以包括：由多个层间介电层隔离与支撑的多层金属化结构。在本实施例中，仅半导体结构100的一部分被示意在WLCSP中。
参考图1，接合垫102形成在半导体结构100的一部分上并且可以与形成在半导体结构100中的电路的互连结构(未示出)之一电性连接。钝化层104和第一平坦化层106顺序地形成在半导体结构100上，并且钝化层104和第一平坦化层106覆盖接合垫102的一部分。在第一平坦化层106中形成开口108以露出接合垫102的一部分，并且RDL110形成在第一平坦化层106的一部分上，同时形成在开口108中以覆盖接合垫102自开口108中露出的部分。第二平坦化层112形成在第一平坦化层106及RDL110上，并且在第二平坦化层112中形成开口114以露出RDL110的一部分。UBM层116形成在第二平坦化层112的一部分及RDL110自第二平坦化层112露出的部分上，并且导电凸块118形成在UBM层116上。
在本实施例中，接合垫102可以包括铝等导电材料，并且钝化层104可以包括氧化硅、氮化硅或者他们的组合物等介电材料。第一平坦化层106和第二平坦化层112可以包括氮化硅、氧化硅或者聚合物等介电材料。在一个实施例中，适合于第一平坦化层106和第二平坦化层112的聚合物例如可以为聚酰亚胺，聚苯并恶唑，苯环丁烯。RDL110可以包括铜、镍或铝等导电材料。UBM层116可以包括金属或金属合金等导电材料，例如镍、银、铝、铜或者他们的合金，或者掺有多晶硅、单晶硅或者导电玻璃的材料。另外，诸如钛、钼、铬或者钛钨等耐火金属材料可以用来单独地形成UBM层116或者与其他金属层组合。一般地，第一平坦化层106的厚度C大约介于5μm～7.5μm之间。并且位于接合垫102上的第一平坦化层106的阶梯高度(step-height)过大，使得第一平坦化层106中形成的开口108小于钝化层104中形成的开口，该钝化层104中形成的开口的大小介于3μm～300μm之间。因此，RDL110形成在第一平坦化层106的一部分和接合垫102自开口108露出的部分上，并且RDL110具有梯状部A和平坦部B，其中梯状部A在开口108附近具有梯状(step-like)构造，其中平坦部B具有平坦构造并且平坦部B从开口108延伸并且位于第一平坦化层106上。另外，第二平坦化层112中形成的开口114露出RDL110的平坦部B的一部分，使得UBM层114可以设置在第二平坦化层112的一部分以及平坦部B从开口114露出的部分上。
在图1所示的WLCSP中，由于提供的第一平坦化层106的厚度C介于5μm～7.5μm之间，因此开口108附近的第一平坦化层106的阶梯高度必然太高而无法形成小尺寸的开口108。如此，RDL110位于开口108附近的部分形成梯状构造，并且UBM层116和形成在UBM层116上的导电凸块(如焊锡凸块)118仅形成在RDL110的平坦部B上，其中该平坦部B沿开口108延伸并且位于第一平坦化层106上。另外，由于钝化层104中形成的开口的尺寸需要大于第一平坦化层106中形成的开口108的尺寸，因此钝化层104中形成的开口所露出的接合垫102将具备在图1所示的WLCSP的操作期间仅具有单一电位的大型(large-sized)导电垫的构造。因此，图1所示的WLCSP的封装(footprint)是相当大并且没有机会在靠近接合垫102的位置形成另一导电元件，以在图1所示的WLCSP的操作期间提供另一电位。由于趋势是进一步降低WLCSP中的IC(集成电路)的尺寸，因此图1所示的WLCSP是不受欢迎的。
因此，图2～8为根据本发明另一实施例的横截面示意图，用来示意形成WLCSP的方法，其中，该WLCSP具有靠近接合垫的额外的导电元件，该导电元件提供不同于接合垫的电位的另一电位。
参考图2，提供了半导体结构200，具有形成在该半导体结构200的各部分上的接合垫202及导电元件203。接合垫202包括：多个分开的导电片段(conductive segments)，形成在半导体结构200上，并且导电元件203邻近接合垫202。在一个实施例中，如图2所示，接合垫202包括：两个导电片段202a，形成在半导体结构200的各部分上，并且导电元件203于导电垫202的导电片段202a之间的位置处形成于半导体结构200上。导电元件203通过沟道(trench)201与接合垫202的两个导电片段202a隔开，其中该沟道201形成于导电元件203和接合垫202的一个导电片段202a之间。导电元件203及接合垫202的导电片段202a包括：诸如Al(铝)、Cu(铜)或者W(钨)等相同的导电材料，并且可以同时形成。
仍然参考图2，接着例如通过CVD(Chemical Vapor Deposition，化学气相沉积)工艺(未示出)在半导体结构200、接合垫202及导电元件203上形成钝化层204。该钝化层204形成在半导体结构200、接合垫202及导电元件203上，并且填充每个沟道201。如图2所示，钝化层204具有非平坦的顶面，位于半导体结构200的上方。在一个实施例中，钝化层204的一部分形成在半导体结构200上，并且厚度T介于0.8μm～4μm之间。
在一个实施例中，半导体结构200相同于图1所示的半导体结构100，并且形成钝化层204的材料类似于形成图1所示的钝化层104的材料，以及形成接合垫202及导电元件203的材料类似于形成图1所示的接合垫102的材料。
参考图3所示，接着在图2所示的钝化层204上执行图案化工艺206以形成多个开口208，其中该多个开口208仅位于导电片段202a上的钝化层204中。
如图3所示，该多个开口208分别露出接合垫202的多个导电片段202a的一部分，例如一个开口208露出一个导电片段202a的一部分。但是，钝化层204位于导电元件203上的部分中没有形成任何开口208，从而使得钝化层204仍然覆盖导电元件203并且导电元件203不会从开口208露出。每个开口208的尺寸(例如宽度)大约介于2μm～90μm之间，并且俯视时，开口208可以为圆形、带状或者多边形(未示出)。在一个实施例中，图案化工艺206可以包括：使用合适的图案化光罩(未示出)来作为蚀刻光罩(未示出)的光刻(photolithography)与蚀刻(etching)步骤。
参考图4所示，第一平坦化层210形成在图3所示的结构的顶面上，并且接着在第一平坦化层210上执行图案化工艺212以在第一平坦化层210的一部分中形成开口214，从而露出钝化层204的一部分、开口208以及导电片段202a自开口208露出的部分，其中钝化层204露出的部分是形成于导电元件203和导电片段202a上。例如可以通过CVD或旋转涂覆来形成第一平坦化层210，并且可以通过图案化工艺212来图案化第一平坦化层210，其中图案化工艺212包括：使用了合适的图案化光罩(未示出)来作为蚀刻光罩(未示出)的光刻与蚀刻步骤(未示出)。用来形成第一平坦化层210的材料可以相同于图1所示的第一平坦化层106的材料，第一平坦化层的厚度大约介于2μm～15μm之间。
参考图5，接着在钝化层204自开口214露出的部分和第一平坦化层210的一部分上形成图案化的导电的重分布层216。参考图5所示，图案化的导电的重分布层216形成于开口214中的部分填充开口208并且覆盖钝化层204形成于导电元件203上的部分，其中开口208露出接合垫202的导电片段202a的一部分，其中图案化的导电的重分布层216形成于开口214中的部分包含：多个第一部分216a，填充钝化层204中形成的开口208，以及第二部分216b，形成于钝化层204的平坦的顶面和开口208的上方。因此，图案化的导电的重分布层216具有一致地顶面，如图5所示。通过首先在钝化层204上及开口208中形成导电的重分布层，接着通过图案化工艺(未示出)来图案化该导电的重分布层，从而形成图案化的导电的重分布层216，其中图案化工艺(未示出)包括：结合了合适的图案化光罩(未示出)来作为蚀刻光罩的光刻与蚀刻步骤(未示出)。形成图案化的导电的重分布层216的导电材料可以相同于图1所示的导电的重分布层110的材料，并且钝化层204上方的图案化的导电的重分布层216的厚度介于4μm～9μm之间。
参考图6，在图5所示的结构的顶面上形成第二平坦化层218，并且接着在第二平坦化层218上执行图案化工艺220，以在第二平坦化层218的一部分中形成开口222，从而露出图案化的重分布层216的一部分。例如可以通过CVD或者旋转涂覆来形成第二平坦化层218，并且由图案化工艺220来图案化第二平坦化层218，其中图案化工艺220包括：结合了合适的图案化光罩(未示出)来作为蚀刻光罩的光刻与蚀刻步骤(未示出)。形成第二平坦化层218的材料可以与图1所示的第一平坦化层112的材料相同，并且第二平坦化层218的厚度大约介于7.5μm～10μm之间，其中第二平坦化层218的厚度大于重分布层216的厚度。
参考图7所示，接着在重分布层216从开口222露出的部分上形成UBM层224。通过在图6所示的结构上形成导电材料层来形成UBM层224，其中例如可以通过CVD或电镀来在图6所示的结构上形成导电材料层，并且接着通过图案化工艺(未示出)来图案化UBM层224，其中图案化工艺(未示出)包括：结合了合适的图案化光罩(未示出)来作为蚀刻光罩的光刻与蚀刻步骤(未示出)。形成UBM层224的材料可以相同于图1所示的UBM层116的材料。
参考图8，接着通过传统的焊接凸块形成工艺在UBM层224上形成导电凸块226。UBM层224和导电凸块226可以顺序且坚固地形成在重分布层216上。因此，具有额外的靠近接合垫的导电元件的WLCSP大致形成。
如图8所示，由于WLCSP具有额外的导电元件203，该导电元件203与接合垫202和重分布层216电性隔离，使得导电元件203可以被设计为用作信号线、电源线或者接地线，其在图8所示的WLCSP的操作期间，操作在与接合垫202的电位不同的电位。另外，由于形成了导电元件203，因此可以将接合垫202的导电片段202a的尺寸缩小得比图1所示的传统的接合垫102的尺寸更小。因此，图8所示的WLCSP允许在更紧凑的结构中进行多功能设计，由于趋势是进一步降低WLCSP中的集成电路的尺寸，因此图8所示的WLCSP是受欢迎的。
图9为含有图8所示的接合垫202和导电元件203的区域的俯视图。在图9中，仅示意了接合垫202和导电元件203而忽略其他元件，从而方便显示接合垫202和导电元件203的布置。如图9所示，导电元件203设置在接合垫202的导电片段202a之间。导电元件203形成为向上和向下延伸的带状构造，并且接合垫202的导电片段202a形成为接合垫状(pad-like)构造，并且该接合垫状构造具有的最大尺寸(如长度)小于导电元件203的最大尺寸(如长度)。
除了图8所示的示范性实施例之外，图10为本发明的另一示范性的WLCSP的横截面示意图。此时，图10所示的WLCSP为修改自图8所示的WLCSP，并且图10中与图8中类似的元件使用相同的参考符号来表示，并且以下仅讨论图8和图10中所示的WLCSP之间的不同。
参考图10，导电元件203的位置与接合垫202中的一个导电片段202a调换，使得导电元件203形成在接合垫202中的导电片段202a的左侧处。如图10所示，导电元件203仅靠近导电垫202中的一个导电片段202a。
图11为含有图10所示的WLCSP中的接合垫202和导电元件203的区域的俯视图。类似地，在图11中，仅示意了接合垫202和导电元件203而省略了其他元件，从而方便显示接合垫202和导电元件203的布置。如图11所示，导电元件203设置在接合垫202的导电片段202a的左侧处。导电元件203形成为向上和向下延伸的带状构造，并且接合垫202的导电片段202a形成为接合垫状(pad-like)构造，并且该接合垫状构造具有的最大尺寸(如长度)小于导电元件203的最大尺寸(如长度)。
另外，除了图8所示的示范性实施例之外，图12为本发明的另一示范性的WLCSP的横截面示意图。此时，图12所示的WLCSP修改自图8所示的WLCSP，并且图12与图8中类似的元件使用相同的参考符号来表示，并且以下仅讨论图8和图12中所示的WLCSP之间的不同。
参考图12，导电元件203的位置与接合垫202中的一个导电片段202a调换，使得导电元件203形成在接合垫202中的导电片段202a的右侧处。如图12所示，导电元件203仅靠近接合垫202中的一个导电片段202a。
图13为含有图12所示的WLCSP中的接合垫202和导电元件203的区域的俯视图。类似地，在图13中，仅示意了接合垫202和导电元件203而省略了其他元件，从而方便显示接合垫202和导电元件203的布置。如图13所示，导电元件203设置在接合垫202的导电片段202a右侧处。导电元件203形成为向上和向下延伸的带状构造，并且接合垫202的导电片段202a形成为接合垫状(pad-like)构造，并且该接合垫状构造具有的最大尺寸(如长度)小于导电元件203的最大尺寸(如长度)。
类似于图8～9所示的实施例，由于图10～13所示的实施例中的WLCSP也具有与接合垫202和重分布层216电性隔离的额外的导电元件203，使得导电元件203可以设计为用作信号线、电源线或接地线，其在图8所示的WLCSP的操作期间，操作在与接合垫202的电位不同的电位。另外，由于导电元件203的形成，因此可以将接合垫202的导电片段202a的尺寸缩小至小于图1所示的传统的接合垫102的尺寸。因此图10～13所示的WLCSP允许在更紧凑的结构中进行多功能设计，由于趋势是进一步降低WLCSP中集成电路的尺寸，因此图10～13所示的WLCSP是受欢迎的。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种晶圆级芯片尺寸封装，其特征在于，包括：
半导体结构；
接合垫，形成于该半导体结构上并且包括：多个导电片段；
导电元件，形成于该半导体结构上，并且与该接合垫相邻；
钝化层，形成于该半导体结构、该接合垫及该导电元件上，其中该钝化层露出该导电片段的一部分；
重分布层，形成于该钝化层以及该导电片段从该钝化层露出的部分上；
平坦化层，形成于该钝化层和该重分布层上，并且露出该重分布层的一部分；
凸块下金属层，形成于该平坦化层以及该重分布层从该平坦化层露出的部分上；以及
导电凸块，形成于该凸块下金属层上。
2.如权利要求1所述的晶圆级芯片尺寸封装，其特征在于，该导电元件设置在两个该导电片段之间、或者该导电元件设置在多个该导电片段的左侧处、或者该导电元件设置在多个该导电片段的右侧处。
3.如权利要求1所述的晶圆级芯片尺寸封装，其特征在于，该钝化层包括：介电材料；及/或，该平坦化层包括：聚酰亚胺，聚苯并恶唑或者苯环丁烯。
4.如权利要求1所述的晶圆级芯片尺寸封装，其特征在于，该凸块下金属层形成于该重分布层上，其中该该凸块下金属层不位于该导电片段自该钝化层露出的部分的上方。
5.如权利要求1所述的晶圆级芯片尺寸封装，其特征在于，该导电片段从该钝化层露出的部分的尺寸介于2μm～90μm之间；
及/或，该导电片段从该钝化层露出的部分为圆形、带状或者多边形。
6.如权利要求1所述的晶圆级芯片尺寸封装，其特征在于，俯视时该导电元件具有带状构造。
7.一种形成晶圆级芯片尺寸封装的方法，其特征在于，包括：
提供其上形成有接合垫和导电元件的半导体结构，其中该接合垫包括：多个导电片段，并且该导电元件相邻该接合垫；
于该半导体结构、该接合垫及该导电元件上形成钝化层，其中该钝化层露出该导电片段的部分；
于该钝化层和该导电片段自该钝化层露出的部分上形成重分布层；
于该钝化层和该重分布层上形成平坦化层，并且该平坦化层露出该重分布层的一部分；
于该平坦化层以及该重分布层自该平坦化层露出的部分上形成凸块下金属层；以及
于该凸块下金属层上形成导电凸块。
8.如权利要求7所述的方法，其特征在于，该钝化层的形成步骤包括：
于该半导体结构、该接合垫及该导电元件上形成该钝化层；以及
在该钝化层中形成多个开口并且该多个开口分别露出多个该导电片段的部分。
9.如权利要求7所述的方法，其特征在于，该平坦化层的形成步骤包括：
于该钝化层和该重分布层上形成该平坦化层；以及
在该平坦化层的一部分中形成开口，以露出该重分布层的一部分。
10.如权利要求7所述的方法，其特征在于，该导电片段自该钝化层露出的部分具有圆形、带状或多边形；
及/或，该导电片段自该钝化层露出的部分的尺寸介于2μm～90μm之间；
及/或，俯视时该导电元件具有带状构造。
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