CN107167685A - The electrical testing method and system of face-down bonding - Google Patents

The electrical testing method and system of face-down bonding Download PDF

Info

Publication number
CN107167685A
CN107167685A CN201710504024.4A CN201710504024A CN107167685A CN 107167685 A CN107167685 A CN 107167685A CN 201710504024 A CN201710504024 A CN 201710504024A CN 107167685 A CN107167685 A CN 107167685A
Authority
CN
China
Prior art keywords
test circuit
circuit plate
soldered ball
metallic pattern
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710504024.4A
Other languages
Chinese (zh)
Other versions
CN107167685B (en
Inventor
黄寓洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SUZHOU SUNA PHOTOELECTRIC Co Ltd
Original Assignee
SUZHOU SUNA PHOTOELECTRIC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SUZHOU SUNA PHOTOELECTRIC Co Ltd filed Critical SUZHOU SUNA PHOTOELECTRIC Co Ltd
Priority to CN201710504024.4A priority Critical patent/CN107167685B/en
Publication of CN107167685A publication Critical patent/CN107167685A/en
Application granted granted Critical
Publication of CN107167685B publication Critical patent/CN107167685B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals

Abstract

The invention discloses a kind of electrical testing method of face-down bonding and system.The method of testing includes:First test circuit plate is provided, the first metallic pattern of a plurality of electric isolations each other is provided with the first test circuit plate, second test circuit plate is provided, the second metallic pattern of a plurality of electric isolations each other is provided with the second test circuit plate, setting the multiple metal soldered balls being distributed along setting route interval, there is provided mainly by a probe, test power supply, electric current and/or voltage test device and another probe test module in sequential series formed;Then conducting shape and short-circuit test are carried out respectively.The method of testing that the present invention is provided is simple to operation, and cost is low, easy to use, and it is enough normally to connect that can test chip after Flip Chip Bond Technique, and can effectively find the short circuit problem that exists, targetedly modified technique and can improve the quality of flip chip bonding.

Description

The electrical testing method and system of face-down bonding
Technical field
The present invention is more particularly directed to a kind of electrical testing method of face-down bonding and system, belong to semiconductor manufacturing and measurement skill Art field.
Background technology
Upside-down mounting interconnection technique is widely used in semiconductor fabrication process.This technology can be realized between two kinds of chips Hybrid connections, solder joint density is high, good reliability, is widely used in focus planar detector array (FPA), LED light source array, The connection of the corresponding reading circuit of the photoelectric chips such as spatial light modulator array or drive circuit.But photoelectric chip is past Past expensive, the Diameter of Solder Ball in Flip Chip Bond Technique is general at 20 μm or so, directly tests not only with high costs, and test Difficulty is also very high.
The content of the invention
It is a primary object of the present invention to provide the electrical testing method and system of a kind of face-down bonding, to overcome existing skill The deficiency of art.
To realize aforementioned invention purpose, the technical solution adopted by the present invention includes:
The embodiments of the invention provide a kind of electrical testing method of face-down bonding, including:
There is provided and be provided with the first of a plurality of electric isolations each other on the first test circuit plate, the first test circuit plate Metallic pattern,
There is provided and be provided with the second of a plurality of electric isolations each other on the second test circuit plate, the second test circuit plate Metallic pattern,
N number of metal soldered ball along setting route interval distribution is set, and N is positive integer,
There is provided main by a probe, test power supply, electric current and/or voltage test device and another probe is in sequential series is formed Test module;
And, N number of metal soldered ball is alternately electrically connected through a plurality of first metallic patterns, a plurality of second metallic patterns Connect, so that N number of metal soldered ball be connected to form a series circuit, and by two described probes respectively with the series circuit Two ends be electrically connected to form a test circuit, then observe test circuit whether normally;
Or, N number of metal soldered ball and the first test circuit plate or the second test circuit plate are coordinated, and make any one gold Belonging to soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, then two described probes are divided It is not electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball, then whether observe test circuit short-circuit.
The embodiment of the present invention additionally provides a kind of electrical testing system of face-down bonding, including:
First test circuit plate, the first metallic pattern with a plurality of electric isolations each other,
Second test circuit plate, the second metallic pattern with a plurality of electric isolations each other,
Along N number of metal soldered ball of setting route interval distribution, N is positive integer,
Mainly by a probe, test power supply, electric current and/or voltage test device and the survey in sequential series formed of another probe Die trial block;
When carrying out conduction test, N number of metal soldered ball is alternately electrically connected through the first metallic pattern, the second metallic pattern And a series circuit is formed, and initial and end Duan Duan of the two described probes respectively with the series circuit is electrically connected to form one Test circuit;
When carrying out short-circuit test, N number of metal soldered ball and the first test circuit plate or the second test circuit plate coordinate, and Any one metal soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, and described two Probe is electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball respectively.
Compared with prior art, advantages of the present invention includes:The method of testing that the present invention is provided is simple to operation, cost Low, easy to use, chip is enough normally to connect after can testing Flip Chip Bond Technique, and can effectively find that the short circuit existed is asked Topic, can targetedly modified technique and improve flip chip bonding quality.
Brief description of the drawings
Fig. 1 is the graphic structure schematic diagram of conduction test design in the embodiment of the present invention 1;
Fig. 2 is the partial enlargement structural representation of conduction test design in the embodiment of the present invention 1;
Fig. 3 is the detailed structure schematic diagram of conduction test design configuration in the embodiment of the present invention 1;
Fig. 4 is the graphic structure schematic diagram of short-circuit test design in the embodiment of the present invention 2;
Fig. 5 is that the conduction and short circuit of the first test circuit plate and/or the second test circuit version in the embodiment of the present invention are surveyed Attempt shape distribution schematic diagram.
Embodiment
In view of deficiency of the prior art, inventor is able to propose the present invention's through studying for a long period of time and largely putting into practice Technical scheme.The technical scheme, its implementation process and principle etc. will be further explained as follows.
On the one hand the embodiment of the present invention provides a kind of electrical testing method of face-down bonding, including:
There is provided and be provided with the first of a plurality of electric isolations each other on the first test circuit plate, the first test circuit plate Metallic pattern,
There is provided and be provided with the second of a plurality of electric isolations each other on the second test circuit plate, the second test circuit plate Metallic pattern,
N number of metal soldered ball along setting route interval distribution is set, and N is positive integer,
There is provided main by a probe, test power supply, electric current and/or voltage test device and another probe is in sequential series is formed Test module;
And, N number of metal soldered ball is alternately electrically connected through a plurality of first metallic patterns, a plurality of second metallic patterns Connect, so that N number of metal soldered ball be connected to form a series circuit, and by two described probes respectively with the series circuit Two ends be electrically connected to form a test circuit, then observe test circuit whether normally;
Or, N number of metal soldered ball and the first test circuit plate or the second test circuit plate are coordinated, and make any one gold Belonging to soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, then two described probes are divided It is not electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball, then whether observe test circuit short-circuit.
Further, methods described includes:
A probe therein and one first pad is in electrical contact, first pad and only with the 1st metal soldered ball electricity Second metallic pattern of connection is electrically combined;And
Another probe and one second pad is in electrical contact, second pad and only electrically connected with n-th metal soldered ball The second metallic pattern electrically combine;
First pad and the second pad are arranged on the second test circuit plate.
Further, any one in N number of metal soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball Metal soldered ball is simultaneously in electrical contact with the different loci on surface and one first metallic pattern, one second metallic pattern.
Further, methods described is specifically included:
In the first metallic pattern that a plurality of electric isolations each other are deposited on the first test circuit plate,
In the second metallic pattern that a plurality of electric isolations each other are deposited on the second test circuit plate,
In the first test circuit plate and/or the second test circuit plate metallization medium layer,
Correspond on the first test circuit plate and/or the second test circuit plate at solder joint and pad and process window,
The deposited metal welding column at bond pad locations,
Flip chip bonding is carried out using upside-down mounting welding machine, includes the welded ball array of N number of metal soldered ball to be formed.
In some more specific embodiments, methods described includes:At least through photoetching, stripping and electron beam evaporation side Formula, in depositing the first metallic pattern, the second metallic pattern on the first test circuit plate, the second test circuit plate.
In some more specific embodiments, methods described includes:At least through photoetching and reactive ion etching mode Correspond on the first test circuit plate and/or the second test circuit plate at solder joint and pad and process window;
In some more specific embodiments, methods described includes:At least through photoetching and thermal evaporation methods in correspondence The deposition of metal welding column is carried out at solder joint, the metal welding column includes In posts.
Further, methods described includes:If test circuit is short-circuit, judge that face-down bonding has quality problems.
The other side of the embodiment of the present invention additionally provides a kind of electrical testing system of face-down bonding, including:
First test circuit plate, the first metallic pattern with a plurality of electric isolations each other,
Second test circuit plate, the second metallic pattern with a plurality of electric isolations each other,
Along N number of metal soldered ball of setting route interval distribution, N is positive integer,
Mainly by a probe, test power supply, electric current and/or voltage test device and the survey in sequential series formed of another probe Die trial block;
When carrying out conduction test, N number of metal soldered ball is alternately electrically connected through the first metallic pattern, the second metallic pattern And a series circuit is formed, and initial and end Duan Duan of the two described probes respectively with the series circuit is electrically connected to form one Test circuit;
When carrying out short-circuit test, N number of metal soldered ball and the first test circuit plate or the second test circuit plate coordinate, and Any one metal soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, and described two Probe is electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball respectively.
Further, the first metallic pattern or the second metallic pattern only electrically connected with the 1st metal soldered ball also with setting The first pad on the first test circuit plate or the second test circuit plate is electrically combined, and is only electrically connected with n-th metal soldered ball The first metallic pattern or the second metallic pattern also be arranged on the first test circuit plate or the second test circuit plate second Pad is electrically combined, wherein a probe and the first pad are in electrical contact, another probe and the second pad are in electrical contact.
Further, first pad and the second pad are arranged on the second test circuit plate, only with the 1st metal Second metallic pattern of soldered ball electrical connection is electrically combined with the first pad, the second metal only electrically connected with n-th metal soldered ball Figure is electrically combined with the second pad.
Further, any one in N number of metal soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball Metal soldered ball is simultaneously in electrical contact with the different loci on surface and one first metallic pattern, one second metallic pattern.
The method of testing that the present invention is provided is simple, and cost is low, easy to use, and chip is after can testing Flip Chip Bond Technique Enough normal connections, and can effectively find the short circuit problem that exists, targetedly modified technique and can improve the matter of flip chip bonding Amount.
The technical scheme, its implementation process and principle etc. will be further explained in conjunction with specific embodiments as follows It is bright.
The present invention deposits soldered ball thereon by making a pair of test circuit plates after the corresponding metallic pattern of sedimentary facies Metal, carries out flip chip bonding, and complete test after passivation perforate.
The conduction test of embodiment 1
The present embodiment, which is related to, to be tested selected one on a circuit board or the conduction on two lines road.More Body, as shown in fig.1, the present embodiment system surveys to the conduction of A, B point of two selected circuits on a circuit board (wherein, the path of connecting test can be some row/column pixels or a string of pixels in some corner, as needed for examination Depending on), corresponding detection method is as follows:
There is provided main by a probe, test power supply, electric current and/or voltage test device and another probe is in sequential series is formed Test module;
A pair of test circuit plates (the first test circuit plate and the second test circuit plate) are provided, and according to side known to industry Case, it is plural in being deposited on the first test circuit plate, the second test circuit plate by modes such as photoetching, stripping and electron beam evaporations First metallic pattern of individual electric isolation each other, the second metallic pattern (the first metallic pattern is also referred to as upper strata metallic pattern, Two metallic patterns are also referred to as lower metal figure, and upper strata metallic pattern and lower metal figure can be identical or differ , and can be designed according to actual demand).
Using mode known to industry in the first test circuit plate and/or the second test circuit plate metallization medium layer (such as oxygen SiClx or silicon nitride etc.),
Solder joint and weldering are corresponded on the first test circuit plate and/or the second test circuit plate using mode known to industry Pan Chu processes window,
According to scheme known to industry, by modes such as photoetching and thermal evaporations corresponding to carrying out the heavy of In posts at solder joint Product;
According to scheme known to industry, flip chip bonding is carried out using upside-down mounting welding machine, to form the soldered ball battle array for including N number of In balls Row, N is positive integer;
N number of In balls are alternately electrically connected into (the first metal through a plurality of first metallic patterns, a plurality of second metallic patterns The connected mode of figure and the second metallic pattern and In balls see shown in Fig. 2), so that N number of In balls be connected to be formed a string Join in circuit (refering to shown in Fig. 3), N number of In balls except the 1st In ball (corresponding to A points) and n-th In balls (corresponding to B points) it Any one outer In ball is electrically connected with the different loci on surface with one first metallic pattern, one second metallic pattern simultaneously Touch, two described probes are electrically connected to form a test circuit with the two ends of the series circuit respectively, then observe test Circuit whether normally.
The short-circuit test of embodiment 2
The present embodiment, which is related to, to be tested with the presence or absence of short circuit the one or more selected circuit on a circuit board. The typical resolution chart of one of which is as shown in Figure 4.Corresponding method of testing is as follows:
Test module (same as Example 1) is provided;
A test circuit plate (can be the second test circuit plate) is provided, it can make in the way of embodiment 1;
N number of In balls and the second test circuit plate are coordinated, and make any one In ball only can be with corresponding one second metal Figure is in electrical contact, and the second metallic pattern electrical connection electrically connected with first In ball sets the first pad, with n-th In balls electricity The second metallic pattern electrical connection of connection is provided with the second pad, and (the first pad and the second pad are while be arranged on the second test electricity On the plate of road), then two described probes are electrically connected to form a test circuit with the 1st In ball, n-th In balls respectively, then Whether short-circuit observe test circuit.
If test circuit is short-circuit, judge that face-down bonding has quality problems and (lacked such as soldered ball in the presence of being deformed Fall into).The means such as x-ray fluoroscopy, ultrasonic scanning can be now combined, can be with quick positioning question point, modified technique.
Depending on the structure and form of foregoing each test circuit plate can be according to actual demands, it only can be included to be led The circuit structure of general character test, can also only include the circuit structure to carry out short-circuit test, naturally it is also possible to include simultaneously Both circuit structures, such as its form can be refering to shown in Fig. 5.
It should be appreciated that the technical concepts and features of above-described embodiment only to illustrate the invention, its object is to allow be familiar with this The personage of item technology can understand present disclosure and implement according to this, and it is not intended to limit the scope of the present invention.It is all The equivalent change or modification made according to spirit of the invention, should all be included within the scope of the present invention.

Claims (10)

1. a kind of electrical testing method of face-down bonding, it is characterised in that including:
The first metal that a plurality of electric isolations each other are provided with first test circuit plate, the first test circuit plate is provided Figure,
The second metal that a plurality of electric isolations each other are provided with second test circuit plate, the second test circuit plate is provided Figure,
N number of metal soldered ball along setting route interval distribution is set, and N is positive integer,
There is provided main by a probe, test power supply, electric current and/or voltage test device and the survey in sequential series formed of another probe Die trial block;
And, N number of metal soldered ball is alternately electrically connected through a plurality of first metallic patterns, a plurality of second metallic patterns, from And N number of metal soldered ball is connected to form a series circuit, and by two described probes respectively with the series circuit two End is electrically connected to form a test circuit, then observe test circuit whether normally;
Or, N number of metal soldered ball and the first test circuit plate or the second test circuit plate are coordinated, and make any one metal welding Ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, then by two described probes respectively with 1st metal soldered ball, n-th metal soldered ball are electrically connected to form a test circuit, then whether observe test circuit short-circuit.
2. the electrical testing method of face-down bonding according to claim 1, it is characterised in that including:
A probe therein and one first pad is in electrical contact, first pad and only electrically connected with the 1st metal soldered ball The second metallic pattern electrically combine;And
Another probe and one second pad is in electrical contact, second pad and only electrically connected with n-th metal soldered ball Two metallic patterns are electrically combined;
First pad and the second pad are arranged on the second test circuit plate.
3. the electrical testing method of face-down bonding according to claim 1 or 2, it is characterised in that:In N number of metal soldered ball Any one metal soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball simultaneously with the different loci on surface with One first metallic pattern, one second metallic pattern are in electrical contact.
4. the electrical testing method of face-down bonding according to claim 3, it is characterised in that specifically include:
In the first metallic pattern that a plurality of electric isolations each other are deposited on the first test circuit plate,
In the second metallic pattern that a plurality of electric isolations each other are deposited on the second test circuit plate,
In the first test circuit plate and/or the second test circuit plate metallization medium layer,
Correspond on the first test circuit plate and/or the second test circuit plate at solder joint and pad and process window,
The deposited metal welding column at bond pad locations,
Flip chip bonding is carried out using upside-down mounting welding machine, includes the welded ball array of N number of metal soldered ball to be formed.
5. the electrical testing method of face-down bonding according to claim 4, it is characterised in that including:
At least through photoetching, stripping and electron-beam evaporation mode, in depositing on the first test circuit plate, the second test circuit plate One metallic pattern, the second metallic pattern;
And/or, at least through photoetching and reactive ion etching mode on the first test circuit plate and/or the second test circuit plate Corresponding to processing window at solder joint and pad;
And/or, at least through photoetching and thermal evaporation methods corresponding to the deposition that metal welding column is carried out at solder joint, the metal welding Post includes In posts.
6. the electrical testing method of face-down bonding according to claim 4, it is characterised in that including:If test circuit is short Road, then judge that face-down bonding has quality problems.
7. a kind of electrical testing system of face-down bonding, it is characterised in that including:
First test circuit plate, the first metallic pattern with a plurality of electric isolations each other,
Second test circuit plate, the second metallic pattern with a plurality of electric isolations each other,
Along N number of metal soldered ball of setting route interval distribution, N is positive integer,
Mainly by a probe, test power supply, electric current and/or voltage test device and another probe test mould in sequential series formed Block;
When carrying out conduction test, N number of metal soldered ball is alternately electrically connected and shape through the first metallic pattern, the second metallic pattern Into a series circuit, and initial and end Duan Duan of the two described probes respectively with the series circuit is electrically connected to form a test Circuit;
When carrying out short-circuit test, N number of metal soldered ball and the first test circuit plate or the second test circuit plate coordinate, and any Individual metal soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, and two described probes Respectively a test circuit is electrically connected to form with the 1st metal soldered ball, n-th metal soldered ball.
8. the electrical testing system of face-down bonding according to claim 7, it is characterised in that:Only with the 1st metal soldered ball The first metallic pattern or the second metallic pattern of electrical connection are also with being arranged on the first test circuit plate or the second test circuit plate The first pad electrically combine, the first metallic pattern or the second metallic pattern only electrically connected with n-th metal soldered ball is also with setting The second pad put on the first test circuit plate or the second test circuit plate is electrically combined, wherein a probe and the first pad electricity Property contact, another probe and the second pad are in electrical contact.
9. the electrical testing system of face-down bonding according to claim 8, it is characterised in that:First pad and second Pad is arranged on the second test circuit plate, the second metallic pattern and the first pad only electrically connected with the 1st metal soldered ball Electrically combine, the second metallic pattern only electrically connected with n-th metal soldered ball is electrically combined with the second pad.
10. the electrical testing system of the face-down bonding according to any one of claim 7-9, it is characterised in that:N number of gold Belong to any one metal soldered ball in soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball while with surface not It is in electrical contact with site and one first metallic pattern, one second metallic pattern.
CN201710504024.4A 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding Active CN107167685B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710504024.4A CN107167685B (en) 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710504024.4A CN107167685B (en) 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding

Publications (2)

Publication Number Publication Date
CN107167685A true CN107167685A (en) 2017-09-15
CN107167685B CN107167685B (en) 2019-09-06

Family

ID=59826742

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710504024.4A Active CN107167685B (en) 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding

Country Status (1)

Country Link
CN (1) CN107167685B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110488134A (en) * 2019-07-10 2019-11-22 中国科学院上海技术物理研究所 A kind of fast verification assessment chip and method for focal plane device inverse bonding technique
CN111725152A (en) * 2020-06-12 2020-09-29 北京时代民芯科技有限公司 Plastic package daisy chain circuit structure based on flip chip bonding and test method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1823277A (en) * 2003-08-05 2006-08-23 飞思卡尔半导体公司 Integrated circuit with test pad structure and method of testing
CN203275467U (en) * 2013-04-17 2013-11-06 竞陆电子(昆山)有限公司 Low-resistance and open-short synchronous test system of PCB board
CN104515874A (en) * 2013-09-26 2015-04-15 北大方正集团有限公司 Adapter plate used for circuit board testing and test method and test device
US20150208504A1 (en) * 2011-11-16 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Test Structure and Method of Testing Electrical Characteristics of Through Vias
CN205374651U (en) * 2015-12-25 2016-07-06 南通富士通微电子股份有限公司 Short -circuit test carrier is opened to base plate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1823277A (en) * 2003-08-05 2006-08-23 飞思卡尔半导体公司 Integrated circuit with test pad structure and method of testing
US20150208504A1 (en) * 2011-11-16 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Test Structure and Method of Testing Electrical Characteristics of Through Vias
CN203275467U (en) * 2013-04-17 2013-11-06 竞陆电子(昆山)有限公司 Low-resistance and open-short synchronous test system of PCB board
CN104515874A (en) * 2013-09-26 2015-04-15 北大方正集团有限公司 Adapter plate used for circuit board testing and test method and test device
CN205374651U (en) * 2015-12-25 2016-07-06 南通富士通微电子股份有限公司 Short -circuit test carrier is opened to base plate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110488134A (en) * 2019-07-10 2019-11-22 中国科学院上海技术物理研究所 A kind of fast verification assessment chip and method for focal plane device inverse bonding technique
CN111725152A (en) * 2020-06-12 2020-09-29 北京时代民芯科技有限公司 Plastic package daisy chain circuit structure based on flip chip bonding and test method
CN111725152B (en) * 2020-06-12 2021-12-28 北京时代民芯科技有限公司 Plastic package daisy chain circuit structure based on flip chip bonding and test method

Also Published As

Publication number Publication date
CN107167685B (en) 2019-09-06

Similar Documents

Publication Publication Date Title
US6895346B2 (en) Method for test conditions
CN103063886B (en) Probe card for probing integrated circuit
CN102456668B (en) Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)
US20170336440A1 (en) 3d chip testing through micro-c4 interface
CN102937695B (en) Silicon through-hole ultrathin wafer testing structure and testing method
TWI329902B (en) Bump test units and apparatus, and methods for testing bumps
CN104779238B (en) A kind of detection structure and detection method of wafer bond quality
CN103344791A (en) Test substrate and probe card manufactured by means of test substrate
TW200809215A (en) Contactor assembly
CN107167685B (en) The electrical testing method and system of face-down bonding
KR20130083824A (en) Semiconductor integrated circuit device inspection method and semiconductor integrated circuit device
TWI287097B (en) Circuit pattern inspection apparatus, circuit pattern inspection method, and recording medium
CN105845597A (en) Through-silicon-via stacked chip test method
US11307245B2 (en) Method for measuring an electric property of a test sample
JP4542587B2 (en) Wiring board for electronic component inspection equipment
Marinissen et al. Contactless testing: Possibility or pipe-dream?
CN103630824A (en) Chip concurrent test system
CN110531125B (en) Space transformer, probe card and manufacturing method thereof
CN100481444C (en) A modular integrated circuit chip carrier
CN101017182A (en) Wafer-level burn-in and test
US7535239B1 (en) Probe card configured for interchangeable heads
US8378701B2 (en) Non-contact determination of joint integrity between a TSV die and a package substrate
TWI484192B (en) Probe card, inspection device and inspection method
US20040240724A1 (en) Tester and testing method
KR100798724B1 (en) Method for wafer test and probe card for the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant