CN107167685B - The electrical testing method and system of face-down bonding - Google Patents

The electrical testing method and system of face-down bonding Download PDF

Info

Publication number
CN107167685B
CN107167685B CN201710504024.4A CN201710504024A CN107167685B CN 107167685 B CN107167685 B CN 107167685B CN 201710504024 A CN201710504024 A CN 201710504024A CN 107167685 B CN107167685 B CN 107167685B
Authority
CN
China
Prior art keywords
circuit board
test circuit
test
soldered ball
metallic pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710504024.4A
Other languages
Chinese (zh)
Other versions
CN107167685A (en
Inventor
黄寓洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SUZHOU SUNA PHOTOELECTRIC Co Ltd
Original Assignee
SUZHOU SUNA PHOTOELECTRIC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SUZHOU SUNA PHOTOELECTRIC Co Ltd filed Critical SUZHOU SUNA PHOTOELECTRIC Co Ltd
Priority to CN201710504024.4A priority Critical patent/CN107167685B/en
Publication of CN107167685A publication Critical patent/CN107167685A/en
Application granted granted Critical
Publication of CN107167685B publication Critical patent/CN107167685B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention discloses a kind of electrical testing method of face-down bonding and systems.The test method includes: to provide the first test circuit board, the first metallic pattern of a plurality of electric isolations each other is provided on the first test circuit board, second test circuit board is provided, the second metallic pattern of a plurality of electric isolations each other is provided on the second test circuit board, multiple metal soldered balls along setting route interval distribution are set, are provided mainly by a probe, test power supply, electric current and/or voltage test device and the test module of another probe formation in sequential series;Then conducting shape and short-circuit test are carried out respectively.Test method provided by the invention is simple to operation, at low cost, easy to use, and chip is enough normally to be connected to, and can effectively find existing short circuit problem after can testing Flip Chip Bond Technique, can targetedly improve technique and improve the quality of flip chip bonding.

Description

The electrical testing method and system of face-down bonding
Technical field
The present invention is more particularly directed to a kind of electrical testing method of face-down bonding and systems, belong to semiconductors manufacture and measurement skill Art field.
Background technique
Upside-down mounting interconnection technique is widely used in semiconductor fabrication process.This technology can be realized between two kinds of chips Hybrid connections, solder joint density is high, and good reliability is widely used in focus planar detector array (FPA), LED light source array, The connection of the corresponding reading circuit of the photoelectric chips such as spatial light modulator array or driving circuit.But photoelectric chip is past Past expensive, the Diameter of Solder Ball in Flip Chip Bond Technique is generally at 20 μm or so, and directly test is not only with high costs, but also tests Difficulty is also very high.
Summary of the invention
The main purpose of the present invention is to provide a kind of electrical testing method of face-down bonding and systems, to overcome existing skill The deficiency of art.
For realization aforementioned invention purpose, the technical solution adopted by the present invention includes:
The embodiment of the invention provides a kind of electrical testing methods of face-down bonding, comprising:
First test circuit board is provided, is provided with the first of a plurality of electric isolations each other on the first test circuit board Metallic pattern,
Second test circuit board is provided, is provided with the second of a plurality of electric isolations each other on the second test circuit board Metallic pattern,
N number of metal soldered ball along setting route interval distribution is set, N is positive integer,
It provides mainly by a probe, test power supply, electric current and/or voltage test device and the formation in sequential series of another probe Test module;
And N number of metal soldered ball is alternately electrically connected through a plurality of first metallic patterns, a plurality of second metallic patterns Connect, so that N number of metal soldered ball be connected to form a series circuit, and by two probes respectively with the series circuit Both ends be electrically connected to form a test circuit, then observe test circuit whether normally;
Alternatively, by N number of metal soldered ball and the first test circuit board or the second test circuit board cooperation, and make any one gold Belonging to soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, then two probes are divided Be not electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball, then observe test circuit it is whether short-circuit.
The embodiment of the invention also provides a kind of electrical testing systems of face-down bonding, comprising:
First test circuit board, the first metallic pattern with a plurality of electric isolations each other,
Second test circuit board, the second metallic pattern with a plurality of electric isolations each other,
Along N number of metal soldered ball of setting route interval distribution, N is positive integer,
Mainly by a probe, test power supply, electric current and/or voltage test device and the survey of another probe formation in sequential series Die trial block;
When carrying out conduction test, which is alternately electrically connected through the first metallic pattern, the second metallic pattern And a series circuit is formed, and two probes are electrically connected to form one with the initial and end Duan Duan of the series circuit respectively Test circuit;
When carrying out short-circuit test, N number of metal soldered ball and the first test circuit board or the second test circuit board cooperation, and Any one metal soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, and described two Probe is electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball respectively.
Compared with prior art, the invention has the advantages that test method provided by the invention is simple to operation, cost Low, easy to use, chip is enough normally to be connected to, and can effectively find that existing short circuit is asked after can testing Flip Chip Bond Technique Topic can targetedly improve technique and improve the quality of flip chip bonding.
Detailed description of the invention
Fig. 1 is the graphic structure schematic diagram that conduction test designs in the embodiment of the present invention 1;
Fig. 2 is the partial enlargement structural representation that conduction test designs in the embodiment of the present invention 1;
Fig. 3 is the detailed structure schematic diagram of conduction test design configuration in the embodiment of the present invention 1;
Fig. 4 is the graphic structure schematic diagram that short-circuit test designs in the embodiment of the present invention 2;
Fig. 5 is that the conduction and short circuit of the first test circuit board and/or the second test circuit version in the embodiment of the present invention are surveyed Attempt shape distribution schematic diagram.
Specific embodiment
In view of deficiency in the prior art, inventor is studied for a long period of time and is largely practiced, and is able to propose of the invention Technical solution.The technical solution, its implementation process and principle etc. will be further explained as follows.
On the one hand the embodiment of the present invention provides a kind of electrical testing method of face-down bonding, comprising:
First test circuit board is provided, is provided with the first of a plurality of electric isolations each other on the first test circuit board Metallic pattern,
Second test circuit board is provided, is provided with the second of a plurality of electric isolations each other on the second test circuit board Metallic pattern,
N number of metal soldered ball along setting route interval distribution is set, N is positive integer,
It provides mainly by a probe, test power supply, electric current and/or voltage test device and the formation in sequential series of another probe Test module;
And N number of metal soldered ball is alternately electrically connected through a plurality of first metallic patterns, a plurality of second metallic patterns Connect, so that N number of metal soldered ball be connected to form a series circuit, and by two probes respectively with the series circuit Both ends be electrically connected to form a test circuit, then observe test circuit whether normally;
Alternatively, by N number of metal soldered ball and the first test circuit board or the second test circuit board cooperation, and make any one gold Belonging to soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, then two probes are divided Be not electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball, then observe test circuit it is whether short-circuit.
Further, which comprises
A probe therein and one first pad is in electrical contact, first pad and only with the 1st metal soldered ball electricity Second metallic pattern of connection electrically combines;And
Another probe and one second pad is in electrical contact, it second pad and is only electrically connected with n-th metal soldered ball The second metallic pattern electrically combine;
First pad and the second pad are arranged on the second test circuit board.
Further, any one in N number of metal soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball Metal soldered ball is in electrical contact with the different loci on surface and one first metallic pattern, one second metallic pattern simultaneously.
Further, the method specifically includes:
In depositing the first metallic pattern of a plurality of electric isolations each other on the first test circuit board,
In depositing the second metallic pattern of a plurality of electric isolations each other on the second test circuit board,
Circuit board metallization medium layer is tested in the first test circuit board and/or second,
Correspond at solder joint and pad on the first test circuit board and/or the second test circuit board and process window,
The deposited metal welding column at bond pad locations,
Flip chip bonding is carried out using upside-down mounting welding machine, to form the welded ball array for including N number of metal soldered ball.
In some more specific embodiments, which comprises at least through photoetching, removing and electron beam evaporation side Formula tests on circuit board in the first test circuit board, second and deposits the first metallic pattern, the second metallic pattern.
In some more specific embodiments, which comprises at least through photoetching and reactive ion etching mode Correspond at solder joint and pad on the first test circuit board and/or the second test circuit board and processes window;
In some more specific embodiments, which comprises at least through photoetching and thermal evaporation methods in correspondence The deposition of metal welding column is carried out at solder joint, the metal welding column includes In column.
Further, which comprises if test short circuit, judging face-down bonding, there are quality problems.
The other side of the embodiment of the present invention additionally provides a kind of electrical testing system of face-down bonding, comprising:
First test circuit board, the first metallic pattern with a plurality of electric isolations each other,
Second test circuit board, the second metallic pattern with a plurality of electric isolations each other,
Along N number of metal soldered ball of setting route interval distribution, N is positive integer,
Mainly by a probe, test power supply, electric current and/or voltage test device and the survey of another probe formation in sequential series Die trial block;
When carrying out conduction test, which is alternately electrically connected through the first metallic pattern, the second metallic pattern And a series circuit is formed, and two probes are electrically connected to form one with the initial and end Duan Duan of the series circuit respectively Test circuit;
When carrying out short-circuit test, N number of metal soldered ball and the first test circuit board or the second test circuit board cooperation, and Any one metal soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, and described two Probe is electrically connected to form a test circuit with the 1st metal soldered ball, n-th metal soldered ball respectively.
Further, the first metallic pattern or the second metallic pattern being only electrically connected with the 1st metal soldered ball also with setting The first pad on the first test circuit board or the second test circuit board electrically combines, and is only electrically connected with n-th metal soldered ball The first metallic pattern or the second metallic pattern also be arranged in first test circuit board or second test circuit board on second Pad electrically combines, wherein a probe and the first pad are in electrical contact, another probe and the second pad are in electrical contact.
Further, first pad and the second pad are arranged on the second test circuit board, only with the 1st metal Second metallic pattern of soldered ball electrical connection is electrically combined with the first pad, the second metal being only electrically connected with n-th metal soldered ball Figure is electrically combined with the second pad.
Further, any one in N number of metal soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball Metal soldered ball is in electrical contact with the different loci on surface and one first metallic pattern, one second metallic pattern simultaneously.
Test method provided by the invention is simple, at low cost, easy to use, and chip is after can testing Flip Chip Bond Technique Enough normal connections, and can effectively find existing short circuit problem, can targetedly improve technique and improve the matter of flip chip bonding Amount.
The technical solution, its implementation process and principle etc. will be further explained in conjunction with specific embodiments as follows It is bright.
The present invention deposits corresponding metallic pattern on it and deposits soldered ball later by a pair of of test circuit board of production Metal carries out flip chip bonding after passivation aperture, and completes to test.
1 conduction test of embodiment
The present embodiment is related to testing the conduction of selected one or two lines road on a circuit board.More Body, as shown in fig.1, the present embodiment system surveys the conduction of A, B point of two selected routes on a circuit board (wherein, the path of connecting test can be several row/column pixels, be also possible to a string of pixels in some corner, as needed for examination Depending on), corresponding detection method is as follows:
It provides mainly by a probe, test power supply, electric current and/or voltage test device and the formation in sequential series of another probe Test module;
A pair of of test circuit board (the first test circuit board and the second test circuit board) is provided, and according to side known to industry Case, it is plural in being deposited on the first test circuit board, the second test circuit board by modes such as photoetching, removing and electron beam evaporations First metallic pattern of a electric isolation each other, the second metallic pattern (the first metallic pattern is also referred to as upper layer metallic pattern, Two metallic patterns are also referred to as lower metal figure, and upper layer metallic pattern and lower metal figure can be identical or not identical , and can be designed according to actual demand).
Using mode known to industry in the first test circuit board and/or the second test circuit board metallization medium layer (such as oxygen SiClx or silicon nitride etc.),
Solder joint and weldering are corresponded on the first test circuit board and/or the second test circuit board using mode known to industry Pan Chu processes window,
According to scheme known to industry, the heavy of In column is carried out corresponding at solder joint by modes such as photoetching and thermal evaporations Product;
According to scheme known to industry, flip chip bonding is carried out using upside-down mounting welding machine, to form the soldered ball battle array for including N number of In ball Column, N is positive integer;
N number of In ball is alternately electrically connected (the first metal through a plurality of first metallic patterns, a plurality of second metallic patterns The connection type of figure and the second metallic pattern and In ball is seen shown in Fig. 2), so that N number of In ball be connected to be formed a string Join circuit (refering to shown in Fig. 3), in N number of In ball except the 1st In ball (corresponding to A point) and n-th In ball (corresponding to B point) it Any one outer In ball is electrically connected with simultaneously with the different loci on surface and one first metallic pattern, one second metallic pattern Two probes are electrically connected to form a test circuit, then observe test by touching with the both ends of the series circuit respectively Circuit whether normally.
2 short-circuit test of embodiment
The present embodiment is related to testing the one or more selected route on a circuit board with the presence or absence of short circuit. One of typical resolution chart is as shown in Figure 4.Corresponding test method is as follows:
It provides test module (same as Example 1);
One test circuit board (can be the second test circuit board) is provided, can be made in the way of embodiment 1;
By N number of In ball and the second test circuit board cooperation, and make any one In ball only can be with corresponding one second metal Figure is in electrical contact, the second metallic pattern electrical connection the first pad of setting being electrically connected with first In ball, with n-th In ball electricity The second metallic pattern electrical connection of connection is provided with the second pad, and (the first pad and the second pad are arranged electric in the second test simultaneously On the plate of road), then two probes are electrically connected to form a test circuit with the 1st In ball, n-th In ball respectively, then Whether observation test circuit is short-circuit.
If test short circuit, judge that (such as soldered ball exists to be deformed etc. and lacks face-down bonding there are quality problems It falls into).At this time technique can be improved with quick positioning question point in conjunction with means such as x-ray fluoroscopy, ultrasonic scannings.
It, can be only comprising to be led depending on the structure and form of aforementioned each test circuit board can be according to actual demands The circuit structure of general character test, can also be only comprising the circuit structure to carry out short-circuit test, naturally it is also possible to include simultaneously Both circuit structures, such as its form can be refering to shown in Fig. 5.
It should be appreciated that the technical concepts and features of above-described embodiment only to illustrate the invention, its object is to allow be familiar with this The personage of item technology cans understand the content of the present invention and implement it accordingly, and it is not intended to limit the scope of the present invention.It is all Equivalent change or modification made by Spirit Essence according to the present invention, should be covered by the protection scope of the present invention.

Claims (10)

1. a kind of electrical testing method of face-down bonding, characterized by comprising:
First test circuit board is provided, the first metal of a plurality of electric isolations each other is provided on the first test circuit board Figure,
Second test circuit board is provided, the second metal of a plurality of electric isolations each other is provided on the second test circuit board Figure,
N number of metal soldered ball along setting route interval distribution is set, N is positive integer,
Survey mainly by a probe, test power supply, electric current and/or voltage test device and the formation in sequential series of another probe is provided Die trial block;
And be alternately electrically connected N number of metal soldered ball through a plurality of first metallic patterns, a plurality of second metallic patterns, from And N number of metal soldered ball is connected to form a series circuit, and by two probes respectively with the series circuit two End be electrically connected to form a test circuit, then observe test circuit whether normally;
Alternatively, by N number of metal soldered ball and the first test circuit board or the second test circuit board cooperation, and make any one metal welding Ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, then by a probe and the 1st metal welding Ball electrical connection, another probe and n-th metal soldered ball are electrically connected to form a test circuit, then observe whether test circuit short Road.
2. the electrical testing method of face-down bonding according to claim 1, characterized by comprising:
A probe therein and one first pad is in electrical contact, it first pad and is only electrically connected with the 1st metal soldered ball The second metallic pattern electrically combine;And
Another probe and one second pad is in electrical contact, second pad and be only electrically connected with n-th metal soldered ball Two metallic patterns electrically combine;
First pad and the second pad are arranged on the second test circuit board.
3. the electrical testing method of face-down bonding according to claim 1 or 2, it is characterised in that: in N number of metal soldered ball Any one metal soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball simultaneously with the different loci on surface with One first metallic pattern, one second metallic pattern are in electrical contact.
4. the electrical testing method of face-down bonding according to claim 3, it is characterised in that specifically include:
In depositing the first metallic pattern of a plurality of electric isolations each other on the first test circuit board,
In depositing the second metallic pattern of a plurality of electric isolations each other on the second test circuit board,
Circuit board metallization medium layer is tested in the first test circuit board and/or second,
Correspond at solder joint and pad on the first test circuit board and/or the second test circuit board and process window,
The deposited metal welding column at bond pad locations,
Flip chip bonding is carried out using upside-down mounting welding machine, to form the welded ball array for including N number of metal soldered ball.
5. the electrical testing method of face-down bonding according to claim 4, characterized by comprising:
At least through photoetching, removing and electron-beam evaporation mode, circuit board is tested in first, deposits the on the second test circuit board One metallic pattern, the second metallic pattern;
And/or at least through photoetching and reactive ion etching mode on the first test circuit board and/or the second test circuit board Corresponding to processing window at solder joint and pad;
And/or corresponding at solder joint the deposition for carrying out metal welding column, the metal welding at least through photoetching and thermal evaporation methods Column includes In column.
6. the electrical testing method of face-down bonding according to claim 4, characterized by comprising: if test circuit is short Road then judges that there are quality problems for face-down bonding.
7. a kind of electrical testing system of face-down bonding, characterized by comprising:
First test circuit board, the first metallic pattern with a plurality of electric isolations each other,
Second test circuit board, the second metallic pattern with a plurality of electric isolations each other,
Along N number of metal soldered ball of setting route interval distribution, N is positive integer,
Mainly by a probe, test power supply, electric current and/or voltage test device and the test mould of another probe formation in sequential series Block;
When carrying out conduction test, which is alternately electrically connected and shape through the first metallic pattern, the second metallic pattern At a series circuit, and two probes are electrically connected to form a test with the initial and end Duan Duan of the series circuit respectively Circuit;
When carrying out short-circuit test, N number of metal soldered ball and the first test circuit board or the second test circuit board cooperation, and it is any A metal soldered ball only can be in electrical contact with corresponding one first metallic pattern or one second metallic pattern, and a probe and the 1st Metal soldered ball electrical connection, another probe and n-th metal soldered ball are electrically connected to form a test circuit.
8. the electrical testing system of face-down bonding according to claim 7, it is characterised in that: only with the 1st metal soldered ball The first metallic pattern or the second metallic pattern of electrical connection are also with setting on the first test circuit board or the second test circuit board The first pad electrically combine, the first metallic pattern or the second metallic pattern being only electrically connected with n-th metal soldered ball also with set The second pad set on the first test circuit board or the second test circuit board electrically combines, wherein a probe and the first pad electricity Property contact, another probe and the second pad are in electrical contact.
9. the electrical testing system of face-down bonding according to claim 8, it is characterised in that: first pad and second Pad is arranged on the second test circuit board, the second metallic pattern and the first pad being only electrically connected with the 1st metal soldered ball It electrically combines, is only electrically combined with the second metallic pattern of n-th metal soldered ball electrical connection with the second pad.
10. the electrical testing system of the face-down bonding according to any one of claim 7-9, it is characterised in that: N number of gold Any one metal soldered ball in category soldered ball in addition to the 1st metal soldered ball and n-th metal soldered ball is while with surface not It is in electrical contact with site and one first metallic pattern, one second metallic pattern.
CN201710504024.4A 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding Active CN107167685B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710504024.4A CN107167685B (en) 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710504024.4A CN107167685B (en) 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding

Publications (2)

Publication Number Publication Date
CN107167685A CN107167685A (en) 2017-09-15
CN107167685B true CN107167685B (en) 2019-09-06

Family

ID=59826742

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710504024.4A Active CN107167685B (en) 2017-06-27 2017-06-27 The electrical testing method and system of face-down bonding

Country Status (1)

Country Link
CN (1) CN107167685B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110488134A (en) * 2019-07-10 2019-11-22 中国科学院上海技术物理研究所 A kind of fast verification assessment chip and method for focal plane device inverse bonding technique
CN111725152B (en) * 2020-06-12 2021-12-28 北京时代民芯科技有限公司 Plastic package daisy chain circuit structure based on flip chip bonding and test method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1823277A (en) * 2003-08-05 2006-08-23 飞思卡尔半导体公司 Integrated circuit with test pad structure and method of testing
CN203275467U (en) * 2013-04-17 2013-11-06 竞陆电子(昆山)有限公司 Low-resistance and open-short synchronous test system of PCB board
CN104515874A (en) * 2013-09-26 2015-04-15 北大方正集团有限公司 Adapter plate used for circuit board testing and test method and test device
CN205374651U (en) * 2015-12-25 2016-07-06 南通富士通微电子股份有限公司 Short -circuit test carrier is opened to base plate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8993432B2 (en) * 2011-11-16 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Test structure and method of testing electrical characteristics of through vias

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1823277A (en) * 2003-08-05 2006-08-23 飞思卡尔半导体公司 Integrated circuit with test pad structure and method of testing
CN203275467U (en) * 2013-04-17 2013-11-06 竞陆电子(昆山)有限公司 Low-resistance and open-short synchronous test system of PCB board
CN104515874A (en) * 2013-09-26 2015-04-15 北大方正集团有限公司 Adapter plate used for circuit board testing and test method and test device
CN205374651U (en) * 2015-12-25 2016-07-06 南通富士通微电子股份有限公司 Short -circuit test carrier is opened to base plate

Also Published As

Publication number Publication date
CN107167685A (en) 2017-09-15

Similar Documents

Publication Publication Date Title
US6895346B2 (en) Method for test conditions
CN102937695B (en) Silicon through-hole ultrathin wafer testing structure and testing method
TWI329902B (en) Bump test units and apparatus, and methods for testing bumps
TW528874B (en) Non-destructive inspection method
CN107167685B (en) The electrical testing method and system of face-down bonding
US4881029A (en) Semiconductor integrated circuit devices and methods for testing same
CN100358122C (en) Apparatus and method for testing conductive bumps
KR20130083824A (en) Semiconductor integrated circuit device inspection method and semiconductor integrated circuit device
CN109669113A (en) The method for testing the device and method and manufacturing semiconductor devices of interconnection circuit
US9754847B2 (en) Circuit probing structures and methods for probing the same
CN103630824A (en) Chip concurrent test system
CN206282851U (en) Semi-conductor test structure
KR20130083825A (en) Detection method for semiconductor integrated circuit device, and semiconductor integrated circuit device
CN101017182A (en) Wafer-level burn-in and test
US8378701B2 (en) Non-contact determination of joint integrity between a TSV die and a package substrate
CN106771405B (en) A kind of spherical grid array integrated circuit interface adapter
US20060066327A1 (en) Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process
CN109698138B (en) Semiconductor failure positioning test unit and failure positioning method thereof
CN111653497A (en) Test structure and test method
CN105990169B (en) The detection method of chip through-hole connection defect
KR101320934B1 (en) Semiconductor device and manufacturing method thereof
Yang et al. Detection of failure sites by focused ion beam and nano-probing in the interconnect of three-dimensional stacked circuit structures
JP2002203882A (en) Method for manufacturing semiconductor device
TWI397691B (en) Probe station device
US11081469B2 (en) Three-dimensional integrated circuit test and improved thermal dissipation

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant