US11307245B2 - Method for measuring an electric property of a test sample - Google Patents

Method for measuring an electric property of a test sample Download PDF

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US11307245B2
US11307245B2 US16/753,607 US202016753607A US11307245B2 US 11307245 B2 US11307245 B2 US 11307245B2 US 202016753607 A US202016753607 A US 202016753607A US 11307245 B2 US11307245 B2 US 11307245B2
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test sample
layer
terminal
stack
electrically
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US20210231731A1 (en
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Alberto Cagliani
Frederik Westergaard Østerberg
Chia-Hung Wei
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KLA Corp
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KLA Corp
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Assigned to KLA CORPORATION reassignment KLA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WEI, CHIA-HUNG, CAGLIANI, Alberto, OSTERBERG, FREDERIK WESTERGAARD
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
    • G01R1/06733—Geometry aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2648—Characterising semiconductor materials
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1677—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
    • H01L27/222—
    • H01L43/02—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0491—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets for testing integrated circuits on wafers, e.g. wafer-level test cartridge
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]

Definitions

  • the present invention relates to measuring at least one electric property of a test sample such as a multilayer stack composed of electrically conductive layers and at least one tunnelling barrier, for example a magnetic tunnel junction (MTJ).
  • a test sample such as a multilayer stack composed of electrically conductive layers and at least one tunnelling barrier, for example a magnetic tunnel junction (MTJ).
  • MTJ magnetic tunnel junction
  • microscopic multi-point probes are used on for example magnetoresistive random-access memory (MRAM) wafers for current-in-plane tunnelling measurement for determining a number of electric properties of the test sample, i.e. for testing that the wafer is according to specifications.
  • MRAM magnetoresistive random-access memory
  • the electric properties may be the resistance area product, the sheet resistance of a first electrically conductive sheet on top of the tunnelling barrier, the sheet resistance of a second sheet below the tunnelling barrier (bottom sheet), and the magneto tunnelling resistance.
  • the test sample may contain any number of tunnelling barriers and electrically conductive sheets, deposited on top of each other; in such case, multiple resistance area products may be defined. It is also possible that a sample containing more than one tunnelling barrier is modelled by a single barrier mathematical model.
  • the typical method of placing the multi-point probe above the wafer, and contacting the top surface of the wafer with the tips of the electrodes of the probe may result in an erroneous measurement if, for example in the case of a single tunnelling barrier model, the sheet resistance of the top sheet is lower than the sheet resistance of the bottom sheet.
  • a method for measuring an electrically property of a multilayer test sample such as a magnetic tunnel junction comprising:
  • said multilayer test sample having a stack including at least a first layer and a second layer, said stack being above an electrically insulating layer,
  • said first test sample terminal, said second test sample terminal, and said stack being electrically insulated from each other
  • said method further comprising:
  • measuring circuit including a first measuring terminal, and a second measuring terminal
  • a third test sample terminal above the electrically insulating layer for a third connection with a measurement circuit may be provided. And the third measuring terminal may be contacted with the third test sample terminal.
  • a fourth test sample terminal above the electrically insulating layer for a fourth connection with a measurement circuit may be provided. And the fourth measuring terminal may be contacted with the fourth test sample terminal.
  • Embedded means/features may be provided or embedded in, the test sample for embedded measuring of the electronic property, i.e. by embedded measuring is meant measuring the electronic property by means of features embedded in the test sample during the microfabrication of the test sample.
  • the embedded means may be constituted by the two terminals, and the electrically conductive paths below the stack and terminals.
  • the electrically insulated layer below the stack may support the stack. Similarly, the electrically insulated layer may support the test sample terminals.
  • the first layer may be made of an electrically conductive material
  • the second layer may also be made of an electrically conductive material.
  • one of the two layers may be made of an electric insulator.
  • Each of the first layer and/or the second layer may be subdivided into multiple layers/sheets.
  • An electric insulator may also be sandwiched between the first layer and the second layer such that the stack is a three-layer stack—the electric insulator constituting a tunnelling barrier/layer.
  • the multilayer test sample may be a semiconductor wafer having multiple conductive and tunneling layers.
  • the multilayer test may for example be a magnetoresistive random-access memory, wherein each memory cell may be constituted by a magnetic tunnel junction—each junction may be constituted by a pillar.
  • first (conductive) layer There may be a high contact resistance barrier between the first (conductive) layer, and the second (conductive) layer such as Schottky barrier.
  • the stack may comprise the electronics for the desired purpose of the dies of the semiconductor wafer i.e. the two layers may be for a memory purpose or for a sensor purpose.
  • the wafer is to be understood as a substrate for microelectronic devices built in during the microfabrication process of the wafer.
  • the microelectronics may comprise an electronic component directed towards the desired purpose as well as circuits or components for controlling the electronic component, i.e. a memory cell and a switch for the memory cell for example.
  • the wafer may be fabricated by etching and/or layer growth, which may be repeated in a number of steps in a usual wafer fabrication method.
  • the measuring circuit may include a movable probe for moving the first measuring terminal and the second measuring terminal to the test sample such that the contact between the first measuring terminal and the first test sample terminal and also the second measuring terminal and the second test sample terminal may be established.
  • the first test sample terminal and second test sample terminal may each constitute a landing pad for each of the two measuring terminals, i.e. such that a measuring terminal may be brought into contact (electrically) with a test sample for a measuring terminal to land on.
  • Each of the first and the second test sample terminals may be manufactured during the manufacturing of the semiconductor wafer by etching each test sample terminal out as an island, i.e. etching around the area of the semiconductor wafer, which is designated the test sample terminal such that a protruding structure remains.
  • the etching may extend through the three-layer stack (constituting an MTJ stack for example) such that the test sample in itself has the same three layers as the rest of the wafer where there are no etchings.
  • test sample terminal may be manufactured such that the material of the terminal is only deposited/grown in the area designated for the test sample terminal.
  • test sample terminals may be positioned in the scribe lines of the test sample, i.e. the lines dividing the test sample into the respective dies having the integrated circuits constituting the electronics.
  • the scribe lines are typically arranged as a rectangular grid for dicing the dies, i.e. with gridlines being orthogonal.
  • a scribe line may have a width between 20 to 200 microns, such as 75 to 125 microns or such as 100 microns.
  • test sample terminals may be made simultaneously as the electronics/integrated circuits of the dies, i.e. the area of the dies and the scribe lines is exposed with the material of the first layer in one step. In a second step, the test sample terminals may be insulated.
  • the first layer of a test sample terminal, and the first layer of the stack may be in the same plane.
  • test sample terminals may be placed next to each other, such as four test sample terminals. They may have a pitch (distance between them) matching the pitch of a multipoint probe for example, i.e. the second test sample terminal may be adjacent the first test sample terminal.
  • a third test sample terminal may be placed adjacent to the second test sample terminal, and a fourth test sample terminal may, be placed adjacent to the third test sample terminal.
  • Such four test sample terminals may be placed linearly with respect to each other, i.e. constituting a row of test sample terminals.
  • the electrically insulated layer supports the upper layers, and it may also be used for embedding electric wiring, i.e. electric interconnections between different parts of the wafer. Several of such metallization layers may be provided for electric interconnections through the wafer.
  • the electric wiring such as the first electrically conductive path and the second electrically conductive path may be manufactured during manufacturing of the wafer as copper lines deposited on the electrically insulated layer before the paths are embedded by further depositing the material of the electrically insulated layer.
  • Electric connections between the layers may be made by vertical vias, i.e. vias extending in a direction from one layer to another, which will be in a vertical direction when the wafer is on a horizontal surface.
  • a first via may interconnect the first electrically conductive path with the first test sample terminal.
  • Such vias may be made of tungsten, copper, copper nitride, tantalum, tantalum nitride, cobalt, ruthenium.
  • Two separate vias or more may be used for establishing the vertical part of the path, which may interconnect a test sample terminal and the stack to be tested—the electrically conductive path may have two vertical parts of the path (below the test sample terminal and below the stack, respectively) and one horizontal part. Both of the vertical parts may be constituted by two or more vias instead of only one via.
  • the electrically insulating layer may be made of an electrically insulating material such that the electric wiring in the layer defines the circuit paths and where current may flow and the current is confined to the defined paths.
  • Two electrically conductive paths leading to separate test sample terminals may constitute a circuit together with the MTJ stack, for leading a supply current from a first test sample terminal to the MTJ stack and a return current back to a second test sample terminal.
  • a stack including at least a first layer and a second layer, said stack being above an electrically insulating layer,
  • said first test sample terminal, said second test sample terminal, and said stack being electrically insulated from each other
  • said multilayer test sample further comprising:
  • FIG. 1 shows an exploded view of a test sample.
  • FIG. 2 shows a test sample
  • FIG. 3 a shows a test sample
  • FIG. 3 b shows an enlarged view of part of FIG. 3 a.
  • FIG. 4 a shows a test sample
  • FIG. 4 b shows an enlarged view of part of FIG. 4 a.
  • FIG. 1 shows an exploded view of a test sample
  • the test sample 10 has five layers wherein the top three layers constitute a magnetic tunnel junction (MTJ), i.e. a MTJ stack.
  • MTJ magnetic tunnel junction
  • the test sample may constitute a semiconductor wafer comprising at least two electrically conductive layers and a tunnelling electrically insulating layer sandwiched in the middle, for example an MTJ.
  • the top layer 12 of the MTJ stack may or may not contain a ferromagnetic material, but it is electrically conductive.
  • the direction of the magnetization of the top layer may be changed.
  • a middle layer 14 is sandwiched between the top layer and a bottom layer 16 of the MTJ stack.
  • the middle layer is a thin electrically insulator—the thickness of which is not so large that electrons may not tunnel through it, i.e. the middle layer is a tunnelling barrier layer.
  • the bottom layer 16 may also or may not contain ferromagnetic materials, but it is electrically conductive.
  • the top layer may have a permanent magnetization
  • the bottom layer may have a variable direction of the magnetic moments. Both layers may also have a variable direction of the magnetic moments.
  • the resistance of the stack when a voltage potential is applied across the stack could depend on if the magnetization of the top and bottom layer are parallel or antiparallel, i.e. if they are parallel, the tunnelling barrier is lower than if the magnetizations are antiparallel.
  • the top layer is illustrated with a planar top surface, and the layers are in general illustrated as being parallel to each other.
  • the stack may also have more than two conductive layers and one barrier with several electrical properties, which are to be measured.
  • the layers of the test sample may have another function than as for a MRAM cell.
  • a stack having only two layers the purpose of which being a sensor.
  • the three layers of the stack are shown as seven islands in FIG. 1 , i.e. six smaller islands next to each other on a row and one larger island by itself (such as a test island constituting an MTJ stack 28 for MRAM or a sensor purpose). This is a result of etchings in the stack layers such that these islands become electrically insulated from each other, i.e. the islands are not electrically connected with each other.
  • the removed parts of the layers could also be constituted by oxide material or another material constituting an electrical insulator, i.e. such that the space between the islands themselves, and the space between an island and the MTJ stack is filled with an electrical insulator material.
  • the six smaller islands constitute six test sample terminals, which may have the purpose of landing pads such as a first landing pad 26 having a first landing area on top of the landing pad, i.e. the exposed surface 30 which is not covered by another layer on top of it—except for possibly a thin oxide layer.
  • a test sample terminal may have any in-plane shape.
  • FIG. 1 shows rectangular shapes/areas but the shape may be round, oval, elliptic, polygonal or a random shape.
  • Each landing area of each landing pad is for landing a probe tip, i.e. contacting a probe tip with the landing area such that an electric signal may be injected into the landing pad during a measurement routine, or alternatively, an electric measurement signal may be picked up.
  • terminals are provided on the test sample for a probe, and for doing a probe measurement.
  • the test sample may be inserted into a measuring device wherein the measuring terminals have fixed positions aligned with the position of the test sample terminals when the test sample is placed correctly in the measuring device.
  • the larger island 28 may the identical as of the in the MRAM cell needed to be tested, specifically one or more electrical properties of the MTJ stack.
  • a fourth layer constituting a first electrically insulating layer 18 , i.e. no current is intended to flow freely in that layer without control of the current path.
  • the fifth layer constituting a second electrically insulating layer 20 .
  • the first electrically insulating layer, and the second electrically insulating layer may be made as one electrically insulating layer.
  • the first electrically insulating layer has vias such as a first via 22 extending vertically throughout the thickness of the layer.
  • One via is illustrated below each of the six islands constituting a row of islands.
  • cobber lanes i.e. cobber deposited during one of the fabrication steps (another electrically conductive material than cobber may be used).
  • the cobber lanes constitute electrically conductive paths such as a first electrically conductive path 24 .
  • the vias may be omitted.
  • a test sample terminal and test island are next to each other so that the electric connection only needs to be established underneath the isolated/etched part of the test sample.
  • the electrically conductive paths extend parallel with the layers and each electrically conductive path interconnects a via for one landing pad with one of the vias contacting the MTJ stack.
  • One of the electrically insulating layers may also be used for electrically connections leading to for example control electronics such as a switch.
  • the switch itself may be placed in a sixth layer, which may be lower than the electrically insulating layer.
  • a landing pad may not necessarily be constituted by three MTJ layers.
  • the landing pad may be a semiconductor material deposited or otherwise created on the first electrically insulating layer as an island which may conduct an electric signal from a probe tip to the via, which contacts the respective landing pad from below.
  • FIG. 2 shows a test sample
  • test sample in FIG. 2 corresponds to the test sample mentioned in connection with FIG. 1 , but where a probe has been placed above the test sample.
  • test sample is shown in a non-exploded view.
  • the vias and electrically conductive paths are illustrated as dotted lines below the top three layers.
  • the probe has six cantilever arms extending parallel to each other. Each cantilever arm ending in a probe tip such as a first probe tip 32 .
  • Each respective probe tip has been brought into contact with the landing areas of each respective landing pad, i.e. the first probe tip 32 contacts the first landing pad 26 with the first via 22 contacting the first landing pad from below.
  • the contact is such that there is an electric contact between the probe tip and the landing pad, i.e. the probe tip may penetrate a possible oxide layer on top of the landing pad such that the electric contact may be established.
  • a probe tip may penetrate the landing pad a small distance so that it not only rests on the surface constituting the landing area.
  • the first electrically conductive path extends from the first via to the MTJ stack 28 , i.e. to a point below the MTJ stack.
  • the vias and electrically conductive paths enable a circuit path to be completed from one probe tip to another such that a current may be injected into the circuit path and go into the MTJ stack and further to a second probe tip.
  • Four of the cantilever arms may be for a four point measurement (four terminal sensing). Two of these are for injecting a current, and the other two are for voltage measurement.
  • the fifth cantilever arm may be for distance measuring so that the distance between a probe tip and landing pad may be controlled during the landing of a probe tip.
  • FIG. 3 a shows a test sample
  • test sample in FIG. 3 a corresponds to the test sample mentioned in connection with FIG. 1 , but where a cross section has been made through the vias which connects to the MTJ stack to be tested.
  • FIG. 3 b an, enlarged view of one of the vias in FIG. 3 a is shown, i.e. of a part of the test sample shown in FIG. 3 a.
  • the magnified view shows the top layer 12 , the middle layer 14 , and the bottom layer 16 of the MTJ stack.
  • the second via 34 extends vertically from the first electrically conducting path 24 to the bottom layer 16 of the MTJ stack 28 .
  • FIG. 4 a shows a test sample
  • test sample in FIG. 4 a corresponds to the test sample mentioned in connection with FIG. 1 , but where a cross section has been made through one of the electrically conductive paths—the cross section is in a plane orthogonal to the cross section of FIG. 3 b.
  • FIG. 4 b an enlarged view of one of the vias in FIG. 4 a is shown, i.e. of a part of the test sample shown in FIG. 4 a.
  • the magnified view shows the top layer 12 , the middle layer 14 , and the bottom layer 16 of the MTJ stack.
  • the second via 34 extends vertically from the first electrically conducting path 24 to the bottom layer 16 of the MTJ stack 28 .
  • the electrically conducting path 24 extends between the first via 22 and the second via 34 .

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

The method may be used for measuring an electric property of a magnetic tunnel junction used in an embedded MRAM memory for example. The method uses a multi point probe with a plurality of probe tips for contacting a designated area of the test sample, which is electrically insulated from the part of the test sample which is to be tested. Electrically connections are placed underneath the magnetic tunnel junction and goes to the designated area.

Description

The present invention relates to measuring at least one electric property of a test sample such as a multilayer stack composed of electrically conductive layers and at least one tunnelling barrier, for example a magnetic tunnel junction (MTJ).
Typically, microscopic multi-point probes are used on for example magnetoresistive random-access memory (MRAM) wafers for current-in-plane tunnelling measurement for determining a number of electric properties of the test sample, i.e. for testing that the wafer is according to specifications.
The electric properties may be the resistance area product, the sheet resistance of a first electrically conductive sheet on top of the tunnelling barrier, the sheet resistance of a second sheet below the tunnelling barrier (bottom sheet), and the magneto tunnelling resistance.
The test sample may contain any number of tunnelling barriers and electrically conductive sheets, deposited on top of each other; in such case, multiple resistance area products may be defined. It is also possible that a sample containing more than one tunnelling barrier is modelled by a single barrier mathematical model.
The typical method of placing the multi-point probe above the wafer, and contacting the top surface of the wafer with the tips of the electrodes of the probe may result in an erroneous measurement if, for example in the case of a single tunnelling barrier model, the sheet resistance of the top sheet is lower than the sheet resistance of the bottom sheet.
It is an object of the present invention to achieve an improved measurement.
The above object and advantages together with numerous other objects and advantages, which will be evident from the description of the present invention, are according to a first aspect of the present invention obtained by:
A method for measuring an electrically property of a multilayer test sample such as a magnetic tunnel junction, said method comprising:
providing said multilayer test sample having a stack including at least a first layer and a second layer, said stack being above an electrically insulating layer,
providing a first test sample terminal above said electrically insulating layer for a first connection with a measurement circuit,
providing a second test sample terminal above said electrically insulating layer for a second connection with said measurement circuit,
said first test sample terminal, said second test sample terminal, and said stack being electrically insulated from each other,
providing a first electrically conductive path embedded in said electrically insulating layer, said first electrically conductive path electrically interconnecting said first test sample terminal and said stack, and
providing a second electrically conductive path embedded in the electrically insulated layer, said second electrically conductive path electrically interconnecting said second test sample terminal and said stack,
said method further comprising:
providing said measuring circuit including a first measuring terminal, and a second measuring terminal,
contacting said first measuring terminal with said first test sample terminal, contacting said second measuring terminal with said second test sample terminal, and
measuring said electric property of said stack by means of said measuring circuit.
The terms electric, electronic, electrically are to be understood are interchangeable.
A third test sample terminal above the electrically insulating layer for a third connection with a measurement circuit may be provided. And the third measuring terminal may be contacted with the third test sample terminal.
A fourth test sample terminal above the electrically insulating layer for a fourth connection with a measurement circuit may be provided. And the fourth measuring terminal may be contacted with the fourth test sample terminal.
Embedded means/features may be provided or embedded in, the test sample for embedded measuring of the electronic property, i.e. by embedded measuring is meant measuring the electronic property by means of features embedded in the test sample during the microfabrication of the test sample.
The embedded means may be constituted by the two terminals, and the electrically conductive paths below the stack and terminals.
The electrically insulated layer below the stack may support the stack. Similarly, the electrically insulated layer may support the test sample terminals.
The first layer may be made of an electrically conductive material, and the second layer may also be made of an electrically conductive material.
Alternatively, one of the two layers (preferably the second layer, which may be below the first layer) may be made of an electric insulator.
Each of the first layer and/or the second layer may be subdivided into multiple layers/sheets.
An electric insulator may also be sandwiched between the first layer and the second layer such that the stack is a three-layer stack—the electric insulator constituting a tunnelling barrier/layer.
The multilayer test sample may be a semiconductor wafer having multiple conductive and tunneling layers.
The multilayer test may for example be a magnetoresistive random-access memory, wherein each memory cell may be constituted by a magnetic tunnel junction—each junction may be constituted by a pillar.
There may be a high contact resistance barrier between the first (conductive) layer, and the second (conductive) layer such as Schottky barrier.
The stack may comprise the electronics for the desired purpose of the dies of the semiconductor wafer i.e. the two layers may be for a memory purpose or for a sensor purpose.
The wafer is to be understood as a substrate for microelectronic devices built in during the microfabrication process of the wafer.
The microelectronics may comprise an electronic component directed towards the desired purpose as well as circuits or components for controlling the electronic component, i.e. a memory cell and a switch for the memory cell for example.
The wafer may be fabricated by etching and/or layer growth, which may be repeated in a number of steps in a usual wafer fabrication method.
The measuring circuit may include a movable probe for moving the first measuring terminal and the second measuring terminal to the test sample such that the contact between the first measuring terminal and the first test sample terminal and also the second measuring terminal and the second test sample terminal may be established.
The first test sample terminal and second test sample terminal may each constitute a landing pad for each of the two measuring terminals, i.e. such that a measuring terminal may be brought into contact (electrically) with a test sample for a measuring terminal to land on.
Each of the first and the second test sample terminals may be manufactured during the manufacturing of the semiconductor wafer by etching each test sample terminal out as an island, i.e. etching around the area of the semiconductor wafer, which is designated the test sample terminal such that a protruding structure remains.
The etching may extend through the three-layer stack (constituting an MTJ stack for example) such that the test sample in itself has the same three layers as the rest of the wafer where there are no etchings.
Alternatively, a test sample terminal may be manufactured such that the material of the terminal is only deposited/grown in the area designated for the test sample terminal.
The test sample terminals may be positioned in the scribe lines of the test sample, i.e. the lines dividing the test sample into the respective dies having the integrated circuits constituting the electronics.
The scribe lines are typically arranged as a rectangular grid for dicing the dies, i.e. with gridlines being orthogonal.
A scribe line may have a width between 20 to 200 microns, such as 75 to 125 microns or such as 100 microns.
The test sample terminals may be made simultaneously as the electronics/integrated circuits of the dies, i.e. the area of the dies and the scribe lines is exposed with the material of the first layer in one step. In a second step, the test sample terminals may be insulated.
Thus, the first layer of a test sample terminal, and the first layer of the stack may be in the same plane.
Several test sample terminals may be placed next to each other, such as four test sample terminals. They may have a pitch (distance between them) matching the pitch of a multipoint probe for example, i.e. the second test sample terminal may be adjacent the first test sample terminal. A third test sample terminal may be placed adjacent to the second test sample terminal, and a fourth test sample terminal may, be placed adjacent to the third test sample terminal. Such four test sample terminals may be placed linearly with respect to each other, i.e. constituting a row of test sample terminals.
The electrically insulated layer supports the upper layers, and it may also be used for embedding electric wiring, i.e. electric interconnections between different parts of the wafer. Several of such metallization layers may be provided for electric interconnections through the wafer.
The electric wiring such as the first electrically conductive path and the second electrically conductive path may be manufactured during manufacturing of the wafer as copper lines deposited on the electrically insulated layer before the paths are embedded by further depositing the material of the electrically insulated layer.
Electric connections between the layers may be made by vertical vias, i.e. vias extending in a direction from one layer to another, which will be in a vertical direction when the wafer is on a horizontal surface. Thus, a first via may interconnect the first electrically conductive path with the first test sample terminal. Such vias may be made of tungsten, copper, copper nitride, tantalum, tantalum nitride, cobalt, ruthenium. Two separate vias or more may be used for establishing the vertical part of the path, which may interconnect a test sample terminal and the stack to be tested—the electrically conductive path may have two vertical parts of the path (below the test sample terminal and below the stack, respectively) and one horizontal part. Both of the vertical parts may be constituted by two or more vias instead of only one via.
The electrically insulating layer may be made of an electrically insulating material such that the electric wiring in the layer defines the circuit paths and where current may flow and the current is confined to the defined paths.
Two electrically conductive paths leading to separate test sample terminals may constitute a circuit together with the MTJ stack, for leading a supply current from a first test sample terminal to the MTJ stack and a return current back to a second test sample terminal.
According to a second aspect of the present invention the above objects and advantages are obtained by:
A multilayer test sample for embedded measuring of an electrically property of said multilayer test sample, said multilayer test sample comprising:
a stack including at least a first layer and a second layer, said stack being above an electrically insulating layer,
a first test sample terminal above said electrically insulating layer for a first connection with a measurement circuit,
a second test sample terminal above said electrically insulating layer for a second connection with a measurement circuit,
said first test sample terminal, said second test sample terminal, and said stack being electrically insulated from each other,
said multilayer test sample further comprising:
a first electrically conductive path embedded in the electrically insulated layer, said first electrically conductive path electrically interconnecting said first test sample terminal and said stack, and
a second electrically conductive path embedded in the electrically insulated electrically layer, said second electrically conductive path interconnecting said second test sample terminal and said stack such that said first electrically conductive path and said second electrically conductive path together with said stack forming a circuit between said first test sample terminal and said second test sample terminal for measuring said electrically property.
The invention will now be explained in more detail below by means of examples with reference to the accompanying drawings, in which
FIG. 1 shows an exploded view of a test sample.
FIG. 2 shows a test sample.
FIG. 3a shows a test sample.
FIG. 3b shows an enlarged view of part of FIG. 3 a.
FIG. 4a shows a test sample.
FIG. 4b shows an enlarged view of part of FIG. 4 a.
The invention may, however, be embodied in different forms than depicted below, and should not be construed as limited to any examples set forth herein. Rather, any examples are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Like reference numerals refer to like elements throughout. Like elements will thus not be described in detail with respect to the description of each figure.
FIG. 1 shows an exploded view of a test sample,
The test sample 10 has five layers wherein the top three layers constitute a magnetic tunnel junction (MTJ), i.e. a MTJ stack.
The test sample may constitute a semiconductor wafer comprising at least two electrically conductive layers and a tunnelling electrically insulating layer sandwiched in the middle, for example an MTJ.
The top layer 12 of the MTJ stack may or may not contain a ferromagnetic material, but it is electrically conductive.
The direction of the magnetization of the top layer may be changed.
A middle layer 14 is sandwiched between the top layer and a bottom layer 16 of the MTJ stack.
The middle layer is a thin electrically insulator—the thickness of which is not so large that electrons may not tunnel through it, i.e. the middle layer is a tunnelling barrier layer.
The bottom layer 16 may also or may not contain ferromagnetic materials, but it is electrically conductive.
Alternatively, the top layer may have a permanent magnetization, and the bottom layer may have a variable direction of the magnetic moments. Both layers may also have a variable direction of the magnetic moments.
The resistance of the stack when a voltage potential is applied across the stack could depend on if the magnetization of the top and bottom layer are parallel or antiparallel, i.e. if they are parallel, the tunnelling barrier is lower than if the magnetizations are antiparallel.
The top layer is illustrated with a planar top surface, and the layers are in general illustrated as being parallel to each other.
The stack may also have more than two conductive layers and one barrier with several electrical properties, which are to be measured.
Alternatively, the layers of the test sample may have another function than as for a MRAM cell. For example, a stack having only two layers, the purpose of which being a sensor.
The three layers of the stack are shown as seven islands in FIG. 1, i.e. six smaller islands next to each other on a row and one larger island by itself (such as a test island constituting an MTJ stack 28 for MRAM or a sensor purpose). This is a result of etchings in the stack layers such that these islands become electrically insulated from each other, i.e. the islands are not electrically connected with each other.
The removed parts of the layers could also be constituted by oxide material or another material constituting an electrical insulator, i.e. such that the space between the islands themselves, and the space between an island and the MTJ stack is filled with an electrical insulator material.
The six smaller islands constitute six test sample terminals, which may have the purpose of landing pads such as a first landing pad 26 having a first landing area on top of the landing pad, i.e. the exposed surface 30 which is not covered by another layer on top of it—except for possibly a thin oxide layer.
A test sample terminal may have any in-plane shape. FIG. 1 shows rectangular shapes/areas but the shape may be round, oval, elliptic, polygonal or a random shape.
Each landing area of each landing pad is for landing a probe tip, i.e. contacting a probe tip with the landing area such that an electric signal may be injected into the landing pad during a measurement routine, or alternatively, an electric measurement signal may be picked up. In this way, terminals are provided on the test sample for a probe, and for doing a probe measurement.
Instead of using a probe, the test sample may be inserted into a measuring device wherein the measuring terminals have fixed positions aligned with the position of the test sample terminals when the test sample is placed correctly in the measuring device.
The larger island 28 may the identical as of the in the MRAM cell needed to be tested, specifically one or more electrical properties of the MTJ stack.
Below the MTJ stack is a fourth layer constituting a first electrically insulating layer 18, i.e. no current is intended to flow freely in that layer without control of the current path.
Below the fourth electrically insulating layer is the fifth layer constituting a second electrically insulating layer 20.
The first electrically insulating layer, and the second electrically insulating layer may be made as one electrically insulating layer.
The first electrically insulating layer has vias such as a first via 22 extending vertically throughout the thickness of the layer.
One via is illustrated below each of the six islands constituting a row of islands.
Six vias, such as a second via 34, are also shown under the larger island, which all go into contact with the bottom surface of the bottom layer of the MTJ stack.
In the second electrically insulating layer are six cobber lanes, i.e. cobber deposited during one of the fabrication steps (another electrically conductive material than cobber may be used).
The cobber lanes constitute electrically conductive paths such as a first electrically conductive path 24.
For the electric connection between a terminal and the particular part of the test sample, which needs to be tested, it is contemplated that the vias may be omitted. For example if a test sample terminal and test island are next to each other so that the electric connection only needs to be established underneath the isolated/etched part of the test sample.
The electrically conductive paths extend parallel with the layers and each electrically conductive path interconnects a via for one landing pad with one of the vias contacting the MTJ stack.
One of the electrically insulating layers may also be used for electrically connections leading to for example control electronics such as a switch. The switch itself may be placed in a sixth layer, which may be lower than the electrically insulating layer.
A landing pad may not necessarily be constituted by three MTJ layers. Alternatively, the landing pad may be a semiconductor material deposited or otherwise created on the first electrically insulating layer as an island which may conduct an electric signal from a probe tip to the via, which contacts the respective landing pad from below.
FIG. 2 shows a test sample.
The test sample in FIG. 2 corresponds to the test sample mentioned in connection with FIG. 1, but where a probe has been placed above the test sample.
The test sample is shown in a non-exploded view. The vias and electrically conductive paths are illustrated as dotted lines below the top three layers.
The probe has six cantilever arms extending parallel to each other. Each cantilever arm ending in a probe tip such as a first probe tip 32.
Each respective probe tip has been brought into contact with the landing areas of each respective landing pad, i.e. the first probe tip 32 contacts the first landing pad 26 with the first via 22 contacting the first landing pad from below.
For the measurement of the electric property, the contact is such that there is an electric contact between the probe tip and the landing pad, i.e. the probe tip may penetrate a possible oxide layer on top of the landing pad such that the electric contact may be established.
A probe tip may penetrate the landing pad a small distance so that it not only rests on the surface constituting the landing area.
The first electrically conductive path extends from the first via to the MTJ stack 28, i.e. to a point below the MTJ stack.
The vias and electrically conductive paths enable a circuit path to be completed from one probe tip to another such that a current may be injected into the circuit path and go into the MTJ stack and further to a second probe tip.
Four of the cantilever arms may be for a four point measurement (four terminal sensing). Two of these are for injecting a current, and the other two are for voltage measurement.
The fifth cantilever arm may be for distance measuring so that the distance between a probe tip and landing pad may be controlled during the landing of a probe tip.
FIG. 3a shows a test sample.
The test sample in FIG. 3a corresponds to the test sample mentioned in connection with FIG. 1, but where a cross section has been made through the vias which connects to the MTJ stack to be tested.
In FIG. 3b , an, enlarged view of one of the vias in FIG. 3a is shown, i.e. of a part of the test sample shown in FIG. 3 a.
The magnified view shows the top layer 12, the middle layer 14, and the bottom layer 16 of the MTJ stack. The second via 34 extends vertically from the first electrically conducting path 24 to the bottom layer 16 of the MTJ stack 28.
FIG. 4a shows a test sample.
The test sample in FIG. 4a corresponds to the test sample mentioned in connection with FIG. 1, but where a cross section has been made through one of the electrically conductive paths—the cross section is in a plane orthogonal to the cross section of FIG. 3 b.
In FIG. 4b , an enlarged view of one of the vias in FIG. 4a is shown, i.e. of a part of the test sample shown in FIG. 4 a.
The magnified view shows the top layer 12, the middle layer 14, and the bottom layer 16 of the MTJ stack.
The second via 34 extends vertically from the first electrically conducting path 24 to the bottom layer 16 of the MTJ stack 28.
The electrically conducting path 24 extends between the first via 22 and the second via 34.
Below is a list of reference signs used in the detailed description of the invention and in the drawings referred to in the detailed description of the invention
  • 10 Test sample
  • 12 Top layer
  • 14 Middle layer
  • 16 Bottom layer
  • 18 First electrically insulating layer
  • 20 Second electrically insulating layer
  • 22 First via
  • 24 First electrically conductive path
  • 26 First landing pad
  • 28 MTJ stack
  • 30 First landing area
  • 32 Probe tip
  • 34 Second via

Claims (14)

The invention claimed is:
1. A method for measuring an electrical property of a multilayer test sample such as a magnetic tunnel junction, said method comprising:
providing said multilayer test sample having a stack including at least a first layer and a second layer, said stack being above an electrically insulating layer,
providing a first test sample terminal above said electrically insulating layer for a first connection with a measurement circuit,
providing a second test sample terminal above said electrically insulating layer for a second connection with said measurement circuit,
said first test sample terminal, said second test sample terminal, and said stack being electrically insulated from each other,
providing a first electrically conductive path embedded in said electrically insulating layer, said first electrically conductive path electrically interconnecting said first test sample terminal and said stack, and
providing a second electrically conductive path embedded in the electrically insulated layer, said second electrically conductive path electrically interconnecting said second test sample terminal and said stack,
said method further comprising:
providing said measuring circuit including a first measuring terminal and a second measuring terminal,
contacting said first measuring terminal with said first test sample terminal,
contacting said second measuring terminal with said second test sample terminal, and
measuring said electric property of said stack by means of said measuring circuit.
2. The method according to claim 1, said multilayer test sample being a semiconductor wafer for magnetoresistive random-access memory.
3. The method according to claim 1, said stack constituting a magnetic tunnel junction.
4. The method according to claim 1, said first layer being a ferromagnetic sheet.
5. The method according to claim 1, said second layer being a ferromagnetic sheet.
6. The method according to claim 1, said stack including a middle layer sandwiched between said first layer and said second layer.
7. The method according to claim 6, said middle layer being an electric insulator for tunnelling electrons between said first layer and said second layer.
8. The method according to claim 1, a first island of said test sample having at least three layers.
9. The method according to claim 8, a second island of said test sample having at least three layers.
10. The method according to claim 1, said first electrically conductive path extending planarly in said electrically insulating layer.
11. The method according to claim 1, comprising providing a first via between said first test sample and said first electrically conductive path.
12. The method according to claim 11, comprising providing a second via between said stack and said first electrically conductive path.
13. The method according to claim 1, comprising providing a test probe including a first probe tip of said first measuring terminal and a second probe tip of said second measuring terminal,
contacting said first probe tip with said first test sample terminal, and
contacting said second probe tip with said second test sample terminal.
14. A multilayer test sample for embedded measuring of an electrical property of said multilayer test sample, said multilayer test sample comprising:
a stack including at least a first layer and a second layer, said stack being above an electrically insulating layer,
a first test sample terminal above said electrically insulating layer for a first connection with a measurement circuit,
a second test sample terminal above said electrically insulating layer for a second connection with said measurement circuit,
said first test sample terminal, said second test sample terminal, and said stack being electrically insulated from each other,
said multilayer test sample further comprising:
a first electrically conductive path embedded in the electrically insulated layer, said first electrically conductive path electrically interconnecting said first test sample terminal and said stack, and
a second electrically conductive path embedded in the electrically insulated layer, said second electrically conductive path interconnecting said second test sample terminal and said stack such that said first electrically conductive path and said second electrically conductive path together with said stack form a circuit between said first test sample terminal and said second test sample terminal for measuring said electrically property.
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11946890B2 (en) * 2021-05-24 2024-04-02 Kla Corporation Method for measuring high resistivity test samples using voltages or resistances of spacings between contact probes
CN113644003B (en) * 2021-08-10 2024-06-11 青岛海存微电子有限公司 Patterned magnetic tunnel crystallization circle magnetic resistance test structure and use method thereof
US12105136B2 (en) * 2021-09-09 2024-10-01 Kla Corporation Method for determining material parameters of a multilayer test sample
US12044727B2 (en) 2022-09-19 2024-07-23 Orbotech Ltd. Probes for electrical testing in defect detection systems
CN118284309A (en) * 2022-12-29 2024-07-02 浙江驰拓科技有限公司 Magnetic tunnel junction test structure, preparation method and test method of magnetic tunnel junction

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020097063A1 (en) * 1999-11-16 2002-07-25 Kline Jerry D. Wafer level interposer
US20050172702A1 (en) * 2004-02-05 2005-08-11 Gitis Norm V. Method and apparatus for determining characteristics of thin films and coatings on substrates
US20050186793A1 (en) * 2004-01-26 2005-08-25 Seiichi Omoto Manufacturing method of semiconductor device
US20080303140A1 (en) * 2007-06-07 2008-12-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20140252356A1 (en) * 2013-03-08 2014-09-11 Avalanche Technology Inc. Devices and methods for measurement of magnetic characteristics of mram wafers using magnetoresistive test strips
US20160320430A1 (en) 2015-04-29 2016-11-03 Kla-Tencor Corporation Multiple Pin Probes with Support for Performing Parallel Measurements
US20170023617A1 (en) 2015-06-10 2017-01-26 Translarity, Inc. Shaping of contact structures for semiconductor test, and associated systems and methods
US20180083607A1 (en) * 2016-09-16 2018-03-22 Renesas Electronics Corporation Semiconductor device
WO2018162343A2 (en) 2017-03-07 2018-09-13 Capres A/S A probe for testing an electrical property of a test sample
US20190013140A1 (en) * 2017-07-04 2019-01-10 Infineon Technologies Austria Ag Winding Module, Hybrid Transformer, Module and Circuit for DC-DC Power Conversion
US20190066820A1 (en) 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for testing mram device and test apparatus thereof
US20190064219A1 (en) * 2017-08-22 2019-02-28 Samsung Electronics Co., Ltd. Probe card, test apparatus including the probe card, and related methods of manufacturing
US20190310295A1 (en) * 2017-01-09 2019-10-10 Capres A/S A position correction method and a system for position correction in relation to four probe resistance measurements

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040702A (en) * 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
EP0990918B1 (en) * 1998-09-28 2009-01-21 NEC Electronics Corporation Device and method for nondestructive inspection on semiconductor device
US6250933B1 (en) 2000-01-20 2001-06-26 Advantest Corp. Contact structure and production method thereof
AU2003206667A1 (en) * 2002-01-07 2003-07-24 Capres A/S Electrical feedback detection system for multi-point probes
US6927569B2 (en) * 2002-09-16 2005-08-09 International Business Machines Corporation Techniques for electrically characterizing tunnel junction film stacks with little or no processing
US7211446B2 (en) * 2004-06-11 2007-05-01 International Business Machines Corporation Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory
EP2569646A4 (en) 2005-03-28 2014-01-22 Texas Instruments Inc Resilient probes for electrical testing
DE102006050833B4 (en) * 2006-10-27 2011-04-07 Infineon Technologies Ag Magnetoresistive sensor element and a method for its production, as well as its use and a sensor arrangement
JP5165404B2 (en) * 2007-06-06 2013-03-21 ルネサスエレクトロニクス株式会社 Semiconductor device, semiconductor device manufacturing method and test method
TW201003880A (en) * 2008-05-30 2010-01-16 Advanced Micro Devices Inc Semiconductor device comprising a chip internal electrical test structure allowing electrical measurements during the fabrication process
EP2141503A1 (en) * 2008-06-30 2010-01-06 Capres A/S A multi-point probe for testing electrical properties and a method of producing a multi-point probe
US8021712B2 (en) * 2009-03-18 2011-09-20 Tdk Corporation Wafer and manufacturing method of electronic component
US8750031B2 (en) * 2011-12-16 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures, methods of manufacturing thereof, test methods, and MRAM arrays
US8806284B2 (en) * 2012-05-02 2014-08-12 Avalanche Technology Inc. Method for bit-error rate testing of resistance-based RAM cells using a reflected signal
CN103344791B (en) * 2013-06-26 2016-07-06 中国科学院深圳先进技术研究院 A kind of probe card tested substrate and adopt this test substrate manufacture
DE102015113046A1 (en) * 2015-08-07 2017-02-09 Xcerra Corp. Positioning device for a parallel tester for testing printed circuit boards and parallel testers for PCB testing
KR102695418B1 (en) * 2017-02-10 2024-08-19 삼성디스플레이 주식회사 Chip on film package, display panel, and display device
CN110383092B (en) * 2017-03-03 2022-04-01 雅赫测试系统公司 Electronic tester
CN108511358B (en) * 2018-03-29 2019-03-29 长江存储科技有限责任公司 3D NAND detection structure and forming method thereof

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020097063A1 (en) * 1999-11-16 2002-07-25 Kline Jerry D. Wafer level interposer
US20050186793A1 (en) * 2004-01-26 2005-08-25 Seiichi Omoto Manufacturing method of semiconductor device
US20050172702A1 (en) * 2004-02-05 2005-08-11 Gitis Norm V. Method and apparatus for determining characteristics of thin films and coatings on substrates
US20080303140A1 (en) * 2007-06-07 2008-12-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20140252356A1 (en) * 2013-03-08 2014-09-11 Avalanche Technology Inc. Devices and methods for measurement of magnetic characteristics of mram wafers using magnetoresistive test strips
US20160320430A1 (en) 2015-04-29 2016-11-03 Kla-Tencor Corporation Multiple Pin Probes with Support for Performing Parallel Measurements
US20170023617A1 (en) 2015-06-10 2017-01-26 Translarity, Inc. Shaping of contact structures for semiconductor test, and associated systems and methods
US20180083607A1 (en) * 2016-09-16 2018-03-22 Renesas Electronics Corporation Semiconductor device
US20190310295A1 (en) * 2017-01-09 2019-10-10 Capres A/S A position correction method and a system for position correction in relation to four probe resistance measurements
WO2018162343A2 (en) 2017-03-07 2018-09-13 Capres A/S A probe for testing an electrical property of a test sample
US20190013140A1 (en) * 2017-07-04 2019-01-10 Infineon Technologies Austria Ag Winding Module, Hybrid Transformer, Module and Circuit for DC-DC Power Conversion
US20190064219A1 (en) * 2017-08-22 2019-02-28 Samsung Electronics Co., Ltd. Probe card, test apparatus including the probe card, and related methods of manufacturing
US20190066820A1 (en) 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for testing mram device and test apparatus thereof

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
EPO, Search Report for EP Application No. 19167346.6, dated Oct. 4, 2019.
Kataoka et al., "Electroplating Ni micro-cantilevers for low contact-force IC probing," Sensors and Actuators A: Physical, 2003, vol. 103, pp. 116-121.
WIPO, ISR for PCT/US2020/023232, dated Jul. 10, 2020.

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