CN107147394B - High-voltage signal sampling circuit based on double sampling technology - Google Patents
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Abstract
A high-voltage signal sampling circuit based on a double sampling technology. It comprises a third sampling capacitor CS3A fourth sampling capacitor CS4Fully differential spanLead amplifier S and third integrating capacitor CI3And a fourth integrating capacitor CI4A first switch c1, a second switch c2, a third switch c3, a fourth switch c4, a fifth switch c5, a sixth switch c6, a seventh switch c7 and an eighth switch c 8. The high-voltage signal sampling circuit based on the double sampling technology has the advantages that: the circuit utilizes a double-sampling technology, can effectively solve the problem that the voltage of the high-voltage lithium battery cannot be acquired due to no high-voltage capacitor in a low-voltage CMOS process, namely, the low-voltage CMOS process can be utilized to replace a high-voltage CMOS process, thereby reducing the cost.
Description
Technical Field
The invention belongs to the technical field of high-voltage sampling, and particularly relates to a high-voltage signal sampling circuit based on a double-sampling technology.
Background
With the continuous improvement of living standard of people, people have higher pursuit to the requirements of living environment. Therefore, in order to reduce the exhaust emission of automobiles and reduce environmental pollution, new vehicles such as electric bicycles, electric automobiles and scooters are increasingly paid attention to and favored by people. Among them, the battery is a core part of these products, and its safety and service life become important considerations in product design. Therefore, in order to improve the service life of the battery and ensure the safety of the use of the battery, a circuit chip for monitoring, managing and controlling the charge and discharge of the battery is proposed and effectively used in various electronic products. Fig. 1 is a simple block diagram of a multi-cell cascade battery monitor, as shown in fig. 1, the monitor firstly selects a battery to be monitored through a switch Si, then converts a detected analog signal into a digital signal through an analog-to-digital converter and transmits the digital signal to a detection circuit, and the detection circuit measures the voltage condition of the selected battery, so as to control the charging and discharging of the battery. Wherein only one of the switches S1, S2 to Sn is allowed to be opened at a time, and the remaining switches are all in a closed state, i.e. only one battery is measured at a time. The cell voltage at the top of the battery pack is high due to the cascading of multiple cells.
Fig. 2 is a high voltage signal sampling circuit in a typical analog-to-digital converter, which is used for sampling a battery voltage, and comprises: a first sampling capacitor CS1A second sampling capacitor CS2A fully differential transconductance amplifier S and a first integrating capacitor CI1A second integrating capacitor CI2A first switch c1, a second switch c2, a third switch c3, a fourth switch c4, a fifth switch c5, a sixth switch c6, a seventh switch c7, and an eighth switch c8, wherein:
one end of the first switch C1 is the positive input end of the sampling circuit, a signal vinp is input, and the other end of the first switch C1 passes through the first sampling capacitor C in sequenceS1And a seventh switch C7 connected with the non-inverting input terminal of the fully differential transconductance amplifier S, one end of a second switch C2 is the negative input terminal of the sampling circuit, a signal vinn is input, and the other end of the second switch C2 sequentially passes through a second sampling capacitor CS2And an eighth switch C8 connected with the inverting input terminal of the fully differential transconductance amplifier S, one end of a third switch C3 connected with the second sampling capacitor CS2The other end of the eighth switch C8 is connected with the reference voltage vcm, and one end of the fourth switch C4 is connected with the first sampling capacitor CS1And the connection point of the seventh switch C7, the other end of the seventh switch is connected with the reference voltage vcm, and one end of the fifth switch C5 is connected with the first switch C1 and the first sampling capacitor CS1Is connected with the other end of the reference voltage vcm, and one end of a sixth switch C6 is connected with a second switch C2 and a second sampling capacitor CS2Is connected with the other end of the reference voltage vcm, a first integrating capacitor CI1One end of the positive-negative voltage transformer is connected with the non-inverting input end of the fully differential transconductance amplifier S, and the other end of the negative-positive voltage transformer is connected with the negative output end of the fully differential transconductance amplifier S; second integrating capacitor CI2One end of which is connected to the inverting input terminal of the fully differential transconductance amplifier S and the other end of which is connected to the positive output terminal of the fully differential transconductance amplifier S.
The fully differential transconductance amplifier S is a double-end input and a double-end outputIn the fully differential transconductance amplifier, the amplifier output difference divided by the input difference is the amplifier gain, i.e. Voutp-Voutn＝A(Vinp-Vinn) And A is the amplifier gain.
The first sampling capacitor CS1And a second sampling capacitor CS2Is equal and capacity is equal to CS(ii) a The first integrating capacitor CI1And a second integrating capacitor CI2Is equal and capacity is equal to CI。
The positive input end of the sampling circuit is connected with the positive poles of the batteries v1-vn through one group of contacts of the gating switches S1-Sn, and the negative input end of the sampling circuit is connected with the negative poles of the batteries v1-vn through the other group of contacts of the gating switches S1-Sn.
The first to eighth switches c1-c8 are turned on and off under the control of a first clock signal CLK1 and a second clock signal CLK2, the second clock signal CLK2 is at a low level when the first clock signal CLK1 is at a high level, and the first switch c1, the second switch c2, the third switch c3 and the fourth switch c4 are turned on under the action of a high level of the first clock signal CLK 1; under the action of the low level of the second clock signal CLK2, the fifth switch C5, the sixth switch C6, the seventh switch C7 and the eighth switch C8 are closed, and the upper end voltage vinp of the selected battery is charged to the first sampling capacitor C at the upper part of the circuitS1First sampling capacitor C at upper part, i.e. upper part of circuitS1The voltage across the terminals is the voltage difference between the anode voltage of the cell and the reference voltage vcm (vcm is the lower voltage). At the same time, the lower end voltage of the selected battery is charged to a second sampling capacitor C at the lower part of the circuitS2Upper, i.e. lower, second sampling capacitor CS2The voltage across the terminals is the voltage difference between the cathode voltage of the cell and the voltage vcm. When the second clock signal CLK2 is high, the first clock signal CLK1 is low, the fifth to eighth switches C5-C8 are open by the second clock signal CLK2, the first to fourth switches C1-C4 are closed by the first clock signal CLK1, and the first sampling capacitor C is connected to the first sampling capacitor C1S1And a second sampling capacitor CS2The voltages at both ends are reference voltage vcm. At the moment, under the action of the amplifier, the capacitor and the switch, the sampling capacitor collectsThe charge is discharged, the charge is transferred to the integrating capacitor, and the voltage vcm1 is vcm. As can be seen, the upper portion of the circuit, the first sampling capacitor C, goes from the first clock signal CLK1 to the second clock signal CLK2S1The charge variation amount of (a) is [ (vip-vcm) - (vcm-vcm)]*CS＝(vip-vcm)*CSSecond sampling capacitor C at lower part of circuitS2The charge variation amount of (a) is [ (vin-vcm) - (vcm-vcm)]*CS＝(vin-vcm)*CSThus, the voltage difference across the selected cell is [ (vip-vcm) × CS–(vin-vcm)*CS]/CS＝vip-vin。
For example: the topmost battery, i.e., the first battery, is gated on, the switch S1 is opened, the voltage difference between the top voltage of the battery and the ground is vinp-v 1+ v2+ … + vn, and the voltage difference between the bottom voltage of the battery and the ground is vinn-v 2+ … + vn, where v1 is the voltage across the battery, and so on, and vn is the voltage across the nth battery, i.e., the voltage across the bottommost battery. When the first clock signal CLK1 is high, the anode voltage of the topmost first battery is charged to the first sampling capacitor CS1Charging the cathode voltage of the first battery to the second sampling capacitor CS2(ii) a When the second clock signal CLK2 is at high level, the sampling capacitor discharges the collected charges, and the voltage difference between the first battery and the second battery is [ (vinp-vcm). multidot.C ] from the first clock signal CLK1 to the second clock signal CLK2S–(vinn-vcm)*CS]/CSVinp-vinn-v 1. It can be seen that when the switch is turned on at S1 (the first battery is selected), due to the cascade connection of n batteries, the charging voltages (vinp-vcm) and (vinn-vcm) on the two sampling capacitors are both relatively high, and therefore, in the circuit, both sampling capacitors need to be implemented by "high-voltage capacitors", however, some processes do not provide a "high-voltage capacitor" model, and the process for providing "high-voltage capacitors" is usually relatively expensive.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a high voltage signal sampling circuit based on a double sampling technique.
In order to achieve the above object, the present invention provides a high voltage signal sampling circuit based on double sampling technique, comprising: third sampling capacitor CS3A fourth sampling capacitor CS4A fully differential transconductance amplifier S and a third integrating capacitor CI3And a fourth integrating capacitor CI4A first switch c1, a second switch c2, a third switch c3, a fourth switch c4, a fifth switch c5, a sixth switch c6, a seventh switch c7, and an eighth switch c8, wherein:
one end of the first switch C1 is the positive input end of the sampling circuit, a signal vinp is input, and the other end of the first switch C1 passes through the third sampling capacitor C in sequenceS3And a seventh switch C7 is connected with the non-inverting input end of the fully differential transconductance amplifier S, one end of a second switch C2 is the negative input end of the sampling circuit, a signal vinn is input, and the other end of the second switch C2 sequentially passes through a fourth sampling capacitor CS4And an eighth switch C8 connected with the inverting input terminal of the fully differential transconductance amplifier S, one end of a third switch C3 connected with the fourth sampling capacitor CS4The other end of the eighth switch C8 is connected with the reference voltage vinp, and one end of the fourth switch C4 is connected with the third sampling capacitor CS3And a connection point of a seventh switch C7, the other end of the seventh switch is connected with a reference voltage vinn, and one end of a fifth switch C5 is connected with the first switch C1 and the third sampling capacitor CS3Is connected with the other end of the reference voltage vcm, and one end of a sixth switch C6 is connected with a second switch C2 and a fourth sampling capacitor CS4Is connected with the other end of the reference voltage vcm, and a third integrating capacitor CI3One end of the positive-negative voltage transformer is connected with the non-inverting input end of the fully differential transconductance amplifier S, and the other end of the negative-positive voltage transformer is connected with the negative output end of the fully differential transconductance amplifier S; fourth integrating capacitor CI4One end of which is connected to the inverting input terminal of the fully differential transconductance amplifier S and the other end of which is connected to the positive output terminal of the fully differential transconductance amplifier S.
The high-voltage signal sampling circuit based on the double sampling technology has the advantages that: the circuit utilizes a double-sampling technology, can effectively solve the problem that the voltage of the high-voltage lithium battery cannot be acquired due to no high-voltage capacitor in a low-voltage CMOS process, namely, the low-voltage CMOS process can be utilized to replace a high-voltage CMOS process, thereby reducing the cost.
Drawings
FIG. 1 is a simplified block diagram of a multiple cascaded battery pack monitor;
FIG. 2 is a schematic diagram of a high voltage signal sampling circuit in a typical analog-to-digital converter;
fig. 3 is a schematic diagram of a high-voltage signal sampling circuit based on a double sampling technique according to the present invention.
Detailed Description
The high-voltage signal sampling circuit based on the double sampling technique provided by the invention is described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 3, the high voltage signal sampling circuit based on the double sampling technique provided by the present invention includes: third sampling capacitor CS3A fourth sampling capacitor CS4A fully differential transconductance amplifier S and a third integrating capacitor CI3And a fourth integrating capacitor CI4A first switch c1, a second switch c2, a third switch c3, a fourth switch c4, a fifth switch c5, a sixth switch c6, a seventh switch c7, and an eighth switch c8, wherein:
one end of the first switch C1 is the positive input end of the sampling circuit, a signal vinp is input, and the other end of the first switch C1 passes through the third sampling capacitor C in sequenceS3And a seventh switch C7 is connected with the non-inverting input end of the fully differential transconductance amplifier S, one end of a second switch C2 is the negative input end of the sampling circuit, a signal vinn is input, and the other end of the second switch C2 sequentially passes through a fourth sampling capacitor CS4And an eighth switch C8 connected with the inverting input terminal of the fully differential transconductance amplifier S, one end of a third switch C3 connected with the fourth sampling capacitor CS4The other end of the eighth switch C8 is connected with the reference voltage vinp, and one end of the fourth switch C4 is connected with the third sampling capacitor CS3And a connection point of a seventh switch C7, the other end of the seventh switch is connected with a reference voltage vinn, and one end of a fifth switch C5 is connected with the first switch C1 and the third sampling capacitor CS3Is connected with the other end of the reference voltage vcm, and one end of a sixth switch C6 is connected with a second switch C2 and a fourth sampling capacitor CS4Is connected with the other end of the reference voltage vcm, and a third integrating capacitor CI3One end of the positive-negative voltage transformer is connected with the non-inverting input end of the fully differential transconductance amplifier S, and the other end of the negative-positive voltage transformer is connected with the negative output end of the fully differential transconductance amplifier S; fourth integrating capacitor CI4One end of and allThe inverting input end of the differential transconductance amplifier S is connected, and the other end of the differential transconductance amplifier S is connected with the positive output end of the fully differential transconductance amplifier S.
The high-voltage signal sampling circuit based on the double sampling technology provided by the invention is a first sampling capacitor C in the high-voltage signal sampling circuit in the typical analog-to-digital converter shown in figure 2S1Using a third sampling capacitor CS3Instead of, a second sampling capacitor CS2Using a fourth sampling capacitor CS4Instead of, the first integrating capacitor CI1Using a third integrating capacitor CI3To agent, second integrating capacitor CI2Using a fourth integrating capacitor CI4Instead, the reference voltage vcm connected to the fourth switch c4 is changed to be connected to the input signal vinn, and the reference voltage vcm connected to the third switch c3 is changed to be connected to the input signal vinp.
At this time, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the first to fourth switches C1-C4 are turned on by the first clock signal CLK1, the fifth to eighth switches C5-C8 are turned off by the second clock signal CLK2, and the third sampling capacitor C at which the upper anode voltage and the lower cathode voltage of the selected battery are charged to the upper portion of the circuit is chargedS3Third sampling capacitor C at upper part, i.e. upper part of circuitS3The voltage across the terminals is the voltage difference between the anode of the cell and the cathode of the cell. At the same time, the lower cathode voltage and the upper anode voltage of the selected battery are charged to a fourth sampling capacitor C at the lower part of the circuitS4Fourth sampling capacitor C at upper part, i.e. lower part of circuitS4The voltage across the terminals is the voltage difference between the cathode voltage of the cell and the anode of the cell. When the first clock signal CLK1 is low and the second clock signal CLK2 is high, the switches fifth through eighth c5-c8 are turned on by the second clock signal CLK2 and the switches first through fourth c1-c4 are turned off by the first clock signal CLK 1. Under the action of the amplifier, the capacitor, the switch and the input common-mode voltage control circuit, the sampling capacitor discharges the collected charges and transmits the charges to the third integrating capacitor CI3And a fourth integrating capacitor CI4The voltage vcm1 can be obtained by circuit control. As can be seen, the third clock signal from the upper part of the circuit from the first clock signal CLK1 to the second clock signal CLK2Sampling capacitor CI3The charge variation amount of (a) is [ (vinp-vin) - (vcm-vcm)]*CS/2＝(vinp-vinn)*CS/2, fourth sampling capacitor C at the lower part of the circuitS4The amount of change in charge of (d) is [ (vinn-vinp) - (vcm-vcm)]*CS/2＝(vin-vip)*C S2, the voltage difference across the selected cell is therefore [ (vinp-vinn) × CS/2–(vinn-vinp)*CS/2]/CSAnd/2 is vinp-vinn. It can be seen that when the first clock signal CLK1 is asserted, the voltage difference (vip-vin) across the sampling capacitor is a low voltage, so that the "low voltage capacitor" can be utilized to sample the high voltage signal.
Claims (1)
1. The utility model provides a high-pressure signal sampling circuit based on two sampling techniques which characterized in that: the high-voltage signal sampling circuit based on the double sampling technology comprises: third sampling capacitor CS3A fourth sampling capacitor CS4A fully differential transconductance amplifier S and a third integrating capacitor CI3And a fourth integrating capacitor CI4A first switch c1, a second switch c2, a third switch c3, a fourth switch c4, a fifth switch c5, a sixth switch c6, a seventh switch c7, and an eighth switch c8, wherein:
one end of the first switch C1 is the positive input end of the sampling circuit, a signal vinp is input, and the other end of the first switch C1 passes through the third sampling capacitor C in sequenceS3And a seventh switch C7 is connected with the non-inverting input end of the fully differential transconductance amplifier S, one end of a second switch C2 is the negative input end of the sampling circuit, a signal vinn is input, and the other end of the second switch C2 sequentially passes through a fourth sampling capacitor CS4And an eighth switch C8 connected with the inverting input terminal of the fully differential transconductance amplifier S, one end of a third switch C3 connected with the fourth sampling capacitor CS4The other end of the eighth switch C8 is connected with the reference voltage vinp, and one end of the fourth switch C4 is connected with the third sampling capacitor CS3And a connection point of a seventh switch C7, the other end of the seventh switch is connected with a reference voltage vinn, and one end of a fifth switch C5 is connected with the first switch C1 and the third sampling capacitor CS3Is connected with the other end of the reference voltage vcm, and one end of a sixth switch C6 is connected with a second switch C2 and a fourth sampling capacitor CS4Is connected to the other end of the reference voltagevcm, third integrating capacitance CI3One end of the positive-negative voltage transformer is connected with the non-inverting input end of the fully differential transconductance amplifier S, and the other end of the negative-positive voltage transformer is connected with the negative output end of the fully differential transconductance amplifier S; fourth integrating capacitor CI4One end of the second half-bridge is connected with the inverting input end of the fully differential transconductance amplifier S, and the other end of the second half-bridge is connected with the positive output end of the fully differential transconductance amplifier S;
when the first clock signal CLK1 is high and the second clock signal CLK2 is low, the first to fourth switches C1-C4 are turned on by the first clock signal CLK1, the fifth to eighth switches C5-C8 are turned off by the second clock signal CLK2, and the upper anode voltage and the lower cathode voltage of the selected battery are charged to the third sampling capacitor C of the upper part of the circuitS3Third sampling capacitor C at upper part, i.e. upper part of circuitS3The voltage at the two ends is the voltage difference between the anode of the battery and the cathode of the battery; at the same time, the lower cathode voltage and the upper anode voltage of the selected battery are charged to a fourth sampling capacitor C at the lower part of the circuitS4Fourth sampling capacitor C at upper part, i.e. lower part of circuitS4The voltage at the two ends is the voltage difference between the cathode voltage of the battery and the anode of the battery; when the first clock signal CLK1 is at a low level and the second clock signal CLK2 is at a high level, the fifth to eighth switches c5-c8 are turned on by the second clock signal CLK2, and the first to fourth switches c1-c4 are turned off by the first clock signal CLK 1; under the action of the amplifier, the capacitor, the switch and the input common-mode voltage control circuit, the sampling capacitor discharges the collected charges and transmits the charges to the third integrating capacitor CI3And a fourth integrating capacitor CI4If the voltage vcm1 can be obtained through circuit control, the voltage vcm1 is vcm; as can be seen, the third sampling capacitor C at the upper part of the circuit from the first clock signal CLK1 to the second clock signal CLK2S3The amount of change in charge of (d) is [ (vinp-vinn) - (vcm-vcm)]*CS/2＝(vinp-vinn)*CS/2, fourth sampling capacitor C at the lower part of the circuitS4The amount of change in charge of (d) is [ (vinn-vinp) - (vcm-vcm)]*CS/2＝(vinn-vinp)*CS2, the voltage difference across the selected cell is therefore [ (vinp-vinn) × CS/2–(vinn-vinp)*CS/2]/CS(iii)/2 ═ vinp-vinn, where CS3＝CS4＝CS/2。
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| CN113063981B (en) * | 2021-03-03 | 2024-03-22 | 上海摩芯半导体技术有限公司 | Battery pack voltage acquisition circuit and voltage acquisition method |
| CN113078717B (en) * | 2021-05-06 | 2022-05-13 | 北京时代民芯科技有限公司 | Voltage dump circuit applied to voltage sampling of multiple batteries |
| CN113507287A (en) * | 2021-06-18 | 2021-10-15 | 深圳天德钰科技股份有限公司 | Sample-and-hold circuit and electronic device with same |
| CN113625034B (en) * | 2021-07-19 | 2024-05-24 | 杭州知存算力科技有限公司 | Sampling circuit, sampling array, integrated memory chip and electronic equipment |
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| CN104283565A (en) * | 2013-06-24 | 2015-01-14 | 硅实验室股份有限公司 | Capacitance to Digital Converter and Method |
| JP2016042627A (en) * | 2014-08-14 | 2016-03-31 | 旭化成エレクトロニクス株式会社 | Fully differential switched capacitor circuit |
| CN105490649A (en) * | 2014-09-15 | 2016-04-13 | 万高(杭州)科技有限公司 | Instrument amplifier |
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| US7843232B2 (en) * | 2009-02-27 | 2010-11-30 | Atmel Corporation | Dual mode, single ended to fully differential converter structure |
| CN104283565A (en) * | 2013-06-24 | 2015-01-14 | 硅实验室股份有限公司 | Capacitance to Digital Converter and Method |
| JP2016042627A (en) * | 2014-08-14 | 2016-03-31 | 旭化成エレクトロニクス株式会社 | Fully differential switched capacitor circuit |
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Application publication date: 20170908 Assignee: Jiyao cabinet (Tianjin) Medical Technology Co.,Ltd. Assignor: TJU BINHAI INDUSTRIAL RESEARCH INSTITUTE CO.,LTD. Contract record no.: X2022980026634 Denomination of invention: A High Voltage Signal Sampling Circuit Based on Double Sampling Technology Granted publication date: 20200707 License type: Common License Record date: 20230104 |
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Assignee: Jiyao cabinet (Tianjin) Medical Technology Co.,Ltd. Assignor: TJU BINHAI INDUSTRIAL RESEARCH INSTITUTE CO.,LTD. Contract record no.: X2022980026634 Date of cancellation: 20231017 |