CN113063981B - Battery pack voltage acquisition circuit and voltage acquisition method - Google Patents
Battery pack voltage acquisition circuit and voltage acquisition method Download PDFInfo
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- CN113063981B CN113063981B CN202110233790.8A CN202110233790A CN113063981B CN 113063981 B CN113063981 B CN 113063981B CN 202110233790 A CN202110233790 A CN 202110233790A CN 113063981 B CN113063981 B CN 113063981B
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 20
- 238000010586 diagram Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/396—Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/4207—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells for several batteries or cells simultaneously or sequentially
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/48—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
- H01M10/482—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte for several batteries or cells simultaneously or sequentially
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Secondary Cells (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
The invention relates to the technical field of voltage acquisition, in particular to a battery pack voltage acquisition circuit and a voltage acquisition method. Compared with the prior art, the invention has the advantages of simple and feasible combined structure, and the invention has the following advantages: the battery pack voltage acquisition circuit and the voltage acquisition method reduce the number of branches in the module, acquire battery voltage by adopting one transconductance amplifier to reduce power consumption, realize output by using one port, only generate one-level offset voltage, realize voltage acquisition of a plurality of batteries, meet the requirements of low cost, low power consumption and small area, and more accurately realize acquisition of the voltages of all the batteries in the battery pack.
Description
Technical Field
The invention relates to the technical field of voltage acquisition, in particular to a battery pack voltage acquisition circuit and a voltage acquisition method.
Background
Since the advent of electronic products, batteries have played an extremely important role as power sources for electronic products. The battery is largely classified into a primary battery and a secondary battery. Wherein the primary battery is not rechargeable, such as a dry cell battery or the like; the secondary battery is called a rechargeable battery, and is an ideal power supply for electronic products. With the popularity of portable electronic devices and various electric vehicles, rechargeable batteries are becoming increasingly important.
Many electronic devices, such as portable computers, cellular phones, electric vehicles, and other electronic devices, employ a plurality of battery cells connected in series to meet the current and voltage requirements. Overcharge and overdischarge of the individual cells during the charge and discharge of the cells may result in degradation of the performance and life of the battery pack. So, in order to ensure the safety and life of the battery, protection circuits are gradually developed as necessary accessories of the rechargeable battery, and the acquisition of the battery voltage is particularly important. Some conventional voltage comparators require trimming of the voltage, for example, if the voltage on the first terminal is V1 and the voltage on the second terminal is V2, then the voltage V12 between the first terminal and the second segment can be represented by v12=v1-V2. To check a battery voltage condition, such as an overvoltage or undervoltage condition, the voltage V12 needs to be compared to one or more reference voltages, which may need to be relative to a reference level equal to V1 or V2. In addition, the reference level may need to be adjusted according to different requirements, and a large number of reference voltage adjustment processes are required. In some conventional battery protection controllers, where multiple batteries are connected in series, all battery voltages may need to be compared to one or more reference voltages. Such battery protection controllers require a large number of trimming processes, which increase cost, power consumption, and circuit area.
As shown in FIG. 1, the conventional voltage acquisition circuit 100 includes rechargeable batteries 101-1 to 101-N, voltage-to-current converter modules 112-1 to 112-N, and resistors 105-1 to 105-N, wherein the voltage-to-current converter modules 112-1 to 112-N include resistors 102-1 to 102-N, operational amplifiers 103-1 to 103-N, and PMOS tubes 104-1 to 104-N, respectively. Specifically, one end of the battery 101-1-101-N is connected with the resistor 102-1-102-N, the other end of the battery 101-1-101-N is connected with the positive input end of the operational amplifier 103-1-103-N, the negative input end of the operational amplifier 103-1-103-N is connected with the other end of the resistor 102-1-102-N and is connected with the source electrode of the PMOS tube 104-1-104-N to form negative feedback, the grid electrode of the PMOS tube 104-1-104-N is connected with the output end of the operational amplifier 103-1-103-N, the drain electrode of the PMOS tube 104-1-104-N is connected with one end of the resistor 105-1-105-N and outputs sampling signals V102-1-V102-N, and the other end of the resistor 105-1-105-N is grounded.
The working process of the circuit is as follows: in the current-voltage converter 112-1, the operational amplifier 103-1 and the PMOS transistor 104-1 are connected to form a negative feedback loop, the voltage of the positive input end and the voltage of the negative input end of the operational amplifier are equal through negative feedback adjustment, that is, v+=v-, according to the virtual short, the current I102-1 flowing through the resistor 102-1 flows to the resistor 105-1 through the PMOS transistor 104-1, the current value I102-1 is I102-1=v102-1/R102-1, and if the resistance value of the resistor 105-1 is equal to the resistance value of the resistor 102-1, the voltage V102-1 at both ends of the resistor 105-1 is equal to the voltage value of the battery 101-1, thereby completing the acquisition of the battery voltage.
The working process of the existing voltage acquisition circuit is described by taking the acquisition of one battery voltage as an example, based on the principle, and so on, when N batteries exist, N voltage-current converters 112-1-112-i, 2-i-N, N resistors 102-1-102-i, 2-i-N, N resistors 105-1-105-i, 2-i-N are used, and the acquisition of N battery voltages can be realized.
When N batteries exist, each stage of negative feedback loop can generate offset voltage, offset voltage of each stage needs to be compensated, and as each stage is provided with an operational amplifier, current needs to be sampled through a sampling resistor and converted into voltage signals, the circuit area is large, and the power consumption is large.
Disclosure of Invention
The invention aims to solve the defects of the prior art and provides a battery pack voltage acquisition circuit and a battery pack voltage acquisition method, which can more conveniently realize battery pack voltage acquisition.
In order to achieve the above object, a battery voltage acquisition circuit is designed, the battery comprises at least two batteries which are sequentially connected in series, the battery voltage acquisition circuit comprises a transconductance amplifier, the transconductance amplifier comprises two voltage input ends and a voltage output end, the voltage output end is connected with a resistor, and two ends of the at least two batteries which are sequentially connected in series are respectively connected with a switch and then are connected to the two voltage input ends of the transconductance amplifier.
Preferably, the two voltage input ends of the transconductance amplifier are respectively connected to a resistor and then connected to the source electrode of the first PMOS tube and the gate electrode of the second PMOS tube, the drain electrodes of the two first PMOS tubes are connected and then connected to the voltage output end, the drain electrodes of the two second PMOS tubes are respectively connected to one drain electrode of the first current mirror circuit and one drain electrode of the second current mirror circuit, the other drain electrode of the first current mirror circuit and the other drain electrode of the second current mirror circuit are respectively connected to the two drain electrodes of the third current mirror circuit and the gate electrode of the corresponding first PMOS tube, the other drain electrode of the first current mirror circuit is also connected to one end of the first switch, the other drain electrode of the second current mirror circuit is also connected to one end of the second switch, and the other end of the first switch and the other end of the second switch are connected and then connected to the gate electrode of the third current mirror circuit.
Preferably, the first current mirror circuit and the second current mirror circuit respectively comprise two NMOS tubes with gate ends connected.
Preferably, the third current mirror circuit comprises two PMOS transistors with gate ends connected.
Preferably, the source of the third current mirror circuit is connected to the VCC terminal, and the sources of the first current mirror circuit and the second current mirror circuit are grounded.
Preferably, the gate ends of the two first PMOS transistors are further connected to a capacitor, and then connected to a VCC terminal of the power supply.
Preferably, the transconductance amplifier comprises a capacitor 303-1 and a capacitor 303-2, a resistor 301-1 and a resistor 301-2, PMOS tubes 302-1 to 302-6, NMOS tubes 304-1 to 304-4, a switch 305-1 and a switch 305-2, wherein one end of the capacitor 303-1 is connected with the source of the PMOS tube 302-1 and the source of the PMOS tube 302-2 and one end of the capacitor 303-2 and is connected with a power supply VCC, the other end of the capacitor 303-1 is connected with the drain of the PMOS tube 302-1 and the gate of the PMOS tube 302-6, the gate of the PMOS tube 302-1 is connected with the gate of the PMOS tube 302-2 and is connected with one ends of the switch 305-1 and the switch 305-2, the drain of the PMOS tube 302-1 is connected with the other end of the switch 305-1 and is connected with the drain of the NMOS tube 304-1, the switch 305-1 is connected in series with the switch 305-2, the drain of the PMOS tube 302-2 is connected with the drain of the switch 305-2 and the drain of the NMOS tube 304-4 and is connected to the other end of the capacitor 303-2 and the gate of the PMOS tube 302-5, the gate of the PMOS tube 302-3 is connected to the source of the PMOS tube 302-5, the source of the PMOS tube 302-3 is connected with the source of the PMOS tube 302-4 and is connected to one end of the current source 306, the drain of the PMOS tube 302-3 is connected with the drain of the NMOS tube 304-2, the gate of the NMOS tube 304-1 is connected with the gate of the NMOS tube 304-2 and is connected to the drain of the NMOS tube 304-2, the source of the NMOS tube 304-1 is connected with the source of the NMOS tube 304-2, the NMOS tube 304-3 and the source of the NMOS tube 304-4 in parallel, the grid electrode of the PMOS tube 302-4 is connected with the source electrode of the PMOS tube 302-6, the drain electrode of the PMOS tube 302-4 is connected with the drain electrode of the NMOS tube 304-3, the grid electrode of the NMOS tube 304-3 is connected with the grid electrode of the NMOS tube 304-4 and is connected with the drain electrode of the NMOS tube 304-3, the source electrode of the PMOS tube 302-5 is connected with one end of the resistor 301-1, the other end of the resistor 301-1 is connected with the input end of the transconductance amplifier 203, the drain electrode of the PMOS tube 302-5 is used as the output end of the transconductance amplifier 203 to be output, the drain electrode of the PMOS tube 302-6 is connected with the drain electrode of the PMOS tube 302-5, the source electrode of the PMOS tube 302-6 is connected with one end of the resistor 301-2, and the other end of the resistor 301-2 is used as the other input end of the transconductance amplifier 203.
Preferably, the resistances of the resistor 301-1, the resistor 301-2 and the resistor connected to the voltage output terminal are equal.
The invention also relates to a voltage acquisition method of the battery pack, which adopts the battery pack voltage acquisition circuit to acquire voltage.
Preferably, when voltage acquisition is performed, the switches at two ends of each battery are closed in sequence, and for the odd-numbered batteries, the first switch is also closed at the same time; for the even number of batteries, the second switch is also closed at the same time so as to collect the voltage.
Advantageous effects of the invention
Compared with the prior art, the invention has the advantages of simple and feasible combined structure, and the invention has the following advantages: the battery pack voltage acquisition circuit and the voltage acquisition method reduce the number of branches in the module, acquire battery voltage by adopting one transconductance amplifier to reduce power consumption, realize output by using one port, only generate one-level offset voltage, realize voltage acquisition of a plurality of batteries, meet the requirements of low cost, low power consumption and small area, and more accurately realize acquisition of the voltages of all the batteries in the battery pack.
Drawings
Fig. 1 is a schematic diagram of a conventional battery voltage acquisition circuit.
Fig. 2 schematically illustrates a battery voltage acquisition circuit in one embodiment of the invention.
Fig. 3 schematically shows an internal circuit diagram of a transconductance amplifier in one embodiment of the invention.
Detailed Description
The construction and principles of such circuits and methods will be apparent to those skilled in the art from the following description of the invention taken in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention provides a battery pack voltage acquisition circuit, which comprises at least two batteries connected in series in sequence, wherein the battery pack voltage acquisition circuit comprises a transconductance amplifier, the transconductance amplifier comprises two voltage input ends and a voltage output end, the voltage output end is connected with a resistor, and two ends of the at least two batteries connected in series in sequence are respectively connected with a switch and then are connected to the two voltage input ends of the transconductance amplifier.
The two voltage input ends of the transconductance amplifier are respectively connected with a resistor and then connected with the source electrode of the first PMOS tube and the grid electrode of the second PMOS tube, the drain electrodes of the two first PMOS tubes are connected and then connected with the voltage output end, the drain electrodes of the two second PMOS tubes are respectively connected with one drain electrode of the first current mirror circuit and one drain electrode of the second current mirror circuit, the other drain electrode of the first current mirror circuit and the other drain electrode of the second current mirror circuit are respectively connected with the two drain electrodes of the third current mirror circuit and the grid electrode of the corresponding first PMOS tube, the other drain electrode of the first current mirror circuit is also connected with one end of the first switch, the other drain electrode of the second current mirror circuit is also connected with one end of the second switch, and the other end of the first switch is connected with the other end of the second switch and then connected with the grid electrode of the third current mirror circuit.
When in use, the switches at the two ends of each battery are closed in sequence, and for the odd batteries, the first switch is also closed at the same time; for the even number of batteries, the second switch is also closed at the same time so as to realize voltage acquisition.
The structure and method of the present invention are illustrated in the following description, taken in conjunction with the accompanying drawings and specific embodiments.
Example 1
The present embodiment provides a battery voltage acquisition circuit 200. Referring to fig. 2, the battery voltage acquisition circuit 200 includes batteries 201-1 to 201-N, switches 203 to 202-n+1, a transconductance amplifier 203, and a resistor 204. Specifically, the batteries 201-1 to 201-N are sequentially connected in series, one end of the batteries 201-1 to 201-i (i is more than or equal to 1 and less than or equal to N) is connected with a switch 202-i (i=1, 3,5, N), the other end switches 202-i (i=2, 4,6, ·, n+1), switch 202-i (i=1, 3,5, N) V connected to the transconductance amplifier 203 IN1 The end, switch 202-i (i=2, 4,6, ·, n+1) V connected to the transconductance amplifier 203 IN2 The output of the transconductance amplifier 203 is connected to one end of a resistor 204, and the other end of the resistor 204 is grounded.
As a specific scheme of an embodiment, as shown in FIG. 3, the transconductance amplifier 203 includes a capacitor 303-1, a capacitor 303-2, a resistor 301-1, a resistor 301-2, PMOS tubes 303-302-6, NMOS tubes 304-1-304-4, a switch 305-1, a switch 305-2, and a current source 306. The PMOS tubes 302-5 and 302-6 are the first PMOS tube, the PMOS tubes 302-3 and 302-4 are the second PMOS tube, the NMOS tubes 304-1 and 304-2 form a first current mirror circuit, the NMOS tubes 304-3 and 304-4 form a second current mirror circuit, the PMOS tubes 303 and 302-2 form a third current mirror circuit, the switch 305-1 is the first switch, and the switch 305-2 is the second switch.
Specifically, VCC represents a power supply positive electrode, VSS represents a power supply negative electrode, one end of the capacitor 303-1 is connected with the source of the PMOS tube 303 and the source of the PMOS tube 302-2 and one end of the capacitor 303-2 and is connected to the power supply VCC, the other end of the capacitor 303-1 is connected with the drain of the PMOS tube 303 and the gate of the PMOS tube 302-6, the gate of the PMOS tube 303 is connected to the gate of the PMOS tube 302-2 and is connected to one end of the switch 305-1 and one end of the switch 305-2 respectively, the drain of the PMOS tube 303 is connected with the other end of the switch 305-1 and is connected to the drain of the NMOS tube 304-1, the drain of the switch 305-1 is connected in series with the switch 305-2, the drain of the PMOS tube 302-2 and the drain of the NMOS tube 304-4 are connected to the other end of the capacitor 303-2 and the gate of the PMOS tube 302-5, the gate of PMOS tube 302-3 is connected to the source of PMOS tube 302-5, the source of PMOS tube 302-3 is connected to the source of PMOS tube 302-4 and to one end of current source 306, the drain of PMOS tube 302-3 is connected to the drain of NMOS tube 304-2, the gate of NMOS tube 304-1 is connected to the gate of NMOS tube 304-2 and to the drain of NMOS tube 304-2, the source of NMOS tube 304-1 is connected to NMOS tube 304-2, the sources of NMOS tube 304-3 and NMOS tube 304-4 in parallel with VSS, the gate of PMOS tube 302-4 is connected to the source of PMOS tube 302-6, the drain of PMOS tube 302-4 is connected to the drain of NMOS tube 304-3, the gate of NMOS tube 304-3 is connected to the gate of NMOS tube 304-4 and to the drain of NMOS tube 304-3, the source of the PMOS tube 302-5 is connected with one end of the resistor 301-1, the other end of the resistor 301-1 is connected with the input end of the transconductance amplifier 203, the drain of the PMOS tube 302-5 is used as the output end of the transconductance amplifier 203 for output, the drain of the PMOS tube 302-6 is connected with the drain of the PMOS tube 302-5, the source of the PMOS tube 302-6 is connected with one end of the resistor 301-2, and the other end of the resistor 301-2 is used as the other input end of the transconductance amplifier 203. Specifically, VCC represents the positive power supply electrode, and VSS represents the negative power supply electrode.
Example two
Further, in the present embodiment, the battery voltage acquisition circuit shown in the first embodiment is taken as an example, and the battery voltage acquisition method is described as an example, specifically, the working process of the present embodiment is as follows.
As shown in fig. 2, when the switch 203 is closed with the switch 202-2, the voltage of the battery 201-1 is collected, when the switch 202-2 is closed with the switch 202-3, the voltage of the battery 201-2 is collected, …, and when the switch 202-N is closed with the switch 202-n+1, the voltage of the battery 201-N is collected.
To collectFor example, when the switch 203 is closed with the switch 202-2, the voltage of the battery cell 201-1 is collected, and the positive electrode of the battery cell is connected to the V of the transconductance amplifier 203 as shown in FIG. 3 IN1 The negative electrode of the battery 201-1 is connected to the V of the transconductance amplifier IN2 The end, switch 305-1 is closed, at this time PMOS tube 302-4 is turned on at a low level, NMOS tube 304-3 and NMOS tube 304-4 form a current mirror, the current flowing through PMOS tube 302-4 is mirrored, PMOS tube 303 and PMOS tube 302-2 form a current mirror, the current flowing through NMOS tube 304-4 is mirrored, and NMOS tube 304-1 and NMOS tube 304-2 are also not turned on due to non-conduction of PMOS tube 302-3, so that the current flowing through PMOS tube 303 flows into PMOS tube 302-6 to turn on PMOS tube 302-6, at this time the voltage of battery 201-1 is converted into current from output end V of transconductance amplifier OUT Output, current I at output end OUT Has a value of I OUT =V 201-1 /R 301-1 If the resistance R of the resistor 301-1 301-1 Resistance R of resistor 204 204 The voltage at terminal 204 is equal to the voltage of battery 201-1.
Taking the voltage of the battery 201-2 as an example, when the switch 202-2 and the switch 202-3 are closed, referring to fig. 3, the positive electrode of the battery 201-2 is connected to the V of the transconductance amplifier 203 IN2 The negative electrode of the battery 201-2 is connected to the V of the transconductance amplifier IN1 The end, switch 305-2 is closed, at this time PMOS tube 302-3 is turned on at a low level, NMOS tube 304-1 and NMOS tube 304-2 form a current mirror, the current flowing through PMOS tube 302-3 is mirrored, PMOS tube 303 and PMOS tube 302-2 form a current mirror, the current flowing through NMOS tube 304-1 is mirrored, and NMOS tube 304-3 and NMOS tube 304-4 are also not turned on, so that the current flowing through PMOS tube 302-2 flows into PMOS tube 302-5 to turn on PMOS tube 302-5, at this time the voltage of battery 201-2 is converted into current from output end V of the transconductance amplifier OUT Output, current I at output end OUT Has a value of I OUT =V 201-2 /R 301-2 If the resistance R of the resistor 301-2 301-2 Resistance R of resistor 204 204 Equal, the voltage across resistor 204 is the voltage of battery 201-2.
The working process of the voltage acquisition circuit of the invention is described above by taking two battery voltages as an example, and based on the principle, the voltage acquisition of N batteries can be realized by using N+1 switches 203-202-N+1, one transconductance amplifier 203 and one resistor 204. Wherein 'i' represents the number of the devices, 'N' represents the number of the devices, the number of the devices is a natural number, and the value ranges are 1-i-N.
Claims (9)
1. The battery voltage acquisition circuit is characterized by comprising a transconductance amplifier, wherein the transconductance amplifier comprises two voltage input ends and one voltage output end, the voltage output end is connected with a resistor, one end of the at least two batteries which are sequentially connected in series is connected with a switch and then is connected to one voltage input end of the transconductance amplifier, the other end of the at least two batteries which are sequentially connected in series is connected with a switch and then is connected to the other voltage input end of the transconductance amplifier, one voltage input end of the transconductance amplifier is connected with a resistor and then is connected to the source electrode of a first PMOS tube and the grid electrode of a second PMOS tube respectively, the other voltage input end of the transconductance amplifier is connected with the source electrode of the other first PMOS tube and the grid electrode of the other second PMOS tube respectively, the drains of the two first PMOS tubes are connected to the voltage output end after being connected with a switch, the drains of the first PMOS tube is connected to the drain electrode of the first PMOS tube and the drain electrode of the other PMOS tube respectively, the drains of the first PMOS tube and the drain electrode of the first PMOS tube are connected to the drain electrode of the other PMOS tube respectively, the drains of the first PMOS tube and the drain electrode of the second PMOS tube are connected to the drain electrode of the other PMOS tube respectively, the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube are connected to the drain electrode of the other PMOS tube respectively, the other end of the first switch is connected with the other end of the second switch and then connected to the grid electrode of the third current mirror circuit.
2. The battery voltage acquisition circuit of claim 1 wherein the first current mirror circuit and the second current mirror circuit each comprise two NMOS transistors with their gates connected.
3. The battery voltage acquisition circuit as recited in claim 1, wherein the third current mirror circuit comprises two PMOS transistors with their gates connected.
4. The battery voltage acquisition circuit of claim 1 wherein the source of the third current mirror circuit is connected to the power supply VCC and the sources of the first and second current mirror circuits are grounded.
5. The battery voltage acquisition circuit as recited in claim 4, wherein the gates of the two first PMOS transistors are further connected to a capacitor, respectively, and then connected to a VCC terminal of the power supply.
6. The battery voltage acquisition circuit of claim 1 wherein the transconductance amplifier comprises a capacitor 303-1 and a capacitor 303-2, a resistor 301-1 and a resistor 301-2, PMOS tubes 302-1-302-6, NMOS tubes 304-1-304-4, a switch 305-1 and a switch 305-2, wherein one end of the capacitor 303-1 is connected to the source of the PMOS tube 302-1 and the source of the PMOS tube 302-2 and one end of the capacitor 303-2 and is connected to VCC, the other end of the capacitor 303-1 is connected to the drain of the PMOS tube 302-1 and the gate of the PMOS tube 302-6, the gate of the PMOS tube 302-1 is connected to the gate of the PMOS tube 302-2, the connection points are respectively connected to one ends of the switch 305-1 and the switch 305-2, the drain of the PMOS tube 302-1 is connected with the other end of the switch 305-1 and is connected to the drain of the NMOS tube 304-1, the switch 305-1 is connected in series with the switch 305-2, the drain of the PMOS tube 302-2 is connected with the switch 305-2 and the drain of the NMOS tube 304-4 and is connected to the other end of the capacitor 303-2 and the grid of the PMOS tube 302-5, the grid of the PMOS tube 302-3 is connected to the source of the PMOS tube 302-5, the source of the PMOS tube 302-3 is connected with the source of the PMOS tube 302-4 and is connected to one end of the current source 306, the drain of the PMOS tube 302-3 is connected with the drain of the NMOS tube 304-2, the grid of the NMOS tube 304-1 is connected with the grid of the NMOS tube 304-2 and is connected to the drain of the NMOS tube 304-2, the source of the NMOS tube 304-1 is connected with the NMOS tube 304-2, the NMOS tube 304-2, the source of NMOS tube 304-3 and NMOS tube 304-4 are connected in parallel with VSS, the grid of PMOS tube 302-4 is connected with the source of PMOS tube 302-6, the drain of PMOS tube 302-4 is connected with the drain of NMOS tube 304-3, the grid of NMOS tube 304-3 is connected with the grid of NMOS tube 304-4 and is connected to the drain of NMOS tube 304-3, the source of PMOS tube 302-5 is connected with one end of resistor 301-1, the other end of resistor 301-1 is connected with the input end of transconductance amplifier 203, the drain of PMOS tube 302-5 is output as the output end of transconductance amplifier 203, the drain of PMOS tube 302-6 is connected with the drain of PMOS tube 302-5, the source of PMOS tube 302-6 is connected with one end of resistor 301-2, the other end of resistor 301-2 is the other input end of transconductance amplifier 203, VCC represents the positive power supply, and VSS represents the negative power supply.
7. The battery voltage acquisition circuit of claim 6 wherein the resistors 301-1, 301-2 are equal in resistance to the resistors connected to the voltage output.
8. A method for collecting voltage of a battery pack, characterized in that the voltage collection circuit of the battery pack according to any one of claims 1-7 is used for collecting voltage.
9. The method of voltage acquisition of a battery pack according to claim 8, wherein the switches at both ends of each cell are closed in turn, and the first switch is closed for the odd numbered cells and the second switch is closed for the even numbered cells to perform voltage acquisition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110233790.8A CN113063981B (en) | 2021-03-03 | 2021-03-03 | Battery pack voltage acquisition circuit and voltage acquisition method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110233790.8A CN113063981B (en) | 2021-03-03 | 2021-03-03 | Battery pack voltage acquisition circuit and voltage acquisition method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113063981A CN113063981A (en) | 2021-07-02 |
| CN113063981B true CN113063981B (en) | 2024-03-22 |
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| CN114355027B (en) * | 2022-03-17 | 2022-06-14 | 深圳市芯卓微科技有限公司 | Detection circuit and chip |
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