CN107134466B - 软性面板及其制作方法 - Google Patents
软性面板及其制作方法 Download PDFInfo
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
一种软性面板,具有基板、第一绝缘层、第二绝缘层、牺牲层及金属走线层。基板定义有主动区、周边电路区及中介区。第一绝缘层位于基板所述的三个区域,位于中介区的第一绝缘层具有第一图形。第二绝缘层位于第一绝缘层上,位于中介区的第二绝缘层具有第一开口沿着第一方向延伸,使第二绝缘层未覆盖第一绝缘层的第一图形。牺牲层位于中介区的第一绝缘层与第二绝缘层之间,未覆盖第一绝缘层的第一图形。金属走线层延伸于主动区与周边电路区之间,于主动区与周边电路区中位于第二绝缘层上方,于中介区则经由第一开口接触第一绝缘层的第一图形。
Description
技术领域
本发明系关于一软性面板及其制作方法。
背景技术
随着工艺技术的演进以及消费者的需求,越来越多电子大厂积极投入于研发软性面板,也就是可挠式面板。为了缩减显示设备的边界宽度,制造业者减薄面板的部份无机层,以让金属走线弯折至显示设备背面。然而,由于一般无机层的厚度相当厚且蚀刻速率相当大,若是直接对无机层进行蚀刻,将使无机层残余厚度的差异甚大,影响其弯折能力,导致布于无机层上方的金属走线可能因此产生断裂的情况。
发明内容
本发明在于提供一种软性面板及其制作方法,用以提升对无机层进行蚀刻后,无机层残余厚度的均匀性。
依据本发明一实施例的软性面板,具有基板、第一绝缘层、第二绝缘层、牺牲层及金属走线层。基板被定义有主动区、周边电路区及中介区,其中中介区位于主动区及周边电路区之间。第一绝缘层位于基板的主动区、周边电路区与中介区,其中位于中介区的第一绝缘层具有第一图形。第二绝缘层则位于第一绝缘层上,其中位于中介区的第二绝缘层具有第一开口沿着第一方向延伸,使得第二绝缘层未覆盖第一绝缘层的第一图形。牺牲层位于第一绝缘层与第二绝缘层之间,且牺牲层未覆盖第一绝缘层的第一图形。金属走线层延伸于主动区与周边电路区之间。于主动区中与周边电路区中,金属走线层位于第二绝缘层上方,而于中介区中,金属走线层经由第一开口而接触第一绝缘层的第一图形。
依据本发明一实施例的软性面板,具有基板、第一绝缘层、第二绝缘层、晶体管结构及金属走线层。基板被定义有主动区、周边电路区与中介区,其中中介区位于主动区及周边电路区之间。第一绝缘层位于基板的主动区、周边电路区及中介区,其中位于中介区的第一绝缘层具有一第一图形。第二绝缘层则位于第一绝缘层上,其中位于中介区的第二绝缘层具有第一开口沿第一方向延伸,使得第二绝缘层未覆盖第一绝缘层的第一图形。晶体管结构位于第二绝缘层上且位于该主动区中,晶体管结构具有栅极、通道层、漏极及源极。金属走线层延伸于主动区与周边电路区之间。于主动区中与周边电路区中,金属走线层位于第二绝缘层上方,并于主动区中电性连接晶体管结构,而于中介区中,金属走线层经由第一开口而接触第一绝缘层的第一图形。
依据本发明一实施例的软性面板制作方法,其步骤包含:设置第一绝缘层于基板上,其中基板具有主动区、周边电路区以及介于主动区与周边电路区间的中介区;设置牺牲层于第一绝缘层上对应于基板的中介区处,该牺牲层具有一图形;设置第二绝缘层,覆盖第一绝缘层与牺牲层;图形化第二绝缘层,使第二绝缘层于中介区具有一开口以暴露出第一绝缘层与牺牲层;图形化第一绝缘层;以及蚀刻牺牲层暴露的部分。其中于图形化第二绝缘层与图形化第一绝缘层的步骤中,牺牲层的第一蚀刻率小于对第二绝缘层的第二蚀刻率,且牺牲层的第一蚀刻率小于对第一绝缘层的第三蚀刻率
借由上述结构,本案所揭示的软性面板及其制作方法,在需减薄以使金属走线可以弯折的无机层区域,加入蚀刻牺牲层以提升无机层减薄后残余厚度的均匀性,避免金属走线的弯折能力受到底下无机层的残余厚度影响,例如因差异甚大的均匀度导致金属走线的弯折处断裂。
以上的关于本揭露内容的说明及以下的实施方式的说明系用以示范与解释本发明的精神与原理,并且提供本发明的权利要求范围更进一步的解释。
附图说明
图1为依据本发明一实施例所绘示的软性面板的俯视图。
图2A为图1的软性面板的2A-2A剖面图。
图2B为图2A的软性面板的中介区的放大剖面图。
图2C为图2A的软性面板的中介区的俯视图。
图2D为图2C的软性面板的2D-2D切面图。
图3A为依据本发明一实施例所绘示的工艺中的软性面板的剖面图。
图3B为图3A的软性面板的中介区的俯视图。
图3C为图3B的软性面板的3C-3C切面图。
图4A为依据本发明一实施例所绘示的工艺中的软性面板的剖面图。
图4B为图4A的软性面板的中介区的俯视图。
图4C为图4B的软性面板的4C-4C切面图。
图5A为依据本发明一实施例所绘示的工艺中的软性面板的剖面图。
图5B为图5A的软性面板的中介区的俯视图。
图5C为图5B的软性面板的5C-5C切面图。
图6A为依据本发明一实施例所绘示的工艺中的软性面板的剖面图。
图6B为图6A的软性面板的中介区的俯视图。
图6C为图6B的软性面板的6C-6C切面图。
图7A为依据本发明一实施例所绘示的工艺中的软性面板的剖面图。
图7B为图7A的软性面板的中介区的俯视图。
图7C为图7B的软性面板的7C-7C切面图。
图8A为依据本发明一实施例所绘示的工艺中的软性面板的剖面图。
图8B为图8A的软性面板的中介区的俯视图。
图8C为图8B的软性面板的8C-8C切面图。
其中,附图标记:
10 软性面板
PI 基板
B1 第一绝缘层
B2 第二绝缘层
GI 第三绝缘层
ILD 介电质层
M0 牺牲层
M1 金属电极层
M2 金属走线层
Poly 通道层
Q1 晶体管结构
G 栅极
D 源极
S 漏极
AA 主动区
IA 中介区
SA 周边电路区
O1 第一开口
O2 第二开口
SW 凸起部
HO 凹陷部
PA1 第一图形
PA2 第二图形
PA3 第三图形
具体实施方式
以下在实施方式中详细叙述本发明的详细特征以及优点,其内容足以使任何熟习相关技艺者了解本发明的技术内容并据以实施,且根据本说明书所揭露的内容、权利要求及图式,任何本领域技术人员可轻易地理解本发明相关的目的及优点。以下的实施例为进一步详细说明本发明的观点,但非以任何观点限制本发明的范畴。
请参考图1,图1为依据本发明一实施例所绘示的软性面板的俯视图。如图1所示,软性面板10被定义为有主动区AA、中介区IA及周边电路区SA。其中主动区AA例如为指晶体管结构Q1或其他主动元件所在的区域,周边电路区SA为指周边电路的所在区域,中介区IA则为指位于主动区AA及周边电路区SA之间的区域。主动区AA的范围例如为圆形或方形,本发明不予限制。于此实施例中,中介区IA仅设置于软性面板的一侧,然本发明不以此为限,亦可视需求于主动区的其他侧设置中介区和周边电路区。
再来请参考图2A~2C,图2A为图1的软性面板的2A-2A剖面图,图2B为图2A的软性面板的中介区的放大剖面图,图2C则为图2A的软性面板的中介区的俯视图。如图2A及2B所示,软性面板10具有基板PI、第一绝缘层B1、第二绝缘层B2、牺牲层M0及金属走线层M2。基板PI被定义为有主动区AA、周边电路区SA以及中介区IA,即为图1中的主动区AA、周边电路区SA以及中介区IA。于一实施例中,基板PI为由软性塑料例如聚酰亚胺(Polyimide,PI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二酯(PET),或其他软性材质所组成。
第一绝缘层B1位于基板PI上的主动区AA、周边电路区SA以及中介区IA,其中位于中介区IA的第一绝缘层B1具有第一图形PA1。第二绝缘层B2则位于第一绝缘层B1上,其中位于中介区IA的第二绝缘层B2具有第一开口O1沿第一方向延伸。上述的第一方向平行于图2A中的Y轴方向。于一实施例中,第一绝缘层B1的第一图形PA1为沿着第二方向延伸,其中第二方向正交于上述的第一方向。更详细地说,第二方向平行于图2A中的X轴方向,亦即平行于从基板10的主动区AA往周边电路区SA的方向。而组成第一绝缘层B1与第二绝缘层B2的材料例如为氧化铝、氧化硅、氮化硅或其他无机材料,本发明不予限制。于实际的工艺中,第一绝缘层B1与第二绝缘层B2可以分别为厚度500埃(Angstrom,)的氮化硅及厚度的氧化硅。于另一实施例中,软性面板10具有多个第一绝缘层B1及多个第二绝缘层B2,其中第一绝缘层B1与第二绝缘层B2可以为多层交互堆栈。
牺牲层M0位于第一绝缘层B1与第二绝缘层B2之间,其中位于中介区的牺牲层M0具有第二开口O2,第二开口O2对应于第二绝缘层B2的第一开口O1。于一实施例中,牺牲层M0仅位于中介区IA中,被第二绝缘层B2覆盖的牺牲层M0具有第三图形PA3。而组成牺牲层M0的材料例如为钛、铊、铜、铝、钒、银、铂、铅、金或其组合。
金属走线层M2位于主动区AA、中介区IA及周边电路区SA,具有第二图形PA2。组成金属走线层M2的材料例如为选自由钛、铊、铜、铝、钒、银、铂、铅、金及其组合所组成的群组的其中之一。另外,组成金属走线层M2的材料的泊松比(Poisson’s ratio)可以大于0.32,所谓的泊松比为指当材料受拉伸或压缩力导致材料发生变形时,其横向变形量与纵向变形量的比值。于此实施例中,如图2A所示,主动区AA及周边电路区SA中,金属走线层M2为位于第二绝缘层B2之上,而于中介区IA中,金属走线层M2经第一开口O1延伸接触第一绝缘层B1。
再来请参考图2C与图2D,图2D为图2C的软性面板的2D-2D切面图,于一实施例中,如图2D所示,中介区IA中的金属走线层M2覆盖具有第一图形PA1的第一绝缘层B1。第一绝缘层B1的第一图形PA1具有至少一凸起部SW及凹陷部HO,而位于中介区IA的金属走线层M2具有第二图形PA2,其中第二图形PA2位于第一图形PA1的凸起部SW上方。于上述实施例中,第二图形PA2和第一图形PA1可以于垂直基板方向上实质地切齐,其中垂直基板方向平行于Z轴的方向。第一图形PA1的凸起部SW及凹陷部HO的数量可以为一或多个,本发明不予限制。而当第一图形PA1的凸起部SW及凹陷部HO的数量为多个时,第一图形PA1可为条纹图形,换句话说,第一图形PA1具有多个条状凸起部SW以及位于凸起部SW之间的多个条状凹陷部HO,其中相邻的两条状凸起部SW之间的间距(亦即,条状凹陷部HO的间距)介于2.5微米至100微米,多个条状凹陷部HO暴露出下方的基板PI。而于其他实施例中,中介区IA中的金属走线层M2可不覆盖具有第一图形PA1的第一绝缘层B1,也就是说,第一绝缘层B1的第一图形PA1具有至少一凹陷部HO,而金属走线层M2的第二图形PA2位于第一图形PA1的凹陷部HO。又或是,中介区IA中的金属走线层M2可部分覆盖于第一图形PA1的凸起部SW,部份覆盖于凹陷部HO。
请再参考图2A,如图2A所示,于一实施例中,软性面板10具有如同上述实施例中的基板PI、第一绝缘层B1、第二绝缘层B2及金属走线层M2,因此相关的详细内容于此不再赘述。于此实施例中,软性面板10更具有晶体管结构Q1位于主动区AA中的第二绝缘层B2上。晶体管结构Q1例如为薄膜晶体管,具有栅极G、通道层Poly、源极S与漏极D,其中栅极G为由金属电极层M1制作而成,通道层Poly则为由例如多晶硅层制作而成。于此实施例中,软性面板10的金属走线层M2更于主动区AA中透过金属电极层M1或直接连接至晶体管结构Q1的栅极G、漏极D或源极S。于一实施例中,软性面板10具有如同上述实施例中的基板PI、第一绝缘层B1、第二绝缘层B2、牺牲层M0、晶体管结构Q1及金属走线层M2,因此相关的详细内容于此不再赘述。于一实施例中,晶体管结构Q1不限形成于主动区AA中,亦可形成于周边电路区SA中。
接下来的叙述为关于软性面板10的制作过程的说明,请依序参考图3A~8C,其中图3A、4A、5A、6A、7A及8A为依据本发明一实施例所绘示的各阶段工艺中的软性面板的剖面图,而图3B、4B、5B、6B、7B及8B为分别对应于图3A、4A、5A、6A、7A及8A的软性面板中介区的俯视图,图3C、4C、5C、6C、7C及8C则为分别对应于图3A、4A、5A、6A、7A及8A的软性面板的切面图。
首先,如图3A~3C所示,于基板PI上设置第一绝缘层B1,并于第一绝缘层B1上设置牺牲层M0。接着,如图4A所示,图形化牺牲层M0,使剩余的牺牲层M0图案位于基板PI的中介区IA。于一实施例中,图形化牺牲层M0的步骤包含蚀刻牺牲层M0。如图4B及4C所示,图形化后的牺牲层M0形成至少一条状凸起部,呈现例如条纹图形,且条纹图形为沿着从主动区AA往周边电路区SA的方向(X轴方向)延伸。然而,本发明对于牺牲层M0图形化后的实际图形不予限制。
执行完图形化牺牲层M0的步骤后,如图5A~5C所示,设置第二绝缘层B2并使第二绝缘层B2覆盖第一绝缘层B1及牺牲层M0,并于第二绝缘层B2上覆盖第三绝缘层GI。于一实施例中,覆盖第三绝缘层GI之前更包含形成一层半导体图案,例如作为晶体管Q1的通道层Poly。再来,如图6A~6C所示,于第三绝缘层GI上涂布光刻胶PR,其中光刻胶PR于牺牲层M0上方具有开洞,而光刻胶PR开洞的宽度小于牺牲层M0的宽度,也就是说光刻胶PR将保护牺牲层M0的两端不被蚀刻,于是在后续蚀刻后,将留下牺牲层M0的两端。
接着,对第三绝缘层GI及第二绝缘层B2进行蚀刻,如图7A~7C所示,在对第三绝缘层GI及第二绝缘层B2进行蚀刻时,由于牺牲层M0的第一蚀刻率小于第二绝缘层B2的第二蚀刻率,因此由切面来看,如图7C所示,当第二绝缘层B2被蚀刻完而裸露出第一绝缘层B1的部份时,牺牲层M0几乎未被蚀刻,使得第二绝缘层B2的第一开口O1暴露出位于中介区的牺牲层M0及部分第一绝缘层B1。于此实施例中,蚀刻可采用干蚀刻方法进行蚀刻,然本发明不以此为限。蚀刻方法可利用对牺牲层M0的第一蚀刻率小于对第二绝缘层B2的第二蚀刻率的蚀刻剂进行即可。
接着,如图8A~8C所示,继续于中介区IA中对牺牲层M0及第一绝缘层B1进行蚀刻,由于牺牲层M0的第一蚀刻率小于第一绝缘层B1的第三蚀刻率,此阶段以牺牲层M0作为掩膜继续蚀刻裸露的部份第一绝缘层B1,接着,继续蚀刻或例如再转换蚀刻剂使得牺牲层M0的蚀刻率大于第一绝缘层B1的蚀刻率,对牺牲层M0进行蚀刻,使第二绝缘层B2的第一开口O1暴露出第一绝缘层B1及位于中介区边缘的残余牺牲层M0,而原未被牺牲层M0所覆盖的第一绝缘层B1则被蚀刻干净而露出基板PI。最后,移除光刻胶层PR。于此实施例中,如图8A及8B所示,被第二绝缘层B2覆盖的牺牲层M0具有第三图形PA3,第三图形PA3延伸对应于第一绝缘层B1的第一图形PA1,且位于第一开口O1两侧的第二绝缘层B2与第一绝缘层B1之间。另外,如图8C所示,蚀刻后剩余的第一绝缘层B1为于图7C中位于牺牲层M0下的部份第一绝缘层B1,由于蚀刻牺牲层M0的速率与蚀刻第一绝缘层B1的速率不同,因此蚀刻完牺牲层M0后,底下剩余的第一绝缘层B1可以有较为平整的表面与均匀的厚度。
举例来说,前述蚀刻第三绝缘层GI、第二绝缘层B2以及第一绝缘层B1的步骤中,第二蚀刻率与第一蚀刻率的比例为介于3倍至50倍,且第三蚀刻率与第一蚀刻率的比例为介于3倍至50倍。上述的蚀刻率为指每一单位时间内被侵蚀的厚度,例如埃/分钟(Angstrom/minute,)。请参考表1,表1为指氮化硅、氧化硅及牺牲层M0的层别的平均蚀刻率,如表1所示,氮化硅层、氧化硅层及牺牲层M0的平均蚀刻率分别约为及 换句话说,在干蚀刻下,平均每分钟可以使得氮化硅层的厚度减少2177埃,使氧化硅层的厚度减少760埃,并使牺牲层M0的厚度减少121埃,因此能将非位于牺牲层M0之下的第一绝缘层B1蚀刻干净。
表1
请再回到图2A及2C,于一实施例中,在使第二绝缘层B2于中介区具有第一开口O1以暴露出第一绝缘层B1与残余的牺牲层M0后,将进一步于第二绝缘层B2上设置晶体管结构Q1以及金属走线层M2。于一实施例中,设置金属走线层M2的步骤为指于主动区AA、中介区IA及周边电路区SA设置金属走线层M2,使金属走线层自主动区AA经由第一开口O1延伸至周边电路区SA,并使金属走线层M2对应于第一绝缘层B1的第一图形PA1,如图2C所示。如此一来,金属走线层M2将设置于具有平整表面的第一绝缘层B1上,避免以往因底层不平整而导致金属走线断裂的情况。
借由上述结构,本案所揭示的软性面板及其制作方法,在需减薄以使金属走线可以弯折的无机层区域,加入蚀刻牺牲层以提升无机层减薄后残余厚度的均匀性,避免金属走线的弯折能力受到底下无机层的残余厚度影响,例如因差异甚大的均匀度导致金属走线的弯折处断裂。
当然,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明权利要求的保护范围。
Claims (19)
1.一种软性面板,其特征在于,包含:
一基板,定义有一主动区、一周边电路区与一中介区,该中介区位于该主动区与该周边电路区之间;
一第一绝缘层,位于该基板上的该主动区、该周边电路区与该中介区,其中该第一绝缘层于该中介区具有一第一图形;
一第二绝缘层,位于该第一绝缘层上,该第二绝缘层于该中介区具有一第一开口,且该第一开口沿一第一方向延伸,使得该第二绝缘层未覆盖该第一绝缘层的该第一图形;
一牺牲层,位于该中介区的该第一绝缘层与该第二绝缘层之间,且该牺牲层未覆盖该第一绝缘层的该第一图形;以及
一金属走线层,延伸于该主动区与该周边电路区之间,于该主动区中与该周边电路区中该金属走线层位于该第二绝缘层上方,于该中介区中该金属走线层经由该第一开口而接触该第一绝缘层的该第一图形。
2.如权利要求1所述的软性面板,其特征在于,该金属走线层于该中介区覆盖具有该第一图形的该第一绝缘层。
3.如权利要求1所述的软性面板,其特征在于,该第一图形沿一第二方向延伸,该第二方向与该第一方向正交,且该第二方向为指由该主动区往该周边电路区的一方向。
4.如权利要求1所述的软性面板,其特征在于,该第一图形具有至少一凸起部,该金属走线层于该中介区具有一第二图形位于该至少一凸起部上。
5.如权利要求1所述的软性面板,其特征在于,该牺牲层被该第二绝缘层覆盖的部分具有一第三图形,该第三图形位于该第一开口两侧且分别延伸对应于该第一图形。
6.如权利要求1所述的软性面板,其特征在于,该第一图形为一条纹图形。
7.如权利要求6所述的软性面板,其特征在于,该条纹图形具有多个条状凸起部与该些条状凸起部之间的多个开口部,相邻的两该条状凸起部的间距介于2.5微米至100微米。
8.一种软性面板,其特征在于,包含:
一基板,定义有一主动区、一周边电路区与一中介区,该中介区位于该主动区与该周边电路区之间;
一第一绝缘层,位于该基板上的该主动区、该周边电路区与该中介区,其中该第一绝缘层于该中介区具有一第一图形;
一第二绝缘层,位于该第一绝缘层上,该第二绝缘层于该中介区具有一第一开口沿一第一方向延伸,使得该第二绝缘层未覆盖该第一绝缘层的该第一图形;
一晶体管结构,位于该第二绝缘层上且位于该主动区中,该晶体管结构具有一栅极、一通道层、一漏极与一源极;
一金属走线层,延伸于该主动区与该周边电路区之间,于该主动区中与该周边电路区中该金属走线层位于该第二绝缘层上方,并于该主动区中电性连接该晶体管结构,于该中介区中该金属走线层经由该第一开口而接触该第一绝缘层的该第一图形;以及
一牺牲层,位于该中介区的该第一绝缘层与该第二绝缘层之间,且该牺牲层于该中介区未覆盖该第一绝缘层的该第一图形。
9.如权利要求8所述的软性面板,其特征在于,该金属走线层于该中介区覆盖具有该第一图形的该第一绝缘层。
10.如权利要求8所述的软性面板,其特征在于,该第一图形沿一第二方向延伸,该第二方向与该第一方向正交,且该第二方向为指由该主动区往该周边电路区的一方向。
11.如权利要求8所述的软性面板,其特征在于,该第一图形具有至少一凸起部,该金属走线层于该中介区具有一第二图形位于该至少一凸起部上。
12.如权利要求8所述的软性面板,其特征在于,该第一图形为一条纹图形。
13.如权利要求12所述的软性面板,其特征在于,该条纹图形具有多个条状凸起部与该些条状凸起部之间的多个开口部,相邻的两该条状凸起部的间距介于2.5微米至100微米。
14.一种软性面板制作方法,其特征在于,包含:
设置一第一绝缘层于一基板上,该基板具有一主动区、一周边电路区以及介于该主动区与该周边电路区间的一中介区;
设置一牺牲层于该第一绝缘层上对应于该基板的该中介区处,该牺牲层具有一图形;
设置一第二绝缘层,覆盖该第一绝缘层与该牺牲层;
图形化该第二绝缘层,使该第二绝缘层于该中介区具有一开口暴露出部分该第一绝缘层与部分该牺牲层;
图形化该第一绝缘层;以及
蚀刻该牺牲层暴露的部分;
其中,于图形化该第二绝缘层与图形化该第一绝缘层的步骤中,该牺牲层的一第一蚀刻率小于对该第二绝缘层的一第二蚀刻率,且该牺牲层的该第一蚀刻率小于对该第一绝缘层的一第三蚀刻率。
15.如权利要求14所述的方法,其特征在于,该第二蚀刻率与该第一蚀刻率的比例介于3倍至50倍,且该第三蚀刻率与该第一蚀刻率的比例介于3倍至50倍。
16.如权利要求14所述的方法,其特征在于,于图形化该第一绝缘层的步骤包含以该牺牲层为掩膜蚀刻该第一绝缘层。
17.如权利要求14所述的方法,其特征在于,该牺牲层的该图形为一条纹图形,该条纹图形为沿着从该主动区往该周边电路区的方向延伸。
18.如权利要求14所述的方法,其特征在于,更包含于该第二绝缘层上方设置一金属走线层。
19.如权利要求18所述的方法,其特征在于,该金属走线层为由该主动区、该中介区往该周边电路区设置,且于该中介区中使该金属走线层经由该开口而接触经图形化的该第一绝缘层。
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