CN107123689A - A kind of high pressure PIN diode structure and preparation method thereof - Google Patents
A kind of high pressure PIN diode structure and preparation method thereof Download PDFInfo
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- CN107123689A CN107123689A CN201710175036.7A CN201710175036A CN107123689A CN 107123689 A CN107123689 A CN 107123689A CN 201710175036 A CN201710175036 A CN 201710175036A CN 107123689 A CN107123689 A CN 107123689A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 230000036961 partial effect Effects 0.000 claims description 3
- 229910017435 S2 In Inorganic materials 0.000 claims 2
- 229910052738 indium Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 16
- 238000011084 recovery Methods 0.000 abstract description 4
- 230000002441 reversible effect Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000002829 reductive effect Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 26
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of high pressure PIN diode structure and preparation method thereof, the doping column with the second conduction type is formed in the semiconductor layer with the first conduction type by sectional doped technique, it is equal pressure-resistant so as to be realized under thinner epitaxial thickness, while forward conduction voltage drop is reduced, more preferably reverse recovery characteristic is obtained；Simultaneously can be by adjusting the concentration and width of superjunction region p-type and N-type, to adjust the injection efficiency of PN junction, and extra hole is provided, with very high Di/Dt reversely restoring process, hole can be injected to avoid the unstable dynamic avalanche on N/N+ borders, and then obtain more high robust.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of high pressure PIN diode structure and its preparation side
Method.
Background technology
PIN-type diode be between P areas and N areas generate low-doped n type impurity I type floor, by control its thickness with
Doping concentration obtains conduction voltage drop and Reverse recovery is special come the voltage required for obtaining, and by the introducing of lifetime control techniques
Property compromise high-voltage fast recovery.
At present, the method for preparing high pressure PIN diode structure is generally：Extension and substrate doping one on a silicon substrate first
The epitaxial layer with the first conduction type caused, its concentration is about in 1E13cm-3~5E14cm-3, then in the front note of epitaxial layer
Enter the ions with second conduction type different from substrate, afterwards deposited oxide layer, in active area using photoetching in positive and negative
Pattern is formed, and removes the oxide layer in the region, so that metal is contacted, finally in front deposit metal and reverse side deposit metal,
Form anode and negative electrode；However, the high pressure PIN diode structure epitaxial thickness formed in this way is thicker, and positive guide
Logical pressure drop is high, and Reverse recovery performance is bad, and can not obtain higher robustness, and these are all those skilled in the art institute not phases
See.
The content of the invention
For above-mentioned problem, the invention discloses a kind of high pressure PIN diode structure, including：
Substrate with the first conduction type, is provided with front and the back side relative with the front；
Semiconductor layer with the first conduction type, is arranged in the front of the substrate, and the semiconductor and is formed with
Some doping columns with the second conduction type；
Epitaxial layer with the first conduction type, is arranged at the semiconductor layer；
Doped layer with the second conduction type, is arranged on the epitaxial layer；
Anode, is arranged at the upper surface of the doped layer；And
Negative electrode, is arranged at the back side of the substrate.
Above-mentioned high pressure PIN diode structure, wherein, first conduction type is N-type conduction type, and described second
Conduction type is P-type conduction type；Or
First conduction type is P-type conduction type, and second conduction type is N-type conduction type.
Above-mentioned high pressure PIN diode structure, wherein, the ion concentration of the first conduction type is in the semiconductor layer
1E15cm-3~1E16cm-3。
Above-mentioned high pressure PIN diode structure, wherein, the thickness of the semiconductor layer is 10~40um.
Above-mentioned high pressure PIN diode structure, wherein, in the doping column, the ion concentration of the second conduction type is
1E15cm-3~1E16cm-3。
Above-mentioned high pressure PIN diode structure, wherein, in the epitaxial layer, the ion concentration of the first conduction type is
1E13cm-3~5E14cm-3。
The invention discloses a kind of preparation method of high pressure PIN diode structure, comprise the following steps：
Step S1 is there is provided the substrate that one has the first conduction type, and the substrate has front and relative with the front
The back side；
Step S2, in the front of the substrate, growth multilayer has the semiconductor of the first conduction type successively from bottom to top
Layer, and after every layer of semiconductor layer is formed, and then to this layer of ion of the semiconductor layer injection with the second conduction type, with
The doped region with the second conduction type is formed in this layer of semiconductor layer, wherein, any two layers neighbouring semiconductor layer
Formed in doped region correspond and coincide with the upper and lower；
Step S3, the semiconductor layer formation for having the first conduction type in the multilayer has the first conduction type
Epitaxial layer；
Step S4, carries out ion implantation technology, with the top of the epitaxial layer formed with second conduction type from
Sub- injection region；And
Step S5, forms anode, and the back side of the substrate in first conduction type on the ion implanted region
Form negative electrode.
The preparation method of above-mentioned high pressure PIN diode structure, wherein, first conduction type is N-type conduction type,
And second conduction type is P-type conduction type；Or
First conduction type is P-type conduction type, and second conduction type is N-type conduction type.
The preparation method of above-mentioned high pressure PIN diode structure, wherein, in the step S2, in the semiconductor layer,
The ion concentration of first conduction type is 1E15cm-3~1E16cm-3。
The preparation method of above-mentioned high pressure PIN diode structure, wherein, in the step S2, every layer of semiconductor
The thickness of layer is 3~6um.
The preparation method of above-mentioned high pressure PIN diode structure, wherein, in the step S2, the doping column
Highly it is 10~40um.
The preparation method of above-mentioned high pressure PIN diode structure, wherein, in the step S2, in the doping column, the
The ion concentration of two conduction types is 1E15cm-3~1E16cm-3。
The preparation method of above-mentioned high pressure PIN diode structure, wherein, in the step S3, in the epitaxial layer, the
The ion concentration of one conduction type is 1E13cm-3~5E14cm-3。
The preparation method of above-mentioned high pressure PIN diode structure, wherein, the step S5 includes：
Step S51, oxide layer is formed in the front of the Semiconductor substrate；
Step S52, oxide layer described in partial etching is so that the upper surface of the doped region positioned at active area to be exposed；
Step S53, respectively at the front and back deposited metal of the substrate, and in removing after part metals, forms institute
State anode and the negative electrode.
Foregoing invention has the following advantages that or beneficial effect：
The invention discloses a kind of high pressure PIN diode structure and preparation method thereof, by sectional doped technique in tool
Have and the doping column (the floating superjunction at the back side) with the second conduction type is formed in the semiconductor layer of the first conduction type, so that
It can be realized under thinner epitaxial thickness equal pressure-resistant, while forward conduction voltage drop is reduced, obtain more preferably reversely extensive
Multiple characteristic；To adjust the injection efficiency of PN junction, and it can be carried by adjusting the concentration and width of superjunction region p-type and N-type simultaneously
For extra hole, N-/N+ borders are avoided not so that hole in very high Di/Dt reversely restoring process, can be injected
Stable dynamic avalanche, and then obtain more high robust.
Brief description of the drawings
By reading the detailed description made with reference to the following drawings to non-limiting example, the present invention and its feature, outside
Shape and advantage will become more apparent.Identical mark indicates identical part in whole accompanying drawings.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is show the purport of the present invention.
Fig. 1 is the structural representation of mesohigh PIN diode structure of the embodiment of the present invention；
Fig. 2 is the method flow diagram of preparation high pressure PIN diode structure in the embodiment of the present invention；
Fig. 3~11 are the method flow structural representations of preparation high pressure PIN diode structure in the embodiment of the present invention.
Embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
Embodiment one
As shown in figure 1, the present embodiment is related to a kind of high pressure PIN diode structure, specifically, the high pressure PIN diode knot
Structure includes the substrate 101 with the first conduction type, the semiconductor layer 102 with the first conduction type, with the first conductive-type
The epitaxial layer 104 of type, the doped layer 105 with the second conduction type, anode 106 and negative electrode 107；Specifically, should have the
The substrate 101 of one conduction type, is provided with front and the back side relative with front；Semiconductor layer with the first conduction type
102 are arranged at some doping columns 103 with the second conduction type are formed with the front of substrate 101, and the semiconductor, excellent
Choosing, it is parallel to each other between some doping columns 103；Epitaxial layer 104 with the first conduction type is arranged at semiconductor layer 102
On；Doped layer 105 with the second conduction type is arranged on epitaxial layer 104；Anode 106 is arranged at doped layer 105
Upper surface；And negative electrode 107 is arranged at the back side of substrate 101, it is preferred that the material that anode 106 and negative electrode 107 are used is
Metal.
In a preferred embodiment of the invention, above-mentioned first conduction type is N-type conduction type, and the second conductive-type
Type is P-type conduction type；Or first conduction type be P-type conduction type, and the second conduction type be N-type conduction type.
In a preferred embodiment of the invention, the ion concentration of first conduction type is in above-mentioned semiconductor layer 102
1E15cm-3~1E16cm-3。
In a preferred embodiment of the invention, the thickness of above-mentioned semiconductor layer 102 for 10~40um (such as 10um,
20um, 25um or 40um), and in an embodiment of the present invention, height and the semiconductor layer 102 of above-mentioned doping column 103
Thickness is identical, and is parallel to each other between some doping columns 103.
In a preferred embodiment of the invention, in above-mentioned doping column 103, the ion concentration of the second conduction type is
1E15cm-3~1E16cm-3。
In a preferred embodiment of the invention, in above-mentioned epitaxial layer 104, the ion concentration of the first conduction type is
1E13cm-3~5E14cm-3。
Embodiment two
As shown in Fig. 2 the invention discloses a kind of preparation method of high pressure PIN diode structure, specifically, this method bag
Include following steps：
Step S1 has 201, the 201 of the first conduction type to have front and the back side relative with front there is provided one, preferably
, this 201 can be silicon 201；Structure as shown in Figure 3.
Step S2, the front semiconductor layer that growth multilayer has the first conduction type successively from bottom to top in 201 (is partly led
Body structure sheaf 202), and after every layer of semiconductor layer is formed, and then there is the second conductive-type to this layer of semiconductor layer injection
The ion of type, to form the doped region with the second conduction type in this layer of semiconductor layer, wherein, any two layers is neighbouring
Semiconductor layer formed in doped region correspond and coincide with the upper and lower, the structure as shown in Fig. 4~8.
Specifically, forming one in 201 front first has the semiconductor layer 2021 of the first conduction type, the semiconductor layer
2021 thickness is 3~6um or so (such as 3um, 4.5um, 5um or 6um), structure as shown in Figure 4；And then, in
Photoetching process is carried out on the semiconductor layer 2021, then using photoetching process, injection figure is formed, then in the semiconductor layer
The adulterate ion of the second inconsistent conduction type of injection and substrate 201 has to be formed in the semiconductor layer 2021 in 2021
The doped region 2031 of second conduction type, and the height of the doped region 2031 of second conduction type is equal to the semiconductor layer 2021
Thickness, i.e. the doped region 2031 of the second conduction type is disposed through in semiconductor layer 2021, structure as shown in Figure 5；So
It is 3~6um or so and the semiconductor layer 2022 with the first conduction type, structure as shown in Figure 6 to continuously form thickness afterwards；It
Continue at afterwards and the doped region 2032 with the second conduction type is formed in the semiconductor layer, structure as shown in Figure 7 is repeatedly above-mentioned
The process of semiconductor layer and doped region is formed, the semiconductor structure 202 that is made up of multi-lager semiconductor layer is ultimately formed and by multilayer
The doping column that doped region is constituted；And the height of the doping column 203 about 10um~40um (such as 10um, 20um, 25um or
40um), typically, since the height of the doped region in every layer of semiconductor layer is identical with the thickness of this layer of semiconductor, then mix
The height of miscellaneous column 203 is identical with the thickness of semiconductor structure 202.
In a preferred embodiment of the invention, in above-mentioned multi-lager semiconductor layer, the ion concentration of the first conduction type
(this ion concentration refers to the ion concentration of the first conduction type in multi-lager semiconductor layer) is 1E15cm-3~1E16cm-3。
In a preferred embodiment of the invention, in above-mentioned doping column 203, the ion concentration of the second conduction type
(this ion concentration refers to the ion concentration of the second conduction type in doping column 203 in static state) is 1E15cm-3~1E16cm-3。
Step S3, the semiconductor layer formation for having the first conduction type in above-mentioned multilayer has the first conduction type
Epitaxial layer 204, structure as shown in Figure 9.
In a preferred embodiment of the invention, in above-mentioned epitaxial layer 204, ion concentration (this of the first conduction type
Ion concentration refers to the ion concentration of the first conduction type in epitaxial layer 204 in static state) it is 1E13cm-3~5E14cm-3。
Step S4, carries out ion implantation technology, is noted with forming the ion with the second conduction type in the top of doped layer
Enter area 205, structure as shown in Figure 10.
Step S5, forms anode 206 on above-mentioned ion implanted region 205, and in 201 back side of the first conduction type
Form negative electrode 207, structure as shown in figure 11.
In a preferred embodiment of the invention, above-mentioned steps S5 is specifically included：
Step S51, oxide layer is formed in the front of semiconductor 201.
Step S52, partial etching oxide layer so that the upper surface of the ion implanted region 205 positioned at active area to be exposed,
In order to which metal is contacted；
Step S53, respectively at 201 front and back deposited metal, and in removing after part metals, forms above-mentioned anode
206 and negative electrode 207.
In a preferred embodiment of the invention, the first conduction type is N-type conduction type, and the second conduction type is
P-type conduction type；Or
First conduction type is P-type conduction type, and the second conduction type is N-type conduction type.
It is seen that, the present embodiment is the embodiment of the method corresponding with the embodiment of above-mentioned high pressure PIN diode structure,
The present embodiment can work in coordination implementation with the embodiment of above-mentioned high pressure PIN diode structure.Above-mentioned high pressure PIN diode structure
The relevant technical details mentioned in embodiment are still effective in the present embodiment, in order to reduce repetition, repeat no more here.Accordingly
The relevant technical details mentioned in ground, the present embodiment are also applicable in the embodiment of above-mentioned high pressure PIN diode structure.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be with
Change case is realized, be will not be described here.Such change case has no effect on the substantive content of the present invention, will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this has no effect on the substantive content of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modifications, equivalents, and modifications made for any of the above embodiments
In the range of technical scheme protection.
Claims (14)
1. a kind of high pressure PIN diode structure, it is characterised in that including：
Substrate with the first conduction type, is provided with front and the back side relative with the front；
Semiconductor layer with the first conduction type, be arranged in the front of the substrate, and the semiconductor be formed with it is some
Doping column with the second conduction type；
Epitaxial layer with the first conduction type, is arranged at the semiconductor layer；
Doped layer with the second conduction type, is arranged on the epitaxial layer；
Anode, is arranged at the upper surface of the doped layer；And
Negative electrode, is arranged at the back side of the substrate.
2. high pressure PIN diode structure as claimed in claim 1, it is characterised in that first conduction type is that N-type is conductive
Type, and second conduction type is P-type conduction type；Or
First conduction type is P-type conduction type, and second conduction type is N-type conduction type.
3. high pressure PIN diode structure as claimed in claim 1, it is characterised in that the first conductive-type in the semiconductor layer
The ion concentration of type is 1E15cm-3~1E16cm-3。
4. high pressure PIN diode structure as claimed in claim 1, it is characterised in that the thickness of the semiconductor layer is 10~
40um。
5. high pressure PIN diode structure as claimed in claim 1, it is characterised in that in the doping column, the second conductive-type
The ion concentration of type is 1E15cm-3~1E16cm-3。
6. high pressure PIN diode structure as claimed in claim 1, it is characterised in that in the epitaxial layer, the first conduction type
Ion concentration be 1E13cm-3~5E14cm-3。
7. a kind of preparation method of high pressure PIN diode structure, it is characterised in that comprise the following steps：
Step S1 has front and the back of the body relative with the front there is provided the substrate that one has the first conduction type, the substrate
Face；
Step S2, in the front of the substrate, growth multilayer has the semiconductor layer of the first conduction type successively from bottom to top, and
After every layer of semiconductor layer is formed, and then to this layer of ion of the semiconductor layer injection with the second conduction type, with this
The doped region with the second conduction type is formed in layer semiconductor layer, wherein, institute in any two layers neighbouring semiconductor layer
The doped region of formation is corresponded and coincided with the upper and lower；
Step S3, has extension of the semiconductor layer formation with the first conduction type of the first conduction type in the multilayer
Layer；
Step S4, carries out ion implantation technology, is noted with forming the ion with the second conduction type in the top of the epitaxial layer
Enter area；And
Step S5, forms anode on the ion implanted region, and the back side of the substrate in first conduction type is formed
Negative electrode.
8. the preparation method of high pressure PIN diode structure as claimed in claim 7, it is characterised in that first conductive-type
Type is N-type conduction type, and second conduction type is P-type conduction type；Or
First conduction type is P-type conduction type, and second conduction type is N-type conduction type.
9. the preparation method of high pressure PIN diode structure as claimed in claim 7, it is characterised in that in the step S2,
In the semiconductor layer, the ion concentration of the first conduction type is 1E15cm-3~1E16cm-3。
10. the preparation method of high pressure PIN diode structure as claimed in claim 7, it is characterised in that in the step S2
In, the thickness of every layer of semiconductor layer is 3~6um.
11. the preparation method of high pressure PIN diode structure as claimed in claim 7, it is characterised in that in the step S2
In, the height of the doping column is 10~40um.
12. the preparation method of high pressure PIN diode structure as claimed in claim 7, it is characterised in that in the step S2,
In the doping column, the ion concentration of the second conduction type is 1E15cm-3~1E16cm-3。
13. the preparation method of high pressure PIN diode structure as claimed in claim 7, it is characterised in that in the step S3
In, in the epitaxial layer, the ion concentration of the first conduction type is 1E13cm-3~5E14cm-3。
14. the preparation method of high pressure PIN diode structure as claimed in claim 7, it is characterised in that the step S5 bags
Include：
Step S51, oxide layer is formed in the front of the Semiconductor substrate；
Step S52, oxide layer described in partial etching is so that the upper surface of the doped region positioned at active area to be exposed；
Step S53, respectively at the front and back deposited metal of the substrate, and in removing after part metals, forms the sun
Pole and the negative electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710175036.7A CN107123689A (en) | 2017-03-22 | 2017-03-22 | A kind of high pressure PIN diode structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710175036.7A CN107123689A (en) | 2017-03-22 | 2017-03-22 | A kind of high pressure PIN diode structure and preparation method thereof |
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|---|---|
| CN107123689A true CN107123689A (en) | 2017-09-01 |
Family
ID=59718128
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|---|---|---|---|
| CN201710175036.7A Pending CN107123689A (en) | 2017-03-22 | 2017-03-22 | A kind of high pressure PIN diode structure and preparation method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010147182A (en) * | 2008-12-17 | 2010-07-01 | Sumitomo Electric Ind Ltd | Method of manufacturing epitaxial wafer and method of manufacturing semiconductor device |
| CN102414805A (en) * | 2009-05-28 | 2012-04-11 | 丰田自动车株式会社 | Method for producing diode, and diode |
| CN104134609A (en) * | 2013-05-03 | 2014-11-05 | 无锡华润微电子有限公司 | Semiconductor device with multi-layer epitaxial super junction framework, and manufacturing method of semiconductor device |
-
2017
- 2017-03-22 CN CN201710175036.7A patent/CN107123689A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010147182A (en) * | 2008-12-17 | 2010-07-01 | Sumitomo Electric Ind Ltd | Method of manufacturing epitaxial wafer and method of manufacturing semiconductor device |
| CN102414805A (en) * | 2009-05-28 | 2012-04-11 | 丰田自动车株式会社 | Method for producing diode, and diode |
| CN104134609A (en) * | 2013-05-03 | 2014-11-05 | 无锡华润微电子有限公司 | Semiconductor device with multi-layer epitaxial super junction framework, and manufacturing method of semiconductor device |
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