JP2002246609A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown strength semiconductor device having a guard ring structure in which avalanche resistance is derived to the maximum by setting a reach of a depletion layer. SOLUTION: When an avalanche breakdown voltage is applied to a PN junction comprising a P type guard ring 4 and an N- layer 13a, a depletion layer 15 extending from the junction plane of the PN junction to the N- layer 13a side reaches an auto-doping layer 13b. In the example shown on Fig. 1, the depletion layer 15 intrudes into the auto-doping layer 13b but does not reach an N+ type silicon substrate 2 under avalanche breakdown voltage and a part of an epitaxial layer 13 exists between the depletion layer 15 and the N+ type silicon substrate 2. More specifically, the depletion layer 15 and the N+ type silicon substrate 2 do not touch each other but are separated from each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a guard ring structure used as a breakdown voltage maintaining structure.

[0002]

2. Description of the Related Art A guard ring structure is known as a breakdown voltage maintaining structure of a semiconductor device. Generally, a guard ring is
In order to prevent electric field concentration in the depletion layer due to the geometrical shape around the junction, it refers to a structure in which the internal junction is surrounded by a diode having a breakdown voltage higher than its breakdown voltage. This ensures the stable operation of. The guard ring structure includes a Schottky barrier diode (hereinafter, referred to as SBD) utilizing a rectifying action of a Schottky junction between a metal layer and a semiconductor layer, other fast recovery diodes (FRD), and a power supply MO.
It is also used in SFETs. The SBD has the advantage that the potential barrier is low and the forward voltage drop is small as compared with the PN junction diode, but has the disadvantage that the withstand voltage is low and the reverse characteristics are poor. Therefore, in the SBD, a guard ring is provided around the Schottky junction to limit the leakage current of the Schottky junction and increase the resistance to the reverse voltage. Conventionally, in an SBD having a guard ring structure, various proposals have been made to improve characteristics with respect to a reverse voltage.

Japanese Patent Application Laid-Open No. 58-58774 discloses an SB having a structure in which a depletion layer of a guard ring reaches a semiconductor substrate before a Schottky barrier causes breakdown.
D (conventional example 1) is disclosed. According to this publication, the SBD of Conventional Example 1 prevents the breakdown of the Schottky barrier by causing the depletion layer of the guard ring to reach the semiconductor substrate and setting the PN junction to a conductive state, and thus the breakdown of the Schottky barrier. It is said to prevent thermal destruction by heat. On the other hand, JP-A-10-17320
No. 5 discloses an SBD (hereinafter referred to as Conventional Example 2)
Surface concentration of impurity in the guard ring diffusion layer is 5 × 10 ¹⁷ /
By setting the thickness to not more than cm ^3, avalanche breakdown in the diffusion layer is less likely to occur, and the thickness of the N ⁻ epitaxial layer is set such that the depletion layer extending from the PN junction of the guard ring does not reach the silicon semiconductor substrate as the N ⁺ layer. , The energy breakdown value is increased by causing the avalanche breakdown to occur in the N ⁻ layer.

[0004] FIG. 17 shows an S structure having a structure seen in Conventional Examples 1 and 2.
1 shows BD1. As shown in FIG. 17, the SBD 1 includes an N ⁺ type silicon substrate 2 and an N ⁻ type epitaxial layer 3 formed on the N ⁺ type silicon substrate 2 by epitaxial growth.
A P-type guard ring 4 formed in the surface of the N ⁻ -type epitaxial layer 3 by diffusing in a ring shape; and an oxide film serving as a protective film having a contact opening formed on the surface of the N ⁻ -type epitaxial layer 3. 6, an electrode metal 7 serving as an anode electrode attached to the contact opening, and an electrode metal 8 serving as a cathode electrode provided on the back surface of the N ⁺ type silicon substrate 2. In Conventional Example 1, before the Schottky junction composed of the electrode metal 7 and the N ⁻ -type epitaxial layer 3 breaks down, the depletion layer 5a on the N ⁻ -type epitaxial layer 3 reaches the N ⁺ -type silicon substrate 2, It is assumed that a PN junction composed of the P-type guard ring 4 and the N ⁻ -type epitaxial layer 3 causes punch-through (reach-through) breakdown. According to such a conventional example 1,
The breakdown of the SBD 1 is caused by the destruction of the PN junction having a steep breakdown waveform, and the breakdown by the Schottky barrier having the slow breakdown waveform does not occur. According to the conventional example 2, the depletion layer 5b extending to the N ⁻ -type epitaxial layer 3 when the reverse maximum voltage is applied is not in contact with the N ⁺ -type silicon substrate 2, and the destruction due to avalanche breakdown is reduced to the N ⁻ -type epitaxial layer. It is said that the energy destruction value was increased by raising the energy in the layer 3.

In the strong reverse bias mode, the P-type region forming the P-type guard ring 4 and the N ⁻ -type epitaxial layer 3 form a PN junction, so that the P-type guard ring 4 is closer to the N ⁻ -type epitaxial layer 3. Depletion layer 4 extending to
However, due to the influence of the curvature of the guard ring outer corners 9 and 9, it does not extend sufficiently at the portion indicated by the line BB ′,
The width of the depletion layer 5 in this portion is reduced. As a result, the electric field strength E at the outer corner portions 9 and 9 of the guard ring becomes extremely high, and carrier generation G is locally concentrated at the outer corner portions 9 and 9 of the guard ring under the influence of the strong electric field. It is assumed that the carrier generation G is obtained by Expression (1).

(Equation 1) Here, Jn is an electron current, Jp is a hole current, αn and α
p is the ionization coefficient, and q is the elementary charge. As shown in FIG. 18, among the carrier pairs locally generated in the outer corner portions 9 of the guard ring, electrons e1... Are attracted and absorbed by the cathode electrode K, but positively attracted to the anode electrode A. The holes h1... Have a higher concentration distribution as the impurity concentration distribution of the P-type guard ring 4 is closer to the surface thereof, so that the hole current Jp is attracted to the surface side below the oxide film 6 and the path is indicated by arrows C. As shown in FIG. 7B, it passes right below the oxide film 6 to reach the contact opening end 11. Therefore, the oxide film 6
The hole current Jp at the position immediately below is locally concentrated, and the hole current Jp
Since the density of GaN reached an enormous value, the device could be destroyed.

[0006]

The above prior art has the following problems.

(1) A pn junction having a low impurity concentration, that is, a high specific resistance has a wide depletion layer. This is because the carriers in the semiconductor are reduced by lowering the impurity concentration, so that the depletion layer tends to spread over a relatively wide range in an attempt to capture the carriers from a wide range and store space charges. Further, in a pn junction having a low impurity concentration, the depletion layer is widened, resulting in avalanche multiplication due to a wide high electric field region. That is, avalanche mode breakdown occurs. (2) The breakdown of the pn junction is caused by the maximum electric field Emax in the depletion region.
Occurs when the critical electric field Ecrit is reached, is a general theory that is in good agreement with the experimental results. (3) Therefore, the maximum electric field E with respect to the electric field distribution area
The lower the max is, the larger the electric field distribution area becomes, and then the maximum electric field Emax reaches the critical electric field Ecrit. Therefore, the breakdown voltage corresponding to the electric field distribution area at that time is higher. (4) In order to lower the maximum electric field Emax with respect to the electric field distribution area, the depletion layer needs to be spread widely. (5) In order to widen the depletion layer, the impurity concentration may be reduced. (6) If the thickness of the N ⁻ -type epitaxial layer is infinite, the lower the impurity concentration, the higher the breakdown voltage. However, when the N ⁻ type epitaxial layer is finite, the breakdown voltage is limited by reach-through. When reach-through occurs, the thinner the N ⁻ -type epitaxial layer, the lower the reach-through at a relatively low voltage and the lower the breakdown voltage. (7) N ^- -type for breakdown voltage by a layer thickness and the like of the epitaxial layer is different, a constant thickness epitaxial layer, the device structure having a guard ring of a constant depth and impurity concentration, N ^- ratio type epitaxial layer Consider the optimum value of the resistance ρ. (8) In Conventional Example 1, the depletion layer is N ⁺ at a relatively low reverse voltage.
The breakdown voltage reaches the substrate and is limited by the reach-through. That is, since the spread of the depletion layer is limited by the reach-through, the increase in the applied voltage is used to increase the electric field strength, and the maximum electric field reaches the critical electric field and breaks down at a relatively low voltage. Therefore, there is a problem that it is difficult to obtain a high avalanche withstand voltage since breakdown occurs at a relatively low voltage. (9) In Conventional Example 2, the specific resistance is set to 1 Ω · cm, and the N ⁻ -type epitaxial layer has such a thickness that the depletion layer does not reach the N ⁺ -type silicon substrate when a reverse voltage is applied. In other words, for a device structure having a constant thickness of the epitaxial layer and a constant depth and impurity concentration of the guard ring, the specific resistance is set low so that the depletion layer does not reach the N ⁺ substrate when a reverse voltage is applied. is there. When the specific resistance is set low and the depletion layer does not spread widely, the electric field intensity increases, and the maximum electric field reaches the critical electric field at a relatively low reverse voltage. Therefore, there is a problem that it is difficult to obtain a high avalanche withstand voltage since breakdown occurs at a relatively low voltage. Further, Conventional Example 2 has a problem that it is not an effective solution because there is no clear standard as to how much the depletion layer should be separated from the semiconductor substrate or not. Further, N ^- -type epitaxial layer to increase the impurity concentration, i.e., the lower the specific resistance [rho, loss causes an increase of the product V _F · I _R of the forward voltage V _F and the reverse leakage current I _R is larger Problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art. In a semiconductor device having a guard ring structure, a high withstand voltage in which avalanche withstand capability is maximized by setting the degree of attainment of a depletion layer. It is an object of the present invention to provide a semiconductor device.

[0009]

In order to solve the above-mentioned problems, a semiconductor device according to the first aspect of the present invention is, for example, as shown in FIG.
A semiconductor device in which a first conductivity type epitaxial layer 13 having a relatively low impurity concentration is laminated thereon, and a second conductivity type region 4 having a conductivity type opposite to the first conductivity type is formed in a surface portion of the epitaxial layer 13. 10, the second conductivity type region 4 and the first conductivity type region 13a of the epitaxial layer 13
When an avalanche breakdown voltage is applied to the PN junction, the depletion layer 15 extending from the junction surface of the PN junction toward the first conductivity type region 13a causes impurities from the semiconductor substrate 2 to the epitaxial layer 13. The depletion layer 1 reaches the auto-doping layer 13b formed by diffusion.
Between the semiconductor substrate 2 and the epitaxial layer 1
3 is interposed.

In view of the problems of Conventional Examples 1 and 2 described above, two contradictory conditions that the depletion layer is sufficiently expanded in the epitaxial layer and that the breakdown voltage is not limited by the reach-through of the depletion layer are considered. At the intersection that satisfies, there is an optimum value at which the avalanche breakdown voltage is the highest.

According to the first aspect of the present invention, the P-type semiconductor device includes a second conductivity type region and a first conductivity type region of the epitaxial layer.
When an avalanche breakdown voltage is applied to the N-junction, the depletion layer extending toward the first conductivity type region reaches an auto-doping layer formed by diffusing impurities from the semiconductor substrate to the epitaxial layer. Therefore, the depletion layer can be sufficiently spread in the epitaxial layer, and the maximum electric field is lower for the same reverse voltage than when the depletion layer does not reach the auto-doping layer (for example, Conventional Example 2). The breakdown voltage increases. According to the first aspect of the present invention,
When the avalanche breakdown voltage is applied, a part of the epitaxial layer intervenes between the depletion layer and the semiconductor substrate. Therefore, as compared with the case where the depletion layer reaches the semiconductor substrate (for example, Conventional Example 1), the limitation of the breakdown voltage due to the reach-through of the depletion layer is smaller. According to the first aspect of the present invention based on the above theory, the breakdown occurs at a relatively high voltage, so that there is an effect that a high avalanche resistance can be obtained. Further, a depletion layer in comparison with the case does not reach the auto-doped layer (e.g., the conventional example 2), because of the high specific resistance [rho, the product V _F · I _R of the forward voltage V _F and the reverse leakage current I _R And the loss can be kept relatively low.

Here, the auto-doping layer refers to the following range in a region where impurities in the semiconductor substrate have advanced to the epitaxial layer. That is, when the concentration distribution curve in the direction perpendicular to the substrate after the completion of the device is traced from the position of the semiconductor substrate (2) to the epitaxial layer (13) side (for example, as shown in FIGS. 2 to 4 or 10), At the inflection point (G). The tangent (H) of the impurity concentration distribution curve passing through the inflection point (G) and the concentration Cf of the external doping impurity on the surface of the epitaxial layer. The range from the position indicated by the intersection (I) with the straight line parallel to the horizontal axis indicating the value to the semiconductor substrate (2) is the auto-doping layer. This autodoping layer is formed by redistribution of impurities in the semiconductor substrate during epitaxial growth and during subsequent high-temperature heat treatment. Then, the impurity concentration of the auto-doping layer is determined by the total concentration of the impurity mixed from the outside during the epitaxial growth and the impurity that has entered the epitaxial layer from the semiconductor substrate by diffusion.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the second conductivity type region is formed in a ring shape, and an internal junction is formed at a position surrounded by the second conductivity type region. When the avalanche breakdown voltage is applied,
A part of the epitaxial layer 13 is interposed between the depletion layer 15 extending from the internal junction to the first conductivity type region side and the auto-doping layer 13b, or the depletion layer 15 is Contact with

Here, "contact" means that the end of the depletion layer coincides with the interface between the autodoping layer and the first conductivity type region of the epitaxial layer. "Internal bonding"
Corresponds to a Schottky junction or a PN junction. Therefore, according to the second aspect of the present invention, when an avalanche breakdown voltage is applied to the PN junction formed by the second conductivity type region and the first conductivity type region of the epitaxial layer, the pn junction is moved from the internal junction to the first conductivity type region side. Since part of the epitaxial layer is interposed between the extended depletion layer and the auto-doping layer, or until the depletion layer contacts the auto-doping layer,
The depletion layer extending from the internal junction to the first conductivity type region does not enter the auto-doping layer, that is, the internal junction is not limited by the breakdown voltage due to reach-through. Therefore, SBD, FRD, FE surrounded by guard ring
There is an advantage that the reverse voltage characteristic of a semiconductor element such as T is not impaired.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the second conductivity type region is provided.
The impurity concentration Cs on the surface is 1 × 10 ¹⁷ or more and 1 × 10 ¹⁸
(1 / cm ³ ) or less.

Therefore, according to the third aspect of the present invention,
The impurity concentration on the surface of the second conductivity type region is 1 × 10¹⁷(1 /
cm^Three) Or more, sufficient ohmic contact
And the second conductivity type area table
The impurity concentration on the surface is 1 × 10 ¹⁸(1 / cm^Three)
Therefore, local concentration of hole current on the surface of the second conductivity type region is reduced.
Can be avoided.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The following is one embodiment of the present invention and does not limit the present invention.

[First Embodiment] First, a first embodiment of the present invention will be described.
The embodiment will be described with reference to FIG. FIG. 1 shows a semiconductor device (SBD10) according to a first embodiment of the present invention.
FIG.

As shown in FIG. 1, the SBD 1 of this embodiment
Reference numeral 0 denotes an N ⁺ type silicon substrate 2, an epitaxial layer 13 formed on the N ⁺ type silicon substrate 2 by epitaxial growth, and a P type guard ring 4 formed by diffusing in a ring shape on a surface portion of the epitaxial layer 13. And an oxide film 6 having a contact opening formed on the surface of the epitaxial layer 13, an electrode metal 7 serving as an anode electrode attached to the contact opening, and provided on the back surface of the N ⁺ type silicon substrate 2. And an electrode metal 8 serving as a cathode electrode.

The N ⁺ type silicon substrate 2 is formed by adding phosphorus to silicon,
N ⁺ containing a high concentration of impurities such as arsenic or antimony
Type semiconductor.

The epitaxial layer 13 is a silicon layer formed by epitaxial growth, and is a semiconductor containing the same impurities as the N ⁺ type silicon substrate 2 at a low concentration. The layer thickness of the epitaxial layer 13 is represented by d-Ep. Epitaxial layer 13 is divided into N ⁻ layer 13a, autodoping layer 13b, and P-type guard ring 4.

As described above, during the epitaxial growth and during the subsequent high-temperature heat treatment, the impurities in the N ⁺ -type silicon substrate 2
3 is a semiconductor region within a certain range of the region that has advanced to 3.
The layer thickness of the auto-doping layer 13b is represented by d-AD.

The N ^- layer 13a is an auto-doping layer 13
b-type N ^- type semiconductor. The P-type guard ring 4 is a P-type semiconductor formed by injecting and diffusing, for example, boron ions into the surface of the epitaxial layer 13 by an ion implantation method. The P-type guard ring 4 and the N ⁻ layer 13a form a PN junction. The depth of the P-type guard ring 4 is represented by X-jp. The impurity concentration on the surface of the P-type guard ring 4 is 1 × 10 ¹⁷ or more and 1 × 10 ^17
18 (1 / cm ³ ) or less. This is to ensure a sufficient ohmic contact property and to prevent local concentration of hole current on the surface of the P-type guard ring 4.

The oxide film 6 is made of a silicon oxide film having an opening pattern covering the outer peripheral edge of the P-type guard ring 4 exposed on the surface of the epitaxial layer 13, and has a role of an insulating film and a protective film.

The electrode metal 7 is an anode-side electrode,
A Schottky junction is formed with the epitaxial layer 13.
The electrode metal 8 is a cathode-side electrode.

The SBD 10 of this embodiment is different from the above-described conventional examples 1 and 2 in the degree of reaching the depletion layer 15 when a reverse voltage is applied. That is, in the SBD 10 of the present embodiment, P
When an avalanche breakdown voltage is applied to the PN junction comprising the guard ring 4 and the N ⁻ layer 13a, the depletion layer 15 extending from the junction surface of the PN junction to the N ⁻ layer 13a reaches the autodoping layer 13b. are doing. In the example shown in FIG. 1, the depletion layer 15 is
b. However, the depletion layer 15 does not reach the N ⁺ type silicon substrate 2 under the avalanche breakdown voltage, and a part of the epitaxial layer 13 is interposed between the depletion layer 15 and the N ⁺ type silicon substrate 2. That is, depletion layer 1
5 and the N ⁺ type silicon substrate 2 are not in contact with each other and are separated.

The reach of the depletion layer 15 as described above depends on the thickness d-Ep of the epitaxial layer 13 and the P-type guard ring 4.
X-jp, impurity concentration of P-type guard ring 4, N
^- it can be realized by the selection of the specific resistance ρ of the layer 13a. One of the specific methods is as follows. The thickness d of the epitaxial layer 13 depends on the rated voltage.
Defined -ep, P-type deep X-uk of the guard ring 4, an appropriate value of the impurity concentration of the P-type guard ring 4, N ^- layer 13
Simulations are performed on several structures having different specific resistances ρ of “a”, and an impurity concentration distribution curve of a guard ring portion (line A1-A2 in FIG. 1) is obtained for each structure. 2 to 4 show examples of density distribution curves, which will be described below with reference to FIGS. 2 to 4 show respective concentration distribution curves of structures A, B, and C having three different types of specific resistances ρ. Structure A,
The specific resistance ρ was set so as to decrease in the order of B and C. FIG. 2 shows the concentration distribution curve of the structure A having the highest specific resistance value, and FIG. 3 shows the concentration distribution curve of the structure B having a lower specific resistance value than the structure A. The concentration distribution curve of Structure C is shown in FIG.
As shown at the top of the graph, from the left P-type guard ring 4, N
^The -layer 13a, the auto-doping layer 13b, and the N ⁺ -type silicon substrate 2 correspond in this order.

Next, the auto-doping layer 13b for each structure is specified as follows. As shown in FIGS. 2 to 4, when the concentration distribution curve is traced from the position of the N ⁺ type silicon substrate 2 to the epitaxial layer 13 side, the decreasing rate gradually increases and reaches the inflection point G. A tangent line H of the impurity concentration distribution curve passing through the point G is drawn. An intersection point between the tangent line H and a straight line parallel to the horizontal axis indicating the value of the concentration Cf of the externally doped impurity on the epitaxial layer surface is defined as an intersection point I. A straight line J passing through the intersection I and perpendicular to the horizontal axis is drawn. Epitaxial layer 13
Of these, the portion on the right side of the straight line J on the graph is the auto-doping layer 13b.

FIG. 5 shows a standard for determining the thickness d-Ep of the epitaxial layer 13 based on the rated voltage. FIG.
According to the table shown in (a) or the graph shown in (b), N ⁻ according to the Absolute Maximum Rating withstand voltage Vamr.
The impurity concentration Nd of the layer 13a is specified, and Vamr and Nd
And the thickness d-AD of the auto-doping layer 13b is substituted into the following equation (2).

(Equation 2) Alternatively, Vamr is substituted into the following expression (3) as an approximate expression.

(Equation 3) The layer thickness d-Ep of the epitaxial layer 13 is calculated from the substituted equation. Note that the value of d-Ep is calculated by using the table in FIG.
The relationship between amr and d-Ep is shown in the graph of FIG.

On the other hand, an electric field distribution curve of the A1-A2 line when an avalanche breakdown voltage is applied is obtained. FIG. 6 shows electric field distribution curves of structures A, B, and C when an avalanche breakdown voltage is applied. Since the depletion layer 15 is a charged region, its width is indicated by the width of a region surrounded by each electric field distribution curve and a straight line with zero electric field intensity. Therefore, as can be seen from FIG. 6, the depletion layer 15 of each of the structures A, B, and C
Have reached the autodoping layer 13b. Further, the depletion layers 15 of the structures A and B surely penetrate into the auto-doping layer 13b. Auto doping layer 13b and N
^- The structure in the vicinity of the boundary between the layers 13a A, the electric field distribution curve B is refracted is therefore. However, the structure A, B, C of the depletion layer 15 does not reach the N ⁺ -type silicon substrate 2, a portion of the epitaxial layer 13 is interposed between the depletion layer 15 and the N ⁺ -type silicon substrate 2. If the depletion layer 15 does not reach the auto-doping layer 13b or the depletion layer 15 reaches the N ⁺ -type silicon substrate 2, it is excluded as described above. New structures A, B, and C are selected.

To select a structure having a higher withstand voltage among the structures A, B and C, the structure B is selected. As shown in FIG. 6, the maximum electric field Em2-A of the structure A and the maximum electric field E of the structure B
Comparing the maximum electric field Em2-C of m2-B and the structure C,
This is because the maximum electric field Em2-B of the structure B is the lowest.

Next, the relationship between the maximum electric field and the reach of the depletion layer will be described with reference to FIGS. FIG. 7 shows electric field distribution curves of structures A, B, and C when a rated voltage is applied. As shown in FIG. 7, when a rated voltage is applied, the maximum electric field of each structure is the maximum electric field Em1-A of the structure A and the maximum electric field of the structure B.
And the maximum electric field Em1-B of the structure C becomes higher in this order. This is because the expanded region of the depletion layer 15 is smaller in the structure B than in the structure A, and is smaller in the structure C than in the structure B (=
This is because the depletion layer is difficult to spread), which causes an increase in the electric field strength. On the other hand, the depletion layers 15 of the structures A and B slightly penetrate the auto-doping layer 13b, and are beginning to be restricted by reach-through. As shown in FIG. 6, when the avalanche breakdown voltage is applied higher than when the rated voltage is applied, the spread of the depletion layer 15 is limited by the reach-through, so that the maximum electric field of the structure A rises most and then the structure B In FIG. 6, the maximum electric field increases when the voltage changes from the rated voltage to the avalanche breakdown voltage. This is because the depletion layer 15
This is because the spread of the depletion layer is more limited in the structure B than in the structure C and the structure A is more difficult to spread in the structure A than in the structure B.

From the above, it can be seen that before the depletion layer 15 reaches the auto-doping layer 13b, the maximum electric field of the structure in which the depletion layer 15 is wider tends to be lower, and the breakdown voltage becomes higher. . Also, when the depletion layer 15 enters the auto-doping layer 13b to some extent, the tendency is reversed, and it can be seen that the maximum electric field of the structure in which the depletion layer 15 is wider tends to be higher, and the breakdown voltage is lower. Therefore, at the reversal point of the tendency, the maximum electric field becomes minimum, and the specific resistance ρ at which the state is obtained is the optimum value. The structure B is the structure closest to the optimum value among the structures A, B, and C. Therefore,
As described above, by configuring the device structure, it is possible to reliably configure a highly durable device structure including the optimum value.

Next, the distribution of the electric field at the Schottky junction and the spread of the depletion layer will be described. FIG. 8 shows electric field distribution curves of the Schottky junction (C1-C2 line in FIG. 1) and the guard ring portion (A1-A2 line in FIG. 1) of each of the structures A, B, and C when an avalanche breakdown voltage is applied.

As shown in FIG. 8, in all of the structures A, B, and C, the maximum electric field at the Schottky junction is larger than the maximum electric field at the guard ring. In the structure C, the epitaxial layer 13 is located between the depletion layer 15 extending from the Schottky junction to the N ⁻ layer 13a and the auto-doping layer 13b.
Is interposed. In the structure B, the depletion layer 15 extending to the N ⁻ layer 13a immediately below the Schottky junction is in contact with the auto-doping layer 13b. Here, “contact” means that the end of the depletion layer 15 is in contact with the auto-doping layer 13 b and the N ⁻ layer 1.
It means that it coincides with the interface with 3a. According to the device structures such as the structures B and C, the depletion layer 15 does not penetrate into the auto-doping layer 13b, so that the Schottky junction is not restricted by the breakdown voltage due to the reach-through.
The reverse voltage characteristics of the SBD 10 are not impaired.

When the avalanche breakdown voltage is applied, the value obtained by subtracting the maximum electric field generated at the PN junction of the guard ring portion from the maximum electric field generated at the Schottky junction (referred to as Em-SG) is 0.20. × 10 ⁵ or more,
It is recommended that the setting be 0.25 × 10 ⁵ (V / cm) or less. As another criterion, the ratio of Em-SG to the maximum electric field of the PN junction of the guard ring portion when an avalanche breakdown voltage is applied (Rm-SG).
Is recommended to be set to 0.075 or more and 0.1 or less. Em-SG is 0.20 × 10 ⁵ (V /
cm) or Rm-SG of less than 0.075, the depletion layer 15 immediately below the Schottky junction is likely to expand, penetrating into the auto-doping layer 13b and damaging the reverse voltage characteristics of the SBD 10. . On the other hand, Em
-SG exceeds 0.25 × 10 ⁵ (V / cm) or R
When m-SG is more than 0.1, the maximum electric field of the Schottky junction is likely to be large, so that the breakdown at the Schottky junction is apt to occur, and the withstand amount of the SBD 10 may be reduced and the practicality may be poor. Because.

[0037]

Next, an example performed by the inventor of the present invention according to the first embodiment will be described. The inventor of the present application has proposed a 100V / 5A SBD under five different conditions.
Settings were made by two-dimensional two-carrier (hole and electron) numerical simulations, each device structure was prototyped based on the simulation results, and various characteristics of the completed device were measured. In addition, the inventor of the present application evaluated the avalanche withstand capability of each device structure by a single-shot EAS (Single Pulse Avalanche Energy) test, and confirmed the effects of the present invention.

[0038]

[Table 1] Table 1 summarizes the experimental conditions and results for the five structures L, M, N, S, and T. In Table 1, the vertical item No. 11 is the layer thickness d-Ep of the epitaxial layer 13. The vertical item No. 12 is the specific resistance ρ of the N ⁻ layer 13a.
The vertical item No. 13 is the impurity concentration Nd of the N ⁻ layer 13a.
Vertical item No. 21 indicates the depth of P-type guard ring 4 as X-jp.
The vertical item No. 22 is P at the time of simulation design.
This is the depth X-jp of the mold guard ring 4. Vertical item No.2
Reference numeral 3 denotes a boron dose amount of the P-type guard ring 4. The vertical item No. 24 is the impurity surface concentration Cs of the P-type guard ring 4.
It is. The vertical item No. 31 is avalanche breakdown voltage V-AVB
And the reverse voltage under the condition that the reverse current I _R = 400 (μA) and the junction temperature Tj = 25 ° C. Vertical item
No. 32 is the avalanche breakdown voltage V-AVB at the time of simulation. Vertical item No.33 the actual value of the forward voltage drop V _F, vertical items No.34 the actual value of the reverse leakage current I _R, the vertical item No.35 is their product. Vertical item No.36
Is an actually measured value of the reverse recovery time trr. The vertical item No. 37 is the avalanche withstand capability by the single-shot EAS test. Vertical item
No. 41 is a voltage shared by the P-type guard ring 4 in the avalanche breakdown voltage V-AVB. The vertical item No. 42 is a voltage shared by the N ⁻ layer 13 a of the avalanche breakdown voltage V-AVB. The vertical item No. 43 is the maximum electric field of the guard ring portion when the rated voltage of 100 V is applied. Vertical item No.44
Is the maximum electric field of the guard ring portion when the avalanche breakdown voltage V-AVB is applied. The vertical item No. 45 is a difference between the maximum electric field when the rated voltage of 100 V is applied to the guard ring portion and the maximum electric field when the avalanche breakdown voltage V-AVB is applied. Vertical item N
O.51 is the maximum electric field at the Schottky junction when the avalanche breakdown voltage V-AVB is applied. Vertical item No.61, 62
Is the current density of the hole current Jp near the guard ring opening end 11, No. 61 is the current density when the rated voltage of 100 V is applied, and No. 62 is the current density when the avalanche breakdown voltage V-AVB is applied.

As shown in Table 1, the thickness d-Ep of the epitaxial layer 13 was 12 in all the structures.
(Μm), for the structures L, M, and N, the depth X-jp of the P-type guard ring 4 is 3.0 (μm), the boron dose is 4 × 10 ¹³ (1 / cm ² ), and the surface concentration is 2
× 10 ¹⁷ (1 / cm ³ ), the specific resistance ρ = 2.8,
It was changed to 2.5, 2.0 (Ω · cm). Structure S, T
About the depth X-jp of the P-type guard ring 4 is 2.5
(Μm), and the boron dose amount is 1 × 10 ¹³ (1 / cm)
² ), with the surface concentration being 5 × 10 ¹⁶ (1 / cm ³ ),
The specific resistance was changed to ρ = 2.5, 2.0 (Ω · cm).

The impurity concentration of the guard ring portion (line A1-A2 in FIG. 1) of the structure M was measured by the SR (spreading resistance: spreading resistance) method, and the measured values are graphed in FIG. The result is shown in FIG. In FIG. 10, a curve F1 is an impurity concentration curve of a substrate in which the epitaxial layer 13 is formed on the N ⁺ type silicon substrate 2, and an auto-doping layer 13b1 is formed by redistribution during epitaxial growth. A curve F2 is an impurity concentration curve after the completion of the device, in which the P-type guard ring 4 is formed by diffusion, and the auto-doping layer 13b1 is shifted due to the influence of redistribution during the device forming process involving heat treatment. An auto doping layer 13b is formed. As described in the first embodiment, the final auto-doping layer 13 is formed.
When b was specified, the layer thickness was about 3.5 (μm).

Next, a single-shot EAS (Single Pulse Avalanche Energy) performed on each of the structures L, M, N, S, and T
The test will be described. FIG. 11A shows a one-shot EAS measurement circuit diagram, and FIG. 11B shows a waveform diagram of a voltage applied to the test device. The one-shot EAS test is one of test methods in which a high-voltage pulse signal is applied to a test device in a single shot to evaluate the device's capability in an avalanche mode. As shown in FIG. 11, each structure L,
M, N, S, T are connected. ON signal pulse 72
When applied to the gate of SFET 73, MOSFET 73
Is turned on, and the current I-DS flows from the power supply 74 of the voltage V-DD. Thereby, energy is continuously stored in the coil 75. When the MOSFET 73 is turned off when the current I-DS rises and reaches a predetermined I-AV, the current I-D
Since S cannot flow through the MOSFET 73, S
After the voltage rise of dv / dt, a high voltage BV-DSS that lasts for ta period is generated at both ends of the BD 71. At this time, S
Avalanche energy E-SA loaded on BD71
Is represented by the following equation (4).

(Equation 4)

As shown in equation (4), the avalanche energy E-SA can be controlled by the inductance of the coil 75 and the energy storage time. If a high avalanche energy is applied, the SBD 71 is broken and cannot stop the current. The tolerance of the test device (SBD 71) in the avalanche mode can be evaluated based on the magnitude of the avalanche energy that the SBD 71 can support. Each structure L, M, N, S, T
Table 1 shows the avalanche immunity of a single-shot EAS test.
(Vertical item No. 37) As shown in the structure M and the structure S, a high avalanche resistance was obtained.

FIG. 12 is a graph for comparing the avalanche withstand capability of each structure by a single EAS test. The horizontal axis represents the impurity concentration of the N ⁻ layer 13a. On the graph of FIG.
Points L1, M1, N1, S1, and T1 are plots of the avalanche withstand capability of the structures L, M, N, S, and T in a single-shot EAS test, respectively.
2, S2, and T2 are, in order, the structures L, M, N, S,
V _F · I _R product of T is obtained by plotting. The values are shown in Table 1. As shown in FIG. 12, the point N1 → M1
When attention is paid to the change in the avalanche resistance, the impurity concentration becomes lower, that is, as the range of the depletion layer becomes wider. Focusing on the change from point M1 to L1,
The avalanche withstand capability decreases as the impurity concentration decreases, that is, as the range covered by the depletion layer increases. On the other hand, as V _F · I _R product is enhanced impurity concentration, elevated, larger property loss. From that viewpoint, assuming that the structure M has the optimum specific resistance ρ, the point M
It is better to select the left side of 1.

FIG. 13 is a graph showing the maximum electric field of each structure. On the graph of FIG. 13, points L3, M3, N3, S3, T
3 sequentially plots the maximum electric field of the guard ring portion when the avalanche breakdown voltage V-AVB of the structures L, M, N, S, and T is applied, and points L4, M4, N4, S
4 and T4 respectively plot the maximum electric field of the guard ring portion when the rated voltage of 100 V is applied to the structures L, M, N, S, and T, respectively. The values are shown in Table 1.
As shown in FIG. 13, when a rated voltage of 100 V is applied,
The maximum electric field becomes higher in the order of L4 → M4 → N4. This is because the enlarged area of the depletion layer 15 is smaller in the structure M than in the structure L and in the structure N than in the structure M (= the depletion layer is hard to spread).
This is because the electric field strength increases. Rated voltage 100
If the applied voltage increases from V to the avalanche breakdown voltage,
Since the spread of the depletion layer 15 is limited by the reach-through, the maximum electric field of the structure L is increased most (point L4 →
Then, the structure M rises greatly (change from point M4 to point M3). This is because the extent of the depletion layer 15 is limited by the reach-through, and the structure M is more difficult to spread than the structure N and the structure L is more difficult to spread than the structure M. Therefore, the increase in the applied voltage is used to increase the electric field strength. This is because the. As a result, the maximum electric field of the structure M became minimum when the avalanche breakdown voltage was applied. The structure M is a structure in which the maximum electric field when an avalanche breakdown voltage is applied can be minimized, and the avalanche withstand capability can be increased.

As described above, local concentration of the hole current Jp (see FIG. 18) can be cited as a cause of device destruction.
For the structures L, M, and N, the hole current Jp near the contact opening end on the surface of the P-type guard ring 4 was measured. The values are as shown in the column 1 No. 61 and 62 in Table 1 above. Avalanche breakdown voltage V-AVB shown in vertical item No. 62
FIG. 14 is a graph showing the current density at the time of application. From these results, it can be confirmed that the structure M has the lowest hole current Jp current density.

According to the above fact, the structure M can suppress the maximum electric field to the lowest, and since the maximum electric field is low, the generation of the hole current Jp is suppressed, and the device destruction is caused by the local concentration of the hole current Jp. Can be suppressed, and the avalanche resistance can be said to be the largest.

As described above, when the avalanche breakdown voltage is applied to the PN junction composed of the P-type guard ring 4 and the N ⁻ layer 13a, the N-type junction is formed from the junction surface of the PN junction.
^The depletion layer 15 extending to the −layer 13a side reaches the auto-doping layer 13b, and the depletion layer 15 does not reach the N ⁺ type silicon substrate 2 but is between the depletion layer 15 and the N ⁺ type silicon substrate 2. By selecting a device structure in which a part of the epitaxial layer 13 is interposed, it is possible to reliably select a highly resistant device structure including an optimum value.

[Second Embodiment] In the first embodiment, the SBD 10 has been described as an example of the semiconductor device of the present invention. However, the present invention is not limited to this, and the SBD 20 shown in FIG. May be applied.

As shown in FIG. 15A, the SBD 20
It differs from the SBD 10 in the structure of the Schottky junction. SB
The Schottky junction of D20 is formed by forming a trench 22 in the N ^- layer 13a and partially burying the electrode metal 21. According to the SBD 20, the spread of the depletion layer 15 from the Schottky junction is equal to the spread W below the silicon outermost surface.
The width W-N2 below the trench 22 is smaller than that of -N1.
It approaches the ⁺ type silicon substrate 2. In order not to impair the reverse voltage characteristic of the SBD 20, when applying the avalanche breakdown voltage,
A part of the epitaxial layer 13 is interposed between the lowermost end of the spread W-N2 and the auto-doping layer 13b, or until the lowermost end of the spread W-N2 contacts the auto-doping layer 13b. It is preferable that the lowermost end does not enter the auto-doping layer 13b.

Third Embodiment In the first embodiment, the SBD 10 has been described as an example of the semiconductor device of the present invention. However, the present invention is not limited to this, and the SBD 30 shown in FIG. May be applied.

As shown in FIG. 15B, the SBD 30
Unlike the SBD 10, a P-type island-shaped semiconductor region 31 is formed by diffusion in the Schottky junction area (in the P-type guard ring 4) of the surface layer of the N ⁻ layer 13a. According to the SBD 30, the spread of the depletion layer 15 from the Schottky junction is
Silicon from spreading W-N1 under the outermost surface, towards the spread W-N2 under the island-shaped semiconductor region 31 is N ⁺ -type silicon substrate 2
Approach. In order not to impair the reverse voltage characteristic of the SBD 30, when the avalanche breakdown voltage is applied, a part of the epitaxial layer 13 is interposed between the lowermost end of the spread W-N2 and the auto-doping layer 13b, or the spread W-N2 It is preferable that the lowermost edge of W-N2 does not penetrate into the autodoping layer 13b until the lowermost edge thereof contacts the autodoping layer 13b.

[Fourth Embodiment] Although the above embodiment has been described using the SBD, the present invention is not limited to the SBD, and the present invention is not limited to the SBD.
It goes without saying that the present invention is similarly applicable to diodes such as D).

In this embodiment, the FRD 40 shown in FIG. 16A will be described as an example. FRD40 As shown in FIG. 16 (a) is different N and SBD10 ^- in the Schottky junction region on the layer 13a (P-type guard ring 4), N ^- semiconductor layer 41 of P-type on the layer 13a is diffused Is formed. The impurity concentration of the semiconductor layer 41 is set lower than that of the P-type guard ring 4. Such FRD
According to 40, the spread W-N2 under the semiconductor layer 41 is N ⁺
Approaching the silicon substrate 2. In order not to impair the reverse voltage characteristic of the FRD 40, when the avalanche breakdown voltage is applied, a part of the epitaxial layer 13 is interposed between the lowermost end of the spread W-N2 and the auto-doping layer 13b, or the spread W-N2 It is preferable that the lowermost edge of W-N2 does not penetrate into the autodoping layer 13b until the lowermost edge thereof contacts the autodoping layer 13b.

[Fifth Embodiment] Although the above embodiment has been described using a diode, the present invention is not limited to a diode, and a high breakdown voltage MOSFET may be used.
T and transistors and the like widely used as power switching elements of various circuits such as power supply devices,
It goes without saying that it is equally applicable.

In this embodiment, the MOSFET 50 shown in FIG. 16B will be described as an example. As shown in FIG. 16B, the MOSFET 50 has an N ⁺ type silicon substrate 2,
It is roughly composed of the N ^- layer 13a, the P-type guard ring 4, the oxide film 53, the electrode metal 55, and has three electrodes of a drain, a source, and a gate. The P-type guard ring 4 provided in the MOSFET 50 is composed of a P-type guard ring 4a and a P-type guard ring 4a.
It is formed doubly by the mold guard ring 4b. According to the MOSFET 50, the spread W-N2 below the island-shaped semiconductor region 51 is larger than the spread W-N1 below the silicon outermost surface.
Is closer to the N ⁺ type silicon substrate 2. MOSFET
In order not to impair the reverse voltage characteristics of the epitaxial layer 13 during the application of the avalanche breakdown voltage, a part of the epitaxial layer 13 is interposed between the lowermost end of the spread W-N2 and the auto-doping layer 13b, or the spread W-N2 It is preferable that the lowermost edge of W-N2 does not penetrate into the autodoping layer 13b until the lowermost edge thereof contacts the autodoping layer 13b.

In the above embodiment, a semiconductor device using an N-type semiconductor substrate has been described. However, the present invention is not limited to this, and uses a P-type semiconductor substrate of an opposite conductivity type. The present invention can also be applied to a conventional semiconductor device. In this case, the guard ring is formed by implanting N-type impurities such as phosphorus ions.

[0057]

As described above, according to the present invention, in a semiconductor device having a guard ring structure, there is no cause of cost increase such as an increase in processes and addition of materials.
There is an effect that a high breakdown voltage semiconductor device with maximum avalanche withstand capability can be obtained by setting the depletion layer reach without deteriorating characteristics in use in a range not exceeding the rated characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a concentration distribution curve of a structure A according to the first embodiment of the present invention.

FIG. 3 is a concentration distribution curve of a structure B according to the first embodiment of the present invention.

FIG. 4 is a concentration distribution curve of a structure C according to the first embodiment of the present invention.

FIG. 5 is a table (a) showing criteria for determining a layer thickness d-Ep of the epitaxial layer 13 according to the first embodiment of the present invention.
And a graph (b).

FIG. 6 shows a structure A according to the first embodiment of the present invention;
It is an electric field distribution curve at the time of avalanche breakdown voltage application of B and C.

FIG. 7 shows a structure A according to the first embodiment of the present invention;
It is an electric field distribution curve at the time of application of rated voltage of B and C.

FIG. 8 shows a structure A according to the first embodiment of the present invention.
3 is an electric field distribution curve of a Schottky junction (C1-C2 line in FIG. 1) and a guard ring portion (A1-A2 line in FIG. 1) when an avalanche breakdown voltage of B and C is applied.

FIG. 9 shows measured values of the impurity concentration of the guard ring portion (line A1-A2 in FIG. 1) of the structure M in the example of the present invention.

FIG. 10 is an impurity concentration curve of a guard ring portion (line A1-A2 in FIG. 1) of the structure M in the example of the present invention.

11A is a circuit diagram of a single-shot EAS measurement circuit, and FIG. 11B is a waveform diagram of a voltage applied to a test device, which is used in the embodiment of the present invention.

[12] structure in the embodiment of the present invention L, M, and avalanche withstand capability due to single EAS test N, is a graph of V _F · I _R product.

FIG. 13 is a graph of the maximum electric field of the structures L, M, and N according to the embodiment of the present invention.

FIG. 14 is a graph showing hole current densities of structures L, M, and N according to an example of the present invention.

FIG. 15A is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention, and FIG. 15B is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the present invention.

FIG. 16A is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment of the present invention, and FIG. 16B is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a conventional semiconductor device.

FIG. 18 is a schematic diagram for explaining a state of local concentration of hole current Jp.

[Explanation of symbols]

2 ... N ⁺ -type silicon substrate 13 ... epitaxial layer 13a ... N ^- layer 13b ... autodoping layer 4 ... P-type guard ring 5,15 ... depletion layer 6 ... oxide films 7 and 8 ... electrode metal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhiko Hayashi 1204 Soya, Hadano-shi, Kanagawa Prefecture, Japan Inter Co., Ltd. (72) Inventor Kazuhiro Nakamura 1204 Soya, Hadano-shi, Kanagawa Japan Co., Ltd. (72) Inventor Shinji Fujimoto 1204 Soya, Hadano-shi, Kanagawa F-term in Japan Inter Corporation (reference) 4M104 CC03 FF27 FF35 GG03

Claims (3)

[Claims] An epitaxial layer of a first conductivity type having a relatively low impurity concentration is laminated on a semiconductor substrate of a first conductivity type having a relatively high impurity concentration, and the first conductivity type is formed on a surface portion of the epitaxial layer. In a semiconductor device in which a second conductivity type region of the opposite conductivity type is formed, when an avalanche breakdown voltage is applied to a PN junction composed of the second conductivity type region and the first conductivity type region of the epitaxial layer, the PN A depletion layer extending from the junction surface of the junction to the first conductivity type region side,
A semiconductor which reaches an auto-doping layer formed by diffusing impurities from the semiconductor substrate to the epitaxial layer, and a part of the epitaxial layer is interposed between the depletion layer and the semiconductor substrate. apparatus. 2. The second conductivity type region is formed in an annular shape,
An internal junction is formed at a position surrounded by the PN.
When an avalanche breakdown voltage is applied to the junction, a part of the epitaxial layer is interposed between the depletion layer extending from the internal junction toward the first conductivity type region and the auto-doping layer, or the depletion is caused by the depletion. The semiconductor device according to claim 1, wherein a layer is in contact with the auto-doping layer. 3. The method according to claim 1, wherein the impurity concentration on the surface of the second conductivity type region is not less than 1 × 10 ^{17 and not} more than 1 × 10 ¹⁸ (1 / cm ³ ). Semiconductor device.