CN107122541A - One kind floating ground lotus control HP memristor equivalent circuits - Google Patents

One kind floating ground lotus control HP memristor equivalent circuits Download PDF

Info

Publication number
CN107122541A
CN107122541A CN201710278216.8A CN201710278216A CN107122541A CN 107122541 A CN107122541 A CN 107122541A CN 201710278216 A CN201710278216 A CN 201710278216A CN 107122541 A CN107122541 A CN 107122541A
Authority
CN
China
Prior art keywords
terminal
operational amplifier
memristor
resistor
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710278216.8A
Other languages
Chinese (zh)
Inventor
王将
钱辉
蒋涛
姚凯文
胡爱黄
吴平业
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changzhou University
Original Assignee
Changzhou University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changzhou University filed Critical Changzhou University
Priority to CN201710278216.8A priority Critical patent/CN107122541A/en
Publication of CN107122541A publication Critical patent/CN107122541A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/36Circuit design at the analogue level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Abstract

本发明公开了一种浮地荷控HP忆阻等效电路,电路包括运算放大器U1、运算放大器U2、乘法器U3、电流传输器U4、电流传输器U5以及电阻R1、R2、R3、R4、R5和电容C1。其中电阻R2、R3和运放U1相连构成减法运算电路;运放U2与电容C1和电阻R4相连接构成积分电路;乘法器U3用来实现乘法运算。电流传输器U4与U5相连,实现电流的镜像。本发明利用模拟电路实现了一种简化型的浮地HP忆阻的伏安特性,采用阻值较小的电阻,其结构简单,精确度高,误差小,易于实现;而且也通过改变乘法器的输入端口的连接方式可实现增量忆阻与减量忆阻的变换,也与HP忆阻特性更加符合。

The invention discloses a floating charge controlled HP memristor equivalent circuit. The circuit includes an operational amplifier U 1 , an operational amplifier U 2 , a multiplier U 3 , a current transmitter U 4 , a current transmitter U 5 , and a resistor R 1 , R 2 , R 3 , R 4 , R 5 and capacitor C 1 . Among them, resistors R 2 and R 3 are connected with operational amplifier U 1 to form a subtraction circuit; operational amplifier U 2 is connected with capacitor C 1 and resistor R 4 to form an integral circuit; multiplier U 3 is used to realize multiplication. The current transmitter U 4 is connected to U 5 to implement current mirroring. The present invention utilizes the analog circuit to realize the volt-ampere characteristic of a kind of simplified floating ground HP memristor, adopts the resistor with smaller resistance value, its structure is simple, the precision is high, the error is small, and it is easy to realize; and also by changing the multiplier The connection mode of the input port can realize the transformation of incremental memristor and decremental memristor, and it is more consistent with the characteristics of HP memristor.

Description

一种浮地荷控HP忆阻等效电路A Floating Charge Controlled HP Memristor Equivalent Circuit

技术领域technical field

本发明涉及一种HP忆阻等效电路,尤其涉及一种浮地荷控HP忆阻等效电路的设计。The invention relates to an HP memristor equivalent circuit, in particular to the design of a floating charge-controlled HP memristor equivalent circuit.

背景技术Background technique

在自然界和人类社会的各种物理系统中,普遍存在记忆效应。具有记忆效应的物理器件或系统可视为一种忆阻。忆阻(memristor)是描述电荷(charge)和磁通(magneticflux)关系的实现电路的基本组成元件。Memory effects are ubiquitous in various physical systems in nature and human society. A physical device or system with memory effect can be regarded as a kind of memristor. Memristor is the basic component of circuit that describes the relationship between charge and magnetic flux.

1971年,美国加州大学蔡少棠教授从理论上预测了忆阻元件的存在性,并且提出了忆阻器的概念。2008年,惠普实验室史特科夫等在《自然》上首次报道了忆阻器的实现性,研究成果震惊了国际电工电子技术世界。忆阻器是一种无源器件,因为其消耗能量而不产生能量,不产生功率增益,独特的记忆特性使其能够以非易失方式记忆流经电荷的总量。忆阻器除了具有记忆能力,还可以进行逻辑运算,所以忆阻器在人工智能计算机和模拟神经网络中应用更为广泛,同时也将对电子工程、通信工程等有着很深远的影响。In 1971, Professor Cai Shaotang of the University of California theoretically predicted the existence of memristive elements and proposed the concept of memristors. In 2008, Stekov of Hewlett-Packard Laboratory and others reported the realization of memristor for the first time in "Nature", and the research results shocked the international electrotechnical and electronic technology world. A memristor is a passive device because it dissipates energy rather than producing it, produces no power gain, and has unique memory properties that allow it to non-volatilely remember the total amount of charge flowing through it. In addition to its memory ability, memristors can also perform logic operations, so memristors are more widely used in artificial intelligence computers and simulated neural networks, and will also have a profound impact on electronic engineering and communication engineering.

目前因为HP TiO2忆阻采用的纳米技术,所以在具体实现和制作上有着很大的困难,并且忆阻器目前还未作为一个实际的元件走向市场,因此设计一种忆阻等效电路并用其替代实际忆阻器进行实验和应用研究是具有很大价值的。At present, due to the nanotechnology used in HP TiO 2 memristor, there are great difficulties in the specific realization and production, and the memristor has not yet entered the market as an actual component, so a memristor equivalent circuit is designed and used It is of great value to replace the actual memristor for experiment and application research.

目前虽然有不少的忆阻器等效电路已逐渐被报道,但是大都采用了阻值较大的电阻,会影响忆阻等效电路实现的精确度,结构都较为复杂,而且多以接地形式为主。本发明要解决的技术问题就是提供一种简化的浮地型HP忆阻器等效电路,电路结构简单,使用了较小阻值的电阻,精确度高,并且不受接地限制,可应用于众多实际领域中,具有研究意义与价值。At present, although many memristor equivalent circuits have been gradually reported, most of them use resistors with large resistance, which will affect the accuracy of memristor equivalent circuits. The structures are relatively complicated, and most of them are in the form of grounding. Mainly. The technical problem to be solved by the present invention is to provide a simplified floating-type HP memristor equivalent circuit, the circuit structure is simple, a resistor with a small resistance value is used, the accuracy is high, and it is not limited by grounding, and can be applied to In many practical fields, it has research significance and value.

发明内容Contents of the invention

本发明的主要目的是针对现有HP TiO2忆阻等效电路中使用了阻值较大的电阻,而且会影响忆阻特性的精确度,提供一种简化的浮地荷控HP忆阻等效电路,通过电路来模拟出忆阻器的伏安特性,其具有结构简单,电阻值较小,忆阻特性明显,误差较小,容易实现等优点。The main purpose of the present invention is to provide a simplified floating-ground charge-controlled HP memristor for the existing HP TiO2 memristor equivalent circuit that uses a resistor with a large resistance value and affects the accuracy of the memristor characteristic. The effective circuit simulates the volt-ampere characteristic of the memristor through the circuit, which has the advantages of simple structure, small resistance value, obvious memristive characteristic, small error, and easy realization.

上述目的通过下述的技术方案来实现:Above-mentioned purpose is realized by following technical scheme:

电路包括运算放大器U1、运算放大器U2、乘法器U3、电流传输器U4、电流传输器U5以及电阻R1、R2、R3、R4、R5和电容C1The circuit includes operational amplifier U 1 , operational amplifier U 2 , multiplier U 3 , current conveyor U 4 , current conveyor U 5 , resistors R 1 , R 2 , R 3 , R 4 , R 5 and capacitor C 1 .

所述电阻R1的两端标注为A和B端,电阻R2的两端标注为C和D端,电阻R3的两端标注为D和E端,电阻R4的两端标注为E和F端,电阻R5的两端标注为G和H端,电容C1的两端标注为G和H端。The two ends of the resistor R1 are marked as A and B terminals, the two ends of the resistor R2 are marked as C and D terminals, the two ends of the resistor R3 are marked as D and E terminals, and the two ends of the resistor R4 are marked as E and F terminals, the two ends of the resistor R5 are marked as G and H terminals, and the two ends of the capacitor C1 are marked as G and H terminals.

所述A端连接输入端V1,B端与电流传输器U5的Y端连接,C端与乘法器U3的W端连接,运放U1的X端与A端相连接,运放U1的Y端与D端相连接,运放U1的输出端Z与E端连接,整体构成一个减法器。The A terminal is connected to the input terminal V1, the B terminal is connected to the Y terminal of the current transmitter U5 , the C terminal is connected to the W terminal of the multiplier U3, the X terminal of the operational amplifier U1 is connected to the A terminal, and the operational amplifier U The Y terminal of 1 is connected to the D terminal, and the output terminal Z of the operational amplifier U1 is connected to the E terminal, forming a subtractor as a whole.

所述运放U2的正输入X端与A端连接,运放U2的负输入Y端与F端连接,运放U2的输出端Z端与电容C1的H端连接,电容C1的G端与运放U2的负输入Y端连接。 The positive input X terminal of the operational amplifier U2 is connected to the A terminal, the negative input Y terminal of the operational amplifier U2 is connected to the F terminal, the output terminal Z of the operational amplifier U2 is connected to the H terminal of the capacitor C1 , and the capacitor C The G terminal of 1 is connected with the negative input Y terminal of the operational amplifier U2.

所述乘法器U3的X1端与运放U1的正输入X端连接,Y1端与运放U2的输出端Z连接,X2、Y2和Z端与地连接,乘法器U3的输出端W端连接电流传输器U4的正输入端X。The X1 terminal of the multiplier U 3 is connected to the positive input X terminal of the operational amplifier U 1 , the Y1 terminal is connected to the output terminal Z of the operational amplifier U 2 , the X2, Y2 and Z terminals are connected to the ground, and the output of the multiplier U 3 The terminal W is connected to the positive input terminal X of the current transmitter U4 .

所述电流传输器U4的Z端与电流传输器U5的Z端连接,U4、U5的W端和U5的X端都与地连接,电流传输器U4的Y端连接输入端V2The Z terminal of the current transmitter U4 is connected to the Z terminal of the current transmitter U5 , the W terminals of U4 , U5 and the X terminal of U5 are all connected to the ground, and the Y terminal of the current transmitter U4 is connected to the input Terminal V 2 .

电阻R1、R2、R3和R4的阻值相等。The resistance values of the resistors R 1 , R 2 , R 3 and R 4 are equal.

本发明与现有技术相比具有以下优点:Compared with the prior art, the present invention has the following advantages:

1、本发明设计了一种简化的浮地荷控HP忆阻等效电路,不需要阻值较大的电阻,电路结构简单,也易于构建,而且使用小电阻提高忆阻等效的精确度。1. The present invention designs a simplified floating-ground charge-controlled HP memristor equivalent circuit, which does not require a resistor with a large resistance value, the circuit structure is simple, and it is easy to build, and the use of a small resistor improves the accuracy of the memristor equivalent .

2、使用一个运放和两个电阻,构造了一个简单的减法器电路,其结构简单。在构建积分电路时,在电容上并联一个阻值较大的电阻,提高了积分精度,同时也避免了电压漂移。2. Using an operational amplifier and two resistors, a simple subtractor circuit is constructed with a simple structure. When building an integrating circuit, a resistor with a larger resistance is connected in parallel to the capacitor, which improves the integration accuracy and avoids voltage drift.

3、整体忆阻等效电路的实现思路较为清晰,容易实现,经过简单变换可以分别实现增量忆阻与减量忆阻,与HP忆阻特性更加相符。3. The realization idea of the overall memristor equivalent circuit is relatively clear and easy to realize. After a simple transformation, the incremental memristor and the decremental memristor can be realized respectively, which is more consistent with the characteristics of HP memristor.

附图说明Description of drawings

为了使本发明的内容更容易被清楚的理解,下面根据的具体实施方案并结合附图,对本发明作进一步详细的说明,其中:In order to make the content of the present invention more easily understood clearly, the present invention will be further described in detail according to the specific embodiments below in conjunction with the accompanying drawings, wherein:

图1是本发明电路结构示意图。Fig. 1 is a schematic diagram of the circuit structure of the present invention.

图2是减量忆阻乘法器的连接示意图。Fig. 2 is a schematic diagram of the connection of the decremented memristive multiplier.

图3是该忆阻等效电路两输入端加正弦波时的U-I特性曲线。Fig. 3 is the U-I characteristic curve when a sine wave is applied to the two input terminals of the memristor equivalent circuit.

具体实施方式detailed description

下面结合附图和实施例对本发明作进一步说明。The present invention will be further described below in conjunction with drawings and embodiments.

本发明电路就是设计一种模拟电路实现HP TiO2忆阻模型所描述的运算。The circuit of the present invention is to design an analog circuit to realize the operation described by the HP TiO2 memristive model.

如图1所示,该等效电路包括运放U1、运放U2、电流传输器U4和U5、乘法器U3以及电阻R1、R2、R3、R4和R5、电容C1。运放U1的X端连接输入端V1,运放U1的Y端连接电阻R2的D端。根据运放的特性,VX=VY=VD=V1。电阻R2的C端连接电流传输器U4的X端,电流传输器U4的Y端连接输入端V2。根据电流传输器的特性,U4的X端电压和Y端电压相等,所以电阻R2的C端的电压为V2。因为电阻R2和R3阻值相等,所以R2和R3上的电流相等,即i2=i3。因为U1的输出端Z端连接R3的E端,所以对于运放U1端口的电压有如下关系:As shown in Figure 1, this equivalent circuit includes op amp U 1 , op amp U 2 , current conveyors U 4 and U 5 , multiplier U 3 , and resistors R 1 , R 2 , R 3 , R 4 and R 5 , Capacitor C 1 . The X terminal of the operational amplifier U1 is connected to the input terminal V1, and the Y terminal of the operational amplifier U1 is connected to the D terminal of the resistor R2. According to the characteristics of the operational amplifier, V X =V Y =V D =V 1 . The C terminal of the resistor R 2 is connected to the X terminal of the current transmitter U 4 , and the Y terminal of the current transmitter U 4 is connected to the input terminal V 2 . According to the characteristics of the current conveyor, the voltage at the X terminal of U 4 is equal to the voltage at the Y terminal, so the voltage at the C terminal of the resistor R 2 is V 2 . Because the resistance values of resistors R 2 and R 3 are equal, the currents on R 2 and R 3 are equal, that is, i 2 =i 3 . Because the output terminal Z of U 1 is connected to the E terminal of R 3 , the voltage at the port U 1 of the op amp has the following relationship:

电阻R4的E端连接运放U1的Z端,F端与运放U2的Y端连接。因为运放U2的X端与输入端V1相连,所以F端的电压等于V1。所以电阻R4上的电流i4=(vZ1–V1)/R4=(V1–V2)/R4。因为R5、C1和运放U2构成了一个积分器,所以输出端Z端的电压vZ2关系有如下表示: The E terminal of the resistor R4 is connected to the Z terminal of the operational amplifier U1, and the F terminal is connected to the Y terminal of the operational amplifier U2 . Because the X terminal of the operational amplifier U2 is connected to the input terminal V1, the voltage at the F terminal is equal to V1 . Therefore, the current i 4 on the resistor R4 =(v Z1 -V 1 )/R 4 =(V 1 -V 2 )/R 4 . Because R 5 , C 1 and operational amplifier U 2 constitute an integrator, the relationship between the voltage v Z2 at the output terminal Z is expressed as follows:

乘法器的X1端与输入端V1相连接,Y1端与运放U2的输出端Z连接,X2端、Y2端和Z端都接地,所以乘法器的输出端W的电压有如下表示:The X1 terminal of the multiplier is connected to the input terminal V1, the Y1 terminal is connected to the output terminal Z of the operational amplifier U2, and the X2 terminal, Y2 terminal and Z terminal are all grounded, so the voltage of the output terminal W of the multiplier is expressed as follows:

其中,是穿过端点1和2的磁通量。in, is the magnetic flux through endpoints 1 and 2.

电流传输器U4的X端连接乘法器U3的输出端W端,根据电流传输器的特性,所以U4的Y端的电压等于X端的电压,又因为U3的Y端与输入端V2连接,所以V2=vWThe X terminal of the current conveyor U 4 is connected to the output terminal W terminal of the multiplier U 3. According to the characteristics of the current conveyor, the voltage of the Y terminal of U 4 is equal to the voltage of the X terminal, and because the Y terminal of U 3 is connected to the input terminal V 2 connected, so V 2 =v W .

电阻R1的A端连接输入端V1,B端连接电流传输器U5的Y端,所以输入电流iin=i1=V1/R1。因为电流传输器U5的Z端与电流传输器U4的Z端连接,根据电流传输器的特性,电流传输器U5的Z端的电流等于Y端的电流,电流传输器U4的Z端的电流等于U5的Z端口的电流,所以有Terminal A of the resistor R 1 is connected to the input terminal V 1 , and terminal B is connected to the Y terminal of the current transmitter U 5 , so the input current i in =i 1 =V 1 /R 1 . Because the Z terminal of the current conveyor U5 is connected to the Z terminal of the current conveyor U4, according to the characteristics of the current conveyor, the current at the Z terminal of the current conveyor U5 is equal to the current at the Y terminal, and the current at the Z terminal of the current conveyor U4 is equal to the Z terminal of U5. port current, so there are

iin=iY5=iZ5=iZ4=iY4 (4)i in =i Y5 =i Z5 =i Z4 =i Y4 (4)

可见,流进该忆阻等效电路的电流和流出电流都为iin,实现了浮地特性;而且等效电路的端口电压v为It can be seen that the current flowing into and out of the memristor equivalent circuit are both i in , realizing the floating characteristic; and the port voltage v of the equivalent circuit is

所以该等效电路阻值为So the equivalent circuit resistance is

因为HP TiO2忆阻的基本模型为Because the basic model of HP TiO2 memristor is

M(t)=ROFF[1-kq(t)] (7)M(t)=R OFF [1-kq(t)] (7)

而此发明的等效电路的阻值可以表示为And the resistance value of the equivalent circuit of this invention can be expressed as

对比式(7)和式(8),令R1=ROFF,k=–1/10C1那么两个表达式是一致的,说明该等效电路实现了HP忆阻器的V-I特性,且为HP增量忆阻的特性。Comparing formula (7) and formula (8), if R 1 =R OFF , k=–1/10C 1 , then the two expressions are consistent, indicating that the equivalent circuit realizes the VI characteristics of the HP memristor, and is the property of the HP incremental memristor.

需要特别说明的是,k值的正负可通过根据乘法器的特性,如图2所示的接法,可实现负的k值,即实现减量忆阻特性。It should be noted that the positive or negative of the value of k can be realized by the connection method shown in FIG. 2 according to the characteristics of the multiplier, that is, the decremented memristive characteristic can be realized.

图3为在等效电路两端加入幅度为2V,频率20Hz的正弦波,得到的V-I特性曲线图,符合忆阻器的电气特性。Figure 3 is the V-I characteristic curve obtained by adding a sine wave with an amplitude of 2V and a frequency of 20Hz at both ends of the equivalent circuit, which conforms to the electrical characteristics of the memristor.

本发明设计了一种简化型的浮地HP忆阻模拟等效电路,该模拟电路仅含有两个运放、两个电流传输器、一个乘法器以及五个电阻、一个电容。电路采用小电阻,易于实现,结构简单,避免使用阻值偏大的电阻的,提高了忆阻特性的精确度。同时通过使用一个运放和两个电阻实现减法运算,结构简单,且积分精度高。同时该电路设计思路清晰,改变乘法器输入端口的连接方式可实现增量忆阻与减量忆阻的变换,也与HP忆阻特性更加符合。The present invention designs a simplified floating-ground HP memristor analog equivalent circuit, which only includes two operational amplifiers, two current transmitters, a multiplier, five resistors, and a capacitor. The circuit adopts a small resistance, which is easy to realize and has a simple structure, avoids the use of a resistance with a relatively large resistance value, and improves the accuracy of the memristive characteristic. At the same time, the subtraction operation is realized by using an operational amplifier and two resistors, which has a simple structure and high integral precision. At the same time, the design idea of the circuit is clear. Changing the connection mode of the input port of the multiplier can realize the conversion of incremental memristor and decremental memristor, which is more consistent with the characteristics of HP memristor.

上述实施例仅仅是为清楚地说明本发明所作的举例,而并非是对本发明的实施方式的限定。对于所属领域的其他技术人员来说,在上述说明的基础上还可以做出其它不同形式的变动或改进。这里无需也无法对所有的实施方式予以穷举。The above-mentioned embodiments are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those skilled in the art, other changes or improvements in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here.

Claims (3)

1.一种浮地荷控HP忆阻等效电路,其特征在于:电路包括运算放大器U1、运算放大器U2、乘法器U3、电流传输器U4、电流传输器U5以及电阻R1、R2、R3、R4、R5和电容C11. A floating-ground charge-controlled HP memristor equivalent circuit is characterized in that: the circuit includes an operational amplifier U 1 , an operational amplifier U 2 , a multiplier U 3 , a current transmitter U 4 , a current transmitter U 5 and a resistor R 1 , R 2 , R 3 , R 4 , R 5 and capacitor C 1 . 2.根据权利要求1所述的所述一种简化型浮地HP忆阻等效电路,其特征在于电阻R1的两端标注为A和B端,电阻R2的两端标注为C和D端,电阻R3的两端标注为D和E端,电阻R4的两端标注为E和F端,电阻R5和电容C1的两端都标注为G和H端。2. said a kind of simplified floating ground HP memristor equivalent circuit according to claim 1 is characterized in that the two ends of resistance R 1 are marked as A and B ends, and the two ends of resistance R 2 are marked as C and Terminal D, the two ends of resistor R3 are marked as D and E terminals, the two ends of resistor R4 are marked as E and F terminals, and the two ends of resistor R5 and capacitor C1 are marked as G and H terminals. 3.根据权利要求1或2所述的一种简化型浮地HP忆阻等效电路,所述A端连接输入端V1,B端与电流传输器U5的Y端连接,C端与乘法器U3的W端连接,运放U1的X端与A端相连接,运放U1的Y端与D端相连接,运放U1的输出端Z与E端连接,整体构成一个减法器。所述运放U2的正输入X端与A端连接,运放U2的负输入Y端与F端连接,运放U2的输出端Z端与电容C1的H端连接,电容C1的G端与运放U2的负输入Y端连接。所述乘法器U3的X1端与运放U1的正输入X端连接,Y1端与运放U2的输出端Z连接,X2、Y2和Z端与地连接,乘法器U3的输出端W端连接电流传输器U4的正输入端X。所述电流传输器U4的Z端与电流传输器U5的Z端连接,U4、U5的W端和U5的X端都与地连接,电流传输器U4的Y端连接输入端V23. A simplified floating-ground HP memristor equivalent circuit according to claim 1 or 2, the A terminal is connected to the input terminal V1, the B terminal is connected to the Y terminal of the current transmitter U5 , and the C terminal is connected to the Y terminal of the current transmitter U5. The W terminal of the multiplier U3 is connected, the X terminal of the operational amplifier U1 is connected with the A terminal, the Y terminal of the operational amplifier U1 is connected with the D terminal, and the output terminal Z of the operational amplifier U1 is connected with the E terminal, forming a whole Subtractor. The positive input X terminal of the operational amplifier U2 is connected to the A terminal, the negative input Y terminal of the operational amplifier U2 is connected to the F terminal, the output terminal Z of the operational amplifier U2 is connected to the H terminal of the capacitor C1 , and the capacitor C The G terminal of 1 is connected with the negative input Y terminal of the operational amplifier U2. The X1 terminal of the multiplier U 3 is connected to the positive input X terminal of the operational amplifier U 1 , the Y1 terminal is connected to the output terminal Z of the operational amplifier U 2 , the X2, Y2 and Z terminals are connected to the ground, and the output of the multiplier U 3 The terminal W is connected to the positive input terminal X of the current transmitter U4 . The Z terminal of the current transmitter U4 is connected to the Z terminal of the current transmitter U5 , the W terminals of U4 , U5 and the X terminal of U5 are all connected to the ground, and the Y terminal of the current transmitter U4 is connected to the input Terminal V 2 .
CN201710278216.8A 2017-04-25 2017-04-25 One kind floating ground lotus control HP memristor equivalent circuits Pending CN107122541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710278216.8A CN107122541A (en) 2017-04-25 2017-04-25 One kind floating ground lotus control HP memristor equivalent circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710278216.8A CN107122541A (en) 2017-04-25 2017-04-25 One kind floating ground lotus control HP memristor equivalent circuits

Publications (1)

Publication Number Publication Date
CN107122541A true CN107122541A (en) 2017-09-01

Family

ID=59726099

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710278216.8A Pending CN107122541A (en) 2017-04-25 2017-04-25 One kind floating ground lotus control HP memristor equivalent circuits

Country Status (1)

Country Link
CN (1) CN107122541A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107993686A (en) * 2018-01-12 2018-05-04 深圳璞芯智能科技有限公司 A kind of floatingly voltage-controlled memristor equivalence element
CN108365948A (en) * 2018-03-30 2018-08-03 湘潭大学 The memristor type hyperchaotic circuit of arbitrary even number and odd number scrollwork attractor can be generated
CN108846215A (en) * 2018-06-21 2018-11-20 成都师范学院 A kind of extremely simple floating ground lotus control memristor circuit simulation model
CN108875204A (en) * 2018-06-15 2018-11-23 成都师范学院 Sensor circuit simulation model is recalled in a kind of extremely simple floating ground lotus control
CN109344467A (en) * 2018-09-14 2019-02-15 常州大学 A Minimalist Floating HP Memristive Equivalent Circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106130713A (en) * 2016-07-14 2016-11-16 郑州轻工业学院 A kind of the simplest four-dimensional self-governing chaos system with double memristor and realize circuit
US9619596B2 (en) * 2015-06-23 2017-04-11 King Fahd University Of Petroleum And Minerals Floating memristor emulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9619596B2 (en) * 2015-06-23 2017-04-11 King Fahd University Of Petroleum And Minerals Floating memristor emulator
CN106130713A (en) * 2016-07-14 2016-11-16 郑州轻工业学院 A kind of the simplest four-dimensional self-governing chaos system with double memristor and realize circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李志军等: "一个通用的记忆器件模拟器", 《物理学报》 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107993686A (en) * 2018-01-12 2018-05-04 深圳璞芯智能科技有限公司 A kind of floatingly voltage-controlled memristor equivalence element
CN107993686B (en) * 2018-01-12 2020-09-01 深圳璞芯智能科技有限公司 Floating ground voltage control memristor equivalent element
CN108365948A (en) * 2018-03-30 2018-08-03 湘潭大学 The memristor type hyperchaotic circuit of arbitrary even number and odd number scrollwork attractor can be generated
CN108365948B (en) * 2018-03-30 2020-12-08 湘潭大学 Memristive hyperchaotic circuits capable of generating scroll attractors
CN108875204A (en) * 2018-06-15 2018-11-23 成都师范学院 Sensor circuit simulation model is recalled in a kind of extremely simple floating ground lotus control
CN108875204B (en) * 2018-06-15 2022-04-26 成都师范学院 Extremely simple floating ground load control memory sensor circuit simulation model
CN108846215A (en) * 2018-06-21 2018-11-20 成都师范学院 A kind of extremely simple floating ground lotus control memristor circuit simulation model
CN108846215B (en) * 2018-06-21 2022-04-26 成都师范学院 Extremely simple floating ground load control memristor circuit simulation model
CN109344467A (en) * 2018-09-14 2019-02-15 常州大学 A Minimalist Floating HP Memristive Equivalent Circuit

Similar Documents

Publication Publication Date Title
Chen et al. Flux–charge analysis of two-memristor-based Chua's circuit: Dimensionality decreasing model for detecting extreme multistability
CN107122541A (en) One kind floating ground lotus control HP memristor equivalent circuits
Ranjan et al. High‐frequency floating memristor emulator and its experimental results
CN103219983B (en) A kind of memristor equivalent simulation circuit
CN103531230B (en) A kind ofly recall container based on the floating of memristor and recall sensor simulator
CN109829194B (en) Absolute value magnetic control memristor equivalent simulation circuit
Mosad et al. Improved memristor-based relaxation oscillator
CN113054947B (en) A ReLU type memristor simulator
CN106202796A (en) A kind of general memory device simulator
CN103326704A (en) Magnetic control memristor equivalent circuit
CN108153943A (en) The behavior modeling method of power amplifier based on dock cycles neural network
CN109194321A (en) One kind floating ground magnetic control memristor simulator
CN108846215B (en) Extremely simple floating ground load control memristor circuit simulation model
CN113390464B (en) Resistance-variable sensing framework for coded pulse output
CN110222425A (en) A kind of equivalent simulation circuit having source domain cubic polynomial magnetic control memristor with twin part
CN110765718A (en) A binary memristor circuit simulator
CN108696274A (en) A kind of circuit model of exponential type flow control memristor
CN203909497U (en) Single neuron PID controller based on memristors
CN107017979A (en) A kind of Generation of Chaotic Signals based on broad sense memristor simulator
Mladenov Synthesis and analysis of a memristor-based artificial neuron
Li et al. Threshold‐type memristor‐based memory circuit
CN107103929B (en) Floating type HP memristor equivalent circuit with bipolar characteristic
CN206042010U (en) Mesh multi-wing chaotic circuit
CN110147597B (en) Multi-stable-state magnetic control memristor equivalent simulation circuit
CN109670221B (en) A cubic nonlinear magnetron memristive circuit composed of fractional-order capacitors

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170901