CN107112357A - 用于iiia族n装置的经热处理半导体/栅极电介质界面 - Google Patents
用于iiia族n装置的经热处理半导体/栅极电介质界面 Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
在所描述实例中，一种制作用于功率晶体管装置的栅极堆叠的方法(100)包含对衬底上的IIIA族N层的表面进行热氧化(101)以形成厚度大于5A的氧化物材料的第一电介质层。在所述第一电介质层上沉积(102)为氮化硅或氮氧化硅的第二电介质层。在所述第二电介质层上形成(104)金属栅极电极。
Description
技术领域
本发明涉及IIIA族N(例如，GaN)场效应晶体管(FET)，且更特定来说涉及此类FET的栅极堆叠。
背景技术
氮化镓(GaN)是常用IIIA族N材料，其中IIIA族元素(例如Ga、硼、铝、铟及铊)有时还称为13族元素。GaN是具有纤锌矿晶体结构的二元IIIA/V直接带隙半导体。其在室温下达到3.4eV(相对于硅的1.1eV)的相对宽带隙赋予其在光电子器件、高功率及高频率电子装置中用于多种应用的特殊性质。
基于IIIA族N的高电子迁移率晶体管(HEMT)的性能及可靠性可受其相对高栅极泄漏限制。栅极泄漏可降低击穿电压及功率附加效率，同时增加噪声指数。为帮助降低栅极泄漏问题，可将栅极电介质材料从常规SiN改变为SiON或改变为其它电介质材料，或者改变为多层栅极电介质堆叠。
发明内容
对于IIIA族N晶体管装置，当在IIIA族N材料(例如GaN或AlGaN)上使用SiN或SiON栅极电介质时可发生相对高栅极泄漏。举例来说，直接沉积于GaN上的栅极电介质可具有高界面俘获状态密度。在栅极电介质沉积之前及之后的额外热处理可帮助降低栅极泄漏以帮助实现GaN场效应晶体管(FET)的更佳性能，但在本文中认识到所述降低对于一些应用是不充足的。
在所描述实例中，制作用于功率IIIA族N晶体管装置的多层栅极电介质的方法包含对位于衬底上的IIIA族N层的表面进行热氧化以形成包含具有大于5A(埃)的厚度的氧化物材料的第一电介质层。接着在所述第一电介质层上沉积包含氮化硅或氮氧化硅的第二电介质层。接着在所述第二电介质层上形成栅极电极。
附图说明
图1是根据实例性实施例的制作用于功率IIIA族N晶体管装置的多层栅极电介质堆叠的实例性方法中的步骤的流程图。
图2A是根据实例性实施例的实例性耗尽模式HEMT功率装置的横截面图，所述耗尽模式HEMT功率装置具有位于缓冲层上的IIIA族N层上的所揭示多层栅极电介质堆叠，所述IIIA族N层为包含第二不同IIIA族N层上第一IIIA族N层的双层堆叠。
图2B是根据实例性实施例的实例性增强模式HEMT功率装置的横截面图，所述增强模式HEMT功率装置具有正常关断型栅极，所述正常关断型栅极具有位于缓冲层上的IIIA族N层上的所揭示多层栅极电介质堆叠，所述IIIA族N层展示为包含第二不同IIIA族N层上第一IIIA族N层的双层堆叠。
图3是HEMT功率晶体管的关于各种栅极电介质的以实验方式确定的栅极泄漏的绘图，所述HEMT功率晶体管包含控制装置及具有具经热处理半导体/栅极电介质界面的所揭示多层栅极电介质的装置。
具体实施方式
在本发明中，所图解说明动作或事件可以不同次序发生及/或与其它动作或事件同时发生。此外，可不需要一些所图解说明动作或事件来实施根据本发明的方法。
图1是根据实例性实施例的制作用于IIIA族N功率晶体管装置的多层栅极电介质堆叠的实例性方法100中的步骤的流程图。在典型制作过程中，通过金属有机化学气相沉积(MOCVD)在衬底上顺序地生长未掺杂缓冲层(例如，40nm未掺杂AlN缓冲层)、后续接着IIIA族N层(例如，3μm未掺杂GaN层)、后续接着充当有源层的另一IIIA族N层(例如，30nm未掺杂AlGaN层)。
步骤101包含对衬底上的IIIA族N层的表面进行热氧化以形成包含厚度大于5A的氧化物材料的第一电介质层。所述热氧化可包含在氧化环境(例如O2)中在500℃到900℃下达从30秒到30分钟的时间的快速热氧化(RTO)，或者可为在含氧气环境中在500℃到900℃下达30秒到高达1小时的时间的熔炉氧化。在一个实施例中，在从700℃到850℃的温度范围内执行RTO。
步骤101还可包含原位氧化，例如在SiN或SiN低压化学气相沉积(LPCVD，参见下文所描述的步骤102)之前使用空气或氧气环境。氧化产物通常为氧化镓(例如Ga2O3)或Ga2O3与Me2O3的合金(GaxMeyO3)，其中Me可为Al及/或In，这取决于IIIA族N层的组成。在步骤101之后栅极电介质厚度范围通常为5A到5nm，通常是1nm到2.5nm。
所述衬底可包含例如蓝宝石、硅或碳化硅(SiC)等衬底。IIIA族N层可由通式AlxGayIn1-x-yN表示，其中0≤x≤1，0≤y≤1，0≤x+y≤1。举例来说，IIIA族N层可包含GaN、InN、AlN、AlGaN、AlInN、InGaN及AlInGaN中的至少一者。可包含其它IIIA族元素(例如硼(B))，且N可部分地由磷(P)、砷(As)或锑(Sb)取代。IIIA族氮化物化合物半导体中的每一者可含有选自以下各项的任选掺杂剂：Si、C、Ge、Se、O、Fe、Mn、Mg、Ca、Be、Cd及Zn。IIIA族N层可通过包含MBE、MOCVD或HVPE的过程而形成。
步骤102包含在第一电介质层上沉积包含氮化硅或氮氧化硅的第二电介质层。可利用来自第二电介质层的硅及氮将在步骤101中形成的氧化物材料转换为SiOx或SiOxNy，所述第二电介质层为所述转换提供硅源。
步骤103包含在沉积第二电介质层(步骤102)之后(例如)通常在N2(或其它非氧化气体)中从800℃到1100℃的任选退火。
在通常通过光致抗蚀剂保护栅极区域的同时移除源极及漏极区域上的栅极电介质堆叠。接着，(例如)通过溅镀金属堆叠(例如Ti/Al/TiN)而形成欧姆触点。步骤104包含形成栅极电极，例如使用TiW合金来形成栅极电极。
可使用所揭示多层栅极电介质实施例的功率半导体装置的一个实例是HEMT。HEMT(还称作异质结构FET(HFET)或调制掺杂FET(MODFET))是在具有不同带隙的两种半导体材料之间并入结(即，异质结)以替代掺杂区域(其通常为针对金属氧化物半导体场效应晶体管(MOSFET)的情形)作为沟道的场效应晶体管。HEMT包含在沟道层中用作载子的2DEG。由于2DEG用作载子，因此HEMT具有比其它一般晶体管高的电子迁移率。HEMT包含具有宽带隙的化合物半导体。因此，HEMT可具有比其它一般晶体管大的击穿电压。HEMT的击穿电压可与包含2DEG的化合物半导体层(例如GaN层)的厚度成比例地增加。
图2A是根据实例性实施例的实例性耗尽模式HEMT功率装置200的横截面图，耗尽模式HEMT功率装置200具有位于展示为230'的IIIA族N层上的所揭示多层栅极电介质堆叠，所述IIIA族N层为包含第二不同IIIA族N层230a上第一IIIA族N层230b的实例性双层堆叠。HEMT功率装置200展示为具有所揭示多层栅极电介质堆叠，所揭示多层栅极电介质堆叠包含：第一电介质层235a，其为具有大于5A的厚度的氧化物材料；及第一电介质层235a上的第二电介质层235b，其包含氮化硅或氮氧化硅。HEMT功率装置200还具有缓冲层，所述缓冲层包含衬底210上的第一缓冲层220a及第一缓冲层220a上的第二缓冲层220b。
HEMT功率装置200可为离散装置或IC上的许多装置中的一者。第一IIIA族N层230b展示为位于第二IIIA族N层230a的一部分上。尽管将IIIA族N层230'展示为双层，但IIIA族N层230'可为仅单个层，或者三个或多于三个不同IIIA族N层。一般来说，IIIA族N层230'可包含GaN、InN、AlN、AlGaN、AlInN、InGaN及AlInGaN中的一或多者。所述IIIA族N层可包含其它IIIA族元素(例如B)，且N可部分地由P、As或Sb取代，且还可含有任选掺杂剂。在一个实例中，IIIA族N层230'包含AlxGayN层或InxAlyN层顶部上的GaN层。
HEMT功率装置200的2DEG位于IIIA族N层界面230b/230a处。在另一实施例中，IIIA族N层230'可为多于两个IIIA族N层(例如，3到4层)，其(例如)各自为具有x％及y％的不同值的AlxGayN层或InxAlyN层，其中0≤x、y≤1且x+y＝1。特定实例是为包含AlGaN上InAlN上GaN的三层堆叠的IIIA族N层230'。
HEMT功率装置200包含源极241、漏极242及栅极电极240。栅极电极240定位于源极241与漏极242之间，比起漏极242较接近于源极241。尽管将栅极电极240展示为具有包含第一电介质层235a上第二电介质层235b的将栅极电极240与第一IIIA族N层230b物理且电分离的下伏多层栅极电介质堆叠，但第一IIIA族N层230b可替代地与下伏第二IIIA-N层230a直接接触。源极241、漏极242及栅极电极240可由金属及/或金属氮化物形成，但实例性实施例不限于此。
图2B是根据实例性实施例的实例性增强模式HEMT功率装置250的横截面图，增强模式HEMT功率装置250具有正常关断型栅极，所述正常关断型栅极具有包含位于IIIA族N层上的第一电介质层235a上第二电介质层235b的所揭示多层栅极电介质堆叠，所述IIIA族N层展示为包含第二不同IIIA族N层230a上的第一IIIA族N层230b的双层堆叠。在此实施例中，所述栅极电极是与第一IIIA族N层230b直接接触的p掺杂栅极电极245。
在一些实例中，所制作测试装置是HEMT功率晶体管，所述HEMT功率晶体管具有在各种栅极电介质上的包含TiW的栅极电极层且其栅极泄漏被测试。图3是HEMT功率晶体管的关于各种栅极电介质的以实验方式确定的栅极泄漏(以安培为单位，共同在从约0.1μA(10-7安培)到1nA(10-9安培)的范围内展示)的绘图，所述HEMT功率晶体管包含控制装置及具有具经热处理半导体/栅极电介质界面的所揭示栅极电介质的装置。
所有测试装置的栅极电介质包含15nm的SiN。控制装置不具有下部电介质层(第二及第六条目)。测试装置的所揭示多层栅极电介质堆叠包含形成于用于SiN沉积的展示为“栅极熔炉”的LPCVD熔炉中的下部原位电介质层，所述“栅极熔炉”包含在氧气中处于700℃达120秒以提供约1.5nm厚的氧化镓层及在氧气中处于600℃达120秒以提供约1nm厚的氧化镓层。测试装置还包含下部电介质层，所述下部电介质层包含栅极RTO 800℃达120秒以提供约2nm厚的氧化镓层、栅极RTO 700℃达120秒以提供约1.5nm厚的氧化镓层及栅极RTO600℃达120秒以提供约1nm厚的氧化镓层。可看出具有具通过RTO 800℃达120秒而形成的栅极电介质的多层栅极电介质堆叠的测试装置展示最低栅极泄漏，其中泄漏降低大约一个(1)数量级(10x的因数)。
可使用所揭示实施例来形成可集成到用以形成各种不同装置及相关产品的各种组装流程中的半导体裸片。所述半导体裸片可在其中包含各种元件及/或在其上包含若干层(包含势垒层、电介质层、装置结构、有源元件及无源元件)，所述元件及层包含源极区域、漏极区域、位线、基极、发射极、集电极、导电线及导电通孔。此外，所述半导体裸片可由包含双极、绝缘栅极双极晶体管(IGBT)、CMOS、BiCMOS及MEMS的各种过程形成。
在所描述实施例中修改是可能的，且在权利要求书的范围内其它实施例是可能的。
Claims (16)
1.一种制作用于功率晶体管装置的栅极堆叠的方法，所述方法包括：
对衬底上的IIIA族N层的表面进行热氧化以形成包含厚度大于5A的氧化物材料的第一电介质层；
在所述第一电介质层上沉积包含氮化硅或氮氧化硅的第二电介质层；及
在所述第二电介质层上形成金属栅极电极。
2.根据权利要求1所述的方法，其中所述热氧化包含快速热氧化RTO或原位氧化，且其中所述沉积所述第二电介质层包含LPCVD。
3.根据权利要求1所述的方法，其进一步包括在所述沉积所述第二电介质层之后且在沉积用于所述形成所述金属栅极电极的金属栅极材料之前在非氧化环境中在800℃到1100℃下进行退火。
4.根据权利要求1所述的方法，其中所述氧化物材料包含GaOx、SiOx或SiOxNy。
5.根据权利要求1所述的方法，其中所述氧化物材料的厚度介于1nm与2.5nm之间。
6.根据权利要求1所述的方法，其中所述衬底包含蓝宝石、硅或碳化硅SiC。
7.根据权利要求1所述的方法，其中所述IIIA族N层包含GaN或AlGaN。
8.一种制作用于功率晶体管装置的栅极堆叠的方法，所述方法包括：
对衬底上的GaN或AlGaN层的表面进行热氧化以形成包含厚度介于1nm与2.5nm之间的氧化物材料的第一电介质层；
在所述第一电介质层上沉积包含氮化硅或氮氧化硅的第二电介质层；及
在所述第二电介质层上形成金属栅极电极。
9.根据权利要求8所述的方法，其中所述热氧化包含在700℃到850℃下进行快速热氧化RTO，且其中所述沉积所述第二电介质层包含LPCVD。
10.根据权利要求8所述的方法，其中所述氧化物材料包含GaOx、SiOx或SiOxNy。
11.根据权利要求8所述的方法，其中所述衬底包含蓝宝石、硅或碳化硅SiC。
12.一种功率晶体管装置，其包括：
衬底；
至少第一外延IIIA族N层，其位于所述衬底上，包含源极及漏极；及
栅极电极，其位于所述第一外延IIIA族N层上的多层栅极电介质堆叠上，其中所述多层栅极电介质堆叠包含：第一电介质层，其包含具有大于5A的厚度的氧化物材料；及所述第一电介质层上的第二电介质层，其包含氮化硅或氮氧化硅。
13.根据权利要求12所述的功率晶体管装置，其中所述衬底包含蓝宝石、硅或碳化硅SiC。
14.根据权利要求12所述的功率晶体管装置，其中所述氧化物材料包含GaOx、SiOx或SiOxNy。
15.根据权利要求12所述的功率晶体管装置，其中所述氧化物材料的厚度介于1nm与2.5nm之间。
16.根据权利要求12所述的功率晶体管装置，其中所述IIIA族N层包含GaN或AlGaN。
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