CN107085333B

CN107085333B - Array substrate and display panel

Info

Publication number: CN107085333B
Application number: CN201710546281.4A
Authority: CN
Inventors: 许作远; 朱桂熠
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2017-07-06
Filing date: 2017-07-06
Publication date: 2021-02-02
Anticipated expiration: 2037-07-06
Also published as: CN107085333A

Abstract

The invention provides an array substrate, which is provided with a display area and a non-display area surrounding the display area, wherein the display area is provided with a gate line and a data line, and the array substrate further comprises: a fan-out area disposed in the non-display area; at least one signal line extending in a first direction directed from the fan-out area to the display area; at least one binding terminal for binding a driving circuit; the first end of the binding terminal is electrically connected with the signal wire, and the second end of the binding terminal is electrically connected with the test terminal through a first lead; at least one signal line or at least one first lead is arranged between the binding terminals; the signal wire or the first lead in the area between the binding terminals is covered with a layer of covering electrode, and the covering electrode is electrically insulated from the signal wire or the first lead.

Description

Array substrate and display panel

Technical Field

The invention relates to the technical field of display, in particular to an array substrate and a display panel.

Background

At present, in a display panel, a driving circuit is bound with a binding terminal in a non-display area of the display panel through a driving pin of the driving circuit to realize electric connection, that is, the pin and the binding terminal are in one-to-one correspondence to realize pressing.

The binding terminals are mostly positioned in the non-display area, and related signal lines are more and the wiring is more dense in the non-display area. In the process of binding the driving circuit, because of process deviation, position fluctuation is generated between the binding terminal and the pin of the driving circuit due to the deviation. In addition, if wiring of signal wires around the binding terminal is dense, the pin position of the driving circuit is overlapped with the signal wires under the condition of process deviation, and the pins penetrate through the insulating layer under the action of force in the pressing process to be in short circuit with the signal wires, so that abnormal display is caused.

Meanwhile, because of the design problem of the binding terminal, compared with a common signal line, the binding terminal is also provided with a layer of indium tin oxide film, so that the binding terminal and the signal line are not in the same plane, and the Mura phenomenon is easily caused in the pressing process.

In order to solve the problems existing in the existing design, the distance between the signal line wiring and the adjacent binding terminal is ensured in a more used mode nowadays, and the short circuit phenomenon can be prevented under the condition of process deviation. However, as more and more signal lines are used and the demand of consumers for narrow frames is increased, the design for ensuring a certain distance has more problems.

Disclosure of Invention

In order to solve the above problems, the present invention provides an array substrate having a display area and a non-display area surrounding the display area, wherein the display area is provided with a gate line and a data line, and the array substrate further includes:

a fan-out area disposed in the non-display area;

at least one signal line extending in a first direction directed from the fan-out area to the display area;

at least one binding terminal for binding a driving circuit; the first end of the binding terminal is electrically connected with the signal wire, and the second end of the binding terminal is electrically connected with the test terminal through a first lead;

at least one signal wire or at least one lead wire is arranged between the binding terminals; the signal wires or the leads in the area between the binding terminals are covered with a layer of covering electrodes, and the electrodes are electrically insulated from the signal wires or the leads.

In another aspect, a display panel is also provided, which includes the above array substrate.

Compared with the prior art, the technical scheme of the invention has one of the following advantages: the binding terminals of the fan-out area and the signal lines are arranged on the same layer. The first end of the binding terminal is electrically connected with the signal wire, the second end of the binding terminal is electrically connected with the testing terminal through the lead wire, and the testing terminal can be used for testing whether the data wire and the like in the display area are abnormal or not. In addition, at least two of the signal lines or the leads are arranged between the two adjacent binding terminals, covering electrodes are arranged on the signal lines or the leads in the corresponding areas of the two adjacent binding terminals, and the covering electrodes are electrically insulated from the signal lines or the leads. Through setting up the cover electrode, can bind under the process variation allows the condition, bind the pin that electrode and drive circuit of terminal can produce positional deviation, and when positional deviation took place, the pin can not be because of the pressfitting and press through the insulating layer. At this time, the pin contacts the cover electrode, and the cover electrode can effectively protect the signal line or the first lead from being short-circuited.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic plan view of an array substrate according to an embodiment of the present invention;

fig. 2 is a partial schematic view of a fan-out region of an array substrate according to an embodiment of the present invention;

fig. 3 is a partial schematic view of a fan-out region of another array substrate according to an embodiment of the invention;

fig. 4 is a schematic cross-sectional view illustrating a fan-out region of an array substrate according to an embodiment of the present invention;

fig. 5 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the invention;

fig. 6 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention;

fig. 7 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;

fig. 8 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;

fig. 9 is a schematic plan view of a display panel according to an embodiment of the invention.

Detailed Description

An array substrate and a display panel of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, and it is understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The invention provides an array substrate, which is provided with a display area and a non-display area surrounding the display area,

the display area is provided with gate lines and data lines, wherein, still include:

a fan-out area disposed in the non-display area;

As shown in fig. 1, fig. 1 is a schematic plan view of an array substrate according to an embodiment of the present invention. The array substrate 1 has a display area AA and a non-display area NAA surrounding the display area AA. The display area AA is provided therein with a gate line 12 for controlling on and off of a thin film transistor in the array substrate 1, and a data line 11 for inputting a display signal to a pixel electrode in the array substrate 1. The area where the display area AA extends in the first direction X toward the non-display area NAA is provided with a fan-out area F, which is located in the non-display area NAA. As shown in the figure, the fan-out area F is located in the non-display area NAA at the short side of the array substrate.

The fan-out area F is provided with signal lines 2, and the signal lines 2 extend in the first direction X. Specifically, the first direction X is directed from the fan-out area F to the display area AA. The signal lines 2 are mainly electrically connected to the data lines 12 in the display area AA, and are used for transmitting display signals in the driving circuit 5 to the data lines 11.

In the fan-out area F, a binding terminal 23 is further disposed, as shown in fig. 2, fig. 2 is a partial schematic view of the fan-out area of the array substrate according to an embodiment of the present invention. Referring to fig. 1 and 2, the fan-out region F in the array substrate 1 is provided with at least one binding terminal 23, and the binding terminal 23 is used for binding the driving circuit 5. Specifically, the binding terminal 23 has two ends, a first end electrically connected to the signal line 2, a second end electrically connected to the first lead 6, and the first lead 6 is further electrically connected to a test terminal (not shown). The test terminal is mainly used for testing whether the signal line of the display area is short-circuited or broken.

Specifically, at least one signal line 2 or at least one first lead 6 is provided between adjacent binding terminals 23. As shown in fig. 2, taking the middle row of binding terminals 23 as an example, two signal lines 2 and one first lead 6 are provided between the first binding terminal 23 and the second binding terminal 23. In an area where the two binding terminals 23 are correspondingly disposed, for example, in an area corresponding to a long side of the two binding terminals 23 in the drawing, the signal line 2 or the first lead 6 is covered with a layer of covering electrode 7, and the covering electrode 7 is electrically insulated from the signal line 2 or the first lead 6. In the embodiment of fig. 2, in the area corresponding to the long side of the binding terminal 23, the two signal lines 2 and the first lead 6 are covered with a layer of covering electrode 7. By arranging the covering electrode 7, the situation that in the pressing process of the driving circuit, the pin of the driving circuit is pressed to the signal wire 2 or the first lead 6 due to the alignment deviation to cause the short circuit of the signal wire can be effectively prevented. The provision of the cover electrode 7 serves to protect the signal line 2 and the first lead 6.

Specifically, as shown in fig. 3, fig. 3 is a partial schematic view of a fan-out area of another array substrate according to an embodiment of the present invention, and fig. 3 specifically shows a connection relationship among a signal line 2, a first lead 7, a bonding electrode 3, a cover electrode 7, and a test terminal 4. In the fan-out region F, at least two of the signal lines 2 or the first leads 6 are adjacent to each other to constitute a signal line group, and the binding terminals 3 are disposed between the two signal line groups. For example, in the figure, between the binding terminals 3 in the first row, the signal lines 2 are grouped into two signal line groups; between the binding terminals 3 in the second row, a signal line 2 and a first lead wire 6 form a signal line group; between the third row of binding terminals 3, the first leads 6 form signal line groups two by two.

Specifically, at least three rows of binding terminals 3 are disposed in the fan-out area F along the extending direction of the first direction X. Fig. 3 shows only three rows of binding terminals 3, which may be four rows, five rows, etc., and is not limited herein. Also, two adjacent rows of binding terminals 3 are arranged to be staggered with each other, that is, the first row of binding terminals 3 and the second row of binding terminals 3 are staggered with each other, the second row of binding terminals 3 and the third row of binding terminals 3 are staggered with each other, and the first row of binding terminals 3 and the third row of binding terminals 3 are staggered with each other.

Fig. 4 is a schematic cross-sectional view of a fan-out region of an array substrate according to an embodiment of the present invention, and fig. 4 is a cross-sectional view taken along a dotted line in fig. 3. The array substrate 1 is provided with a binding terminal 3, and the binding terminal 3 and the signal line 2 are arranged on the same layer. Further, the binding terminal 3 may also be provided in the same layer as the first lead 6. The drawing exemplarily shows a case where the binding terminal 3 is disposed in the same layer as both the signal line 2 and the first lead 6. Specifically, an insulating layer 31 is arranged on one side of the binding terminal 3 away from the array substrate 1, a binding electrode 32 is arranged on one side of the insulating layer 31 away from the array substrate 1, and the binding electrode 32 and the binding terminal 3 are electrically connected through a via hole 33. Specifically, the insulating layer 31 covers the signal line 2 and the first lead 6. The setting up of insulating layer plays insulating effect on the one hand, prevents that drive circuit pressfitting in-process from contacting with signal line 2 or first lead wire 6, and on the other hand has the effect in planarization fan-out district, guarantees that a plane can be guaranteed in the fan-out district, prevents because of the uneven counterpoint deviation that causes of membranous layer structure.

Further, the bonding electrode 32 completely covers the bonding terminal 3 in a direction perpendicular to the array substrate 1. With reference to fig. 3 and 4, a plurality of via holes 32 may be disposed between the binding terminal 3 and the binding electrode 32, and the plurality of via holes 32 may better achieve electrical connection, thereby ensuring an electrical connection effect between the driving circuit and the binding terminal 3. Specifically, the cover electrode 7 and the binding electrode 32 are disposed in the same layer, which can reduce the process and the film thickness to some extent. Furthermore, the covering electrode 7 and the binding electrode 32 are on the same layer, so that the planarization of the fan-out area is better realized, the alignment in the binding process of the driving electrode is facilitated, and the Mura phenomenon caused by uneven pressing stress is prevented to a certain extent.

Fig. 5 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention, in which a display area AA of the array substrate 1 is provided with a gate line 12 (i.e., a gate electrode) and a data line 11 (i.e., one electrode of a source drain electrode), and the gate electrode and the source drain electrode form a thin film transistor switch of the display area, which is used for controlling signal input of the display area. In addition, the pixel electrode P is electrically connected to the data line 11 through the via hole, and when the thin film transistor is turned on, a display signal is transmitted to the pixel electrode P through the data line 11. The display area AA is further provided with a common electrode C, and the common electrode C receives a common signal transmitted by the driving circuit and forms an electric field with the pixel electrode P to control the rotation of the liquid crystal molecules. Specifically, the common electrode C may be located above the pixel electrode P as shown to form a Top-Com structure, or the pixel electrode P may be located above the common electrode C to form a Mid-Com structure, which is not limited herein.

Specifically, the binding electrode 3 and the signal line 2 may be disposed in the same layer as the gate line 12, and the cover electrode 7 and the binding electrode 32 may be disposed in the same layer as any one of the data line 11, the pixel electrode P, and the common electrode C. Fig. 5 exemplarily illustrates the binding electrode 32 and the cover electrode 7 disposed at the same layer as the data line 11. The cover electrode 7 multiplexes the metal of the data line layer, and plays a role in protection.

Fig. 6 is a schematic cross-sectional structure diagram of another array substrate according to an embodiment of the present invention, and fig. 6 is similar to the basic structure of fig. 5, and the similarities are not repeated, and the difference is that the binding electrode 32 and the covering electrode 7 are disposed at the same layer as the pixel electrode P, and the covering electrode 7 multiplexes the pixel electrode layer, so that a protection effect can be effectively achieved without increasing the thickness of the film layer.

Fig. 7 is a schematic cross-sectional structure diagram of another array substrate according to an embodiment of the present invention, and fig. 7 is similar to the basic structure of fig. 5, and the details of the similar structure are omitted, except that the bonding electrode 32 and the cover electrode 7 are disposed in the same layer as the common electrode C, and the cover electrode 7 multiplexes the common electrode layer, so that a protection effect can be effectively achieved without increasing the thickness of the film layer.

Specifically, in any of the above embodiments, the material covering the electrodes may be a metal or a transparent film, and may be indium tin oxide. In addition, the material of the binding electrode may also be a metal or a transparent film, in which indium tin oxide may be used.

In this embodiment, because of the existence of the covering electrode, the deviation distance that needs to be reserved because of pressfitting counterpoint accuracy problem need not be considered between the signal line or between signal line and the binding terminal. The distance between the signal lines or between the signal line and the binding terminal can be set smaller, and the pin of the drive circuit is not pressed to the signal line or the first lead due to the misalignment. The covering electrode can effectively prevent the circuit from being pressed by the pins of the driving circuit to generate short circuit.

Fig. 8 is a schematic cross-sectional view of a display panel according to an embodiment of the invention, the display panel includes an array substrate 1 and an opposite substrate 10, and the opposite substrate 10 is disposed opposite to the array substrate 1. Specifically, a liquid crystal layer is further provided between the counter substrate 10 and the array substrate 1.

Fig. 9 is a schematic plan view of a display panel according to an embodiment of the present invention, where the display panel according to the embodiment of the present invention includes the array substrate 1 according to any embodiment of the present invention, which may be a mobile phone as shown in fig. 9, or a display panel of a computer, a television, an intelligent wearable device, and the like, and this embodiment is not particularly limited thereto.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate having a display area and a non-display area surrounding the display area, the display area being provided with gate lines and data lines, wherein the array substrate further comprises:

a fan-out area disposed in the non-display area;

at least one signal line or at least one first lead is arranged between the binding terminals; a layer of covering electrode covers the signal wire or the first lead in the area between the binding terminals, and the covering electrode is electrically insulated from the signal wire or the first lead; the covering electrode is arranged in an area corresponding to the long edges of the two binding terminals, and the covering electrode and the binding terminals are arranged at intervals in the same direction;

the binding terminal, the signal line and the first lead are arranged on the same layer, and an insulating layer is arranged on one side of the binding terminal, which is far away from the array substrate;

and one side of the insulating layer, which is far away from the array substrate, is provided with a binding electrode, and the covering electrode and the binding electrode are arranged on the same layer.

2. An array substrate as claimed in claim 1, wherein at least two of said signal lines or said first leads are adjacent to each other in said fan-out region to form signal line groups, and said bonding terminals are disposed between two of said signal line groups.

3. An array substrate as claimed in claim 1, wherein the bonding electrode and the bonding terminal are electrically connected by a via.

4. An array substrate according to claim 3, wherein the insulating layer covers the signal line and the first lead.

5. An array substrate as claimed in claim 3, wherein the binding electrodes completely cover the binding terminals in a direction perpendicular to the array substrate.

6. An array substrate as claimed in claim 3, wherein the material of the bonding electrode is indium tin oxide.

7. The array substrate of claim 1, wherein the signal lines are disposed on the same layer as the gate lines.

8. An array substrate according to claim 7, wherein the array substrate further comprises a pixel electrode and a common electrode, and the cover electrode and the data line or the pixel electrode or the common electrode are disposed in the same layer.

9. An array substrate as claimed in claim 1, wherein along the first direction, at least three rows of binding terminals are disposed in the fan-out area, and two adjacent rows of binding terminals are staggered with respect to each other.

10. An array substrate according to claim 1, wherein the signal lines are electrically connected to the data lines in a one-to-one correspondence.

11. An array substrate according to claim 1, wherein the material of the cover electrode is indium tin oxide.

12. A display panel comprising an array substrate as claimed in any one of claims 1 to 11.

13. The display panel of claim 12, further comprising a counter substrate disposed opposite the array substrate.