CN108845465B - Fan-out wiring structure of display panel and manufacturing method thereof - Google Patents

Fan-out wiring structure of display panel and manufacturing method thereof Download PDF

Info

Publication number
CN108845465B
CN108845465B CN201810708953.1A CN201810708953A CN108845465B CN 108845465 B CN108845465 B CN 108845465B CN 201810708953 A CN201810708953 A CN 201810708953A CN 108845465 B CN108845465 B CN 108845465B
Authority
CN
China
Prior art keywords
fan
bonding
insulating layer
display panel
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810708953.1A
Other languages
Chinese (zh)
Other versions
CN108845465A (en
Inventor
宋利旺
徐洋
柴立
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN201810708953.1A priority Critical patent/CN108845465B/en
Priority to PCT/CN2018/113365 priority patent/WO2020006946A1/en
Publication of CN108845465A publication Critical patent/CN108845465A/en
Application granted granted Critical
Publication of CN108845465B publication Critical patent/CN108845465B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

The invention provides a fan-out routing structure of a display panel and a manufacturing method thereof. The display panel fan-out routing structure comprises: the circuit board comprises a substrate, a metal wiring layer positioned on the substrate, an insulating layer covering the metal wiring layer and the substrate, a plurality of buffer metal cushion layers which are arranged in parallel at intervals and positioned on the insulating layer, a passivation protective layer covering the insulating layer and the buffer metal cushion layers, and a plurality of conductive leads which are arranged in parallel at intervals and positioned on the passivation protective layer; the metal routing layer comprises: the wire drawing device comprises a plurality of bonding leads arranged in parallel at intervals and a plurality of fanout wires which correspond to one ends of the bonding leads one by one and are electrically connected with the bonding leads; each buffer metal pad correspondingly covers one side of one fanout line close to the bonding lead; through the arrangement of the buffer metal pad, the insulating layer can be supported, the insulating layer is prevented from being broken by pressure, the risk of short circuit of COF signal lines and fan-out lines during the position pressing of the COF signal lines is reduced, and narrow-frame display is realized.

Description

Fan-out wiring structure of display panel and manufacturing method thereof
Technical Field
The invention relates to the technical field of display, in particular to a fan-out routing structure of a display panel and a manufacturing method thereof.
Background
Liquid Crystal Display devices (L liquid Crystal displays, L CD) have many advantages such as thin body and low power consumption, and are widely used, for example, in liquid Crystal televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens or notebook computer screens, which are dominant in the field of flat panel displays.
Most of the existing liquid crystal displays in the market are Backlight liquid crystal displays, which include a liquid crystal panel and a Backlight Module (Backlight Module) L CD display device, and the working principle is that the rotation of the liquid crystal is controlled by voltage to rotate the linearly polarized light passing through the lower polarizer, and then the linearly polarized light is emitted from the upper polarizer (perpendicular to the polarization direction of the upper polarizer), so that the upper and lower polarizers and the liquid crystal box function as an optical switch.
The liquid crystal display panel is provided with an effective display area and a fan-out area. The effective display area is provided with a plurality of pixels to form a pixel array, and the fan-out area is provided with fan-out wires. Each pixel comprises a thin film transistor and a pixel electrode connected with the thin film transistor, and the thin film transistor of each pixel is electrically connected with a scanning line and a data line. Usually, the scan lines and the data lines extend from the active display area to the fan-out area, and are electrically connected to a driver ic (driver ic) through fan-out traces.
As shown in fig. 1 and 2, a conventional fan-out routing structure includes: the substrate 1, locate metal level 2 on the substrate 1, cover insulating layer 3 of substrate 1 and metal level 2 and locate many electrically conductive lead wire 401 of parallel interval arrangement on insulating layer 3, metal level 2 includes: a plurality of bonding leads (bonding leads) 201 arranged in parallel at intervals and a plurality of fanout lines (fanout)202 corresponding to and electrically connected with the bonding leads 201 one by one, respectively, each conductive lead 401 is electrically connected with one bonding lead 201 correspondingly through a connection via 31 penetrating through an insulating layer 3, electrical connection between a fan-out trace and a driver Chip is realized by pressing a Chip On Flex (COF) signal line onto the conductive lead 401 in an aligned manner, when a COF signal line 501 and the conductive lead 401 are pressed in an aligned manner, as shown in fig. 3, if the COF signal line 501 is pressed correctly according to a predetermined position, the COF signal line 501 and the conductive lead 401 can be correctly connected without causing poor short circuit, as shown in fig. 4, because a spacing between adjacent fanout lines 202 is smaller than a spacing between adjacent conductive leads 501 and a positioning error exists during pressing, an alignment deviation may occur when the COF signal line 501 and the conductive leads 401 are pressed, as shown in fig. 4, the COF signal lines 501 are shifted downward and rightward with respect to the correct position, and if the pressure is too high during the pressing process, the insulating layer 3 is broken, the COF signal lines 501 are electrically connected not only to the corresponding conductive leads 501, but also are connected to other fanout lines 202 in a staggered manner, as shown at the position B in fig. 4, the COF signal line 501 is misaligned to be connected to the other fanout line 202, causing a short circuit, eventually causing a display failure, in order to avoid the above problem, as shown in fig. 5, the prior art adds a buffer region C having a length greater than 200um between the conductive lead 401 and the fanout line 202, and at this time as shown in fig. 6, even if the COF signal lines 501 are pressed and shifted as shown in fig. 5, the COF signal lines 501 are not connected to other fanout lines 202 in a staggered manner, however, the existence of the buffer area C may cause the frame of the display panel to be widened, and this design does not meet the requirement of the current narrow-frame display.
Disclosure of Invention
The invention aims to provide a fan-out wiring structure of a display panel, which can reduce the risk of short circuit of COF signal lines and fan-out lines when the COF signal lines are in bit alignment and realize narrow-frame display.
The invention also aims to provide a manufacturing method of the fan-out wiring structure of the display panel, which can reduce the risk of short circuit of COF signal lines and fan-out lines when the COF signal lines are in line-to-line pressing and realize narrow-frame display.
In order to achieve the above object, the present invention provides a fan-out routing structure of a display panel, including: the circuit board comprises a substrate, a metal wiring layer positioned on the substrate, an insulating layer covering the metal wiring layer and the substrate, a plurality of buffer metal cushion layers which are arranged in parallel at intervals and positioned on the insulating layer, a passivation protective layer covering the insulating layer and the buffer metal cushion layers, and a plurality of conductive leads which are arranged in parallel at intervals and positioned on the passivation protective layer;
the metal routing layer comprises: the fan-out wire comprises a plurality of bonding leads arranged in parallel at intervals and a plurality of fan-out wires which correspond to the bonding leads one by one and are electrically connected with the bonding leads respectively;
each buffer metal pad correspondingly covers one side of one fanout line close to the bonding lead;
correspond each bonding lead and all be formed with the connection via hole that runs through insulating layer and passivation protective layer, each electrically conductive lead all corresponds and a bonding lead electric connection through connecting the via hole.
Optionally, the length of the buffer metal pad in the extending direction of the fanout line is 50um to 100 um.
Optionally, the buffer metal pad is in a continuous and uninterrupted flat plate shape.
Optionally, the buffer metal pad has the same pattern as the fanout line located therebelow.
Optionally, the conductive leads are used for bonding COF signal lines, and a distance from one end of each conductive lead close to the fanout line electrically connected to the bonding lead corresponding to the conductive lead is less than 80 um.
The invention also provides a manufacturing method of the fan-out routing structure of the display panel, which comprises the following steps:
step S1, providing a substrate, and forming a metal routing layer on the substrate, where the metal routing layer includes: the fan-out wire comprises a plurality of bonding leads arranged in parallel at intervals and a plurality of fan-out wires which correspond to the bonding leads one by one and are electrically connected with the bonding leads respectively;
step S2, covering an insulating layer on the metal wiring layer and the substrate;
step S3, forming a plurality of buffer metal pads arranged at intervals on the insulating layer above the fanout line, wherein each buffer metal pad correspondingly covers one side of one fanout line close to the bonding lead;
step S4, covering a passivation protection layer on the buffer metal pad and the insulating layer;
step S5, forming a connecting via hole penetrating through the insulating layer and the passivation layer corresponding to each bonding lead respectively;
and S6, forming a plurality of conductive leads arranged in parallel at intervals on the passivation protective layer above the bonding lead, wherein each conductive lead is electrically connected with one bonding lead correspondingly through a connecting through hole.
The length of the buffer metal pad in the extending direction of the fanout line is 50 um-100 um.
The buffer metal pad is in a continuous and uninterrupted flat plate shape.
The buffer metal pad has the same pattern as the fanout line positioned below the buffer metal pad.
The conductive leads are used for bonding COF signal lines, and the distance between one end of each conductive lead close to the fanout line and the fanout line electrically connected with the bonding lead corresponding to the conductive lead is less than 80 um.
The invention has the beneficial effects that: the invention provides a fan-out routing structure of a display panel, which comprises: the circuit board comprises a substrate, a metal wiring layer positioned on the substrate, an insulating layer covering the metal wiring layer and the substrate, a plurality of buffer metal cushion layers which are arranged in parallel at intervals and positioned on the insulating layer, a passivation protective layer covering the insulating layer and the buffer metal cushion layers, and a plurality of conductive leads which are arranged in parallel at intervals and positioned on the passivation protective layer; the metal routing layer comprises: the fan-out wire comprises a plurality of bonding leads arranged in parallel at intervals and a plurality of fan-out wires which correspond to the bonding leads one by one and are electrically connected with the bonding leads respectively; each buffer metal pad correspondingly covers one side of one fanout line close to the bonding lead; through the setting of buffering metal pad, can form the support to the insulating layer, prevent that the insulating layer from crushing when counterpointing the pressfitting, reduce COF signal line and the risk of fan-out line short circuit appear when the position pressfitting of COF signal line, realize narrow frame and show. The invention also provides a manufacturing method of the fan-out wiring structure of the display panel, which can reduce the risk of short circuit of the COF signal line and the fan-out line when the COF signal line is in bit alignment.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a diagram of a fan-out routing structure of a conventional display panel;
FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;
FIG. 3 is a schematic diagram illustrating a conventional fan-out routing structure of a display panel correctly laminated with COF signal lines;
FIG. 4 is a schematic diagram illustrating a conventional display panel with a fan-out routing structure and a COF signal line offset during bonding;
FIG. 5 is a schematic diagram of a conventional fan-out routing structure of a display panel with buffer areas added;
FIG. 6 is a schematic diagram of the display panel shown in FIG. 5 after the fan-out routing structure and the COF signal lines are laminated;
FIG. 7 is a diagram of a fan-out routing structure of a display panel according to a first embodiment of the present invention;
FIG. 8 is a cross-sectional view taken at D-D of FIG. 7;
FIG. 9 is a cross-sectional view taken at E-E of FIG. 7;
FIG. 10 is a diagram of a fan-out routing structure of a display panel according to a second embodiment of the present invention;
FIG. 11 is a cross-sectional view taken at F-F of FIG. 10;
FIG. 12 is a cross-sectional view taken at G-G of FIG. 10;
FIG. 13 is a diagram illustrating a fan-out routing structure of a display panel after being laminated with COF signal lines according to a first embodiment of the present invention;
FIG. 14 is a diagram illustrating a fan-out routing structure of a display panel after being laminated with COF signal lines according to a second embodiment of the present invention;
fig. 15 is a flowchart of a manufacturing method of a fan-out routing structure of a display panel according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 7 to 12, the present invention provides a fan-out routing structure of a display panel, including: the circuit board comprises a substrate 10, a metal routing layer 20 positioned on the substrate 10, an insulating layer 30 covering the metal routing layer 20 and the substrate 10, a plurality of buffer metal pad layers 41 which are arranged in parallel at intervals and positioned on the insulating layer 30, a passivation protective layer 50 covering the insulating layer 30 and the buffer metal pad layers 41, and a plurality of conductive leads 61 which are arranged in parallel at intervals and positioned on the passivation protective layer 50.
Specifically, referring to fig. 7 to 9 or fig. 10 to 12, the metal routing layer 20 includes: many parallel interval arrangement's bonding lead 21 and respectively with many bonding lead 21 one-to-one and electric connection's many fanout lines 22 correspond each bonding lead 21 and all are formed with and run through insulating layer 30 and passivation protective layer 50's connection via hole 51, each electrically conductive lead 61 all corresponds and a bonding lead 21 electric connection through connecting via hole 51.
The fan-out line 22 is used for connecting signal lines such as a scan line and a data line in a display area of the display panel, and the bonding lead 21 is used for aligning and laminating the conductive lead 61 and the COF signal line 81 to connect a driving chip, so that signals such as a scan signal and a data signal are provided to the display panel through the driving chip to drive the display panel to work.
Specifically, each buffer metal pad 41 covers a side of one fanout line 22 close to bonding wire 21.
Preferably, buffer metal pad 41 extends from the connection point of fanout line 22 and bonding wire 21 in a direction away from bonding wire 21, and the extended length range is 50um to 100 um.
Further, as shown in fig. 7, in the first embodiment of the present invention, the buffer metal pad 41 has a shape of a continuous uninterrupted flat plate, more specifically, a rectangular plate.
Further, as shown in fig. 10, in the second embodiment of the present invention, the buffer metal pad 41 has the same pattern as the fanout line 22 located therebelow, for example, the fanout line 22 in fig. 6 is a wave-shaped winding, and at this time, the buffer metal pad 41 can also be made into a wave-shaped winding.
As shown in fig. 13 and 14, the buffer metal pad 41 functions as: when the COF signal lines 81 are aligned and pressed onto the conductive leads 61, the insulating layer 30 is supported to prevent the insulating layer 30 from being broken due to an excessive pressing force during pressing, so as to ensure that the COF signal lines 81 are not broken to cause the COF signal lines 81 to be misplaced and connected to other fanout lines 22 due to the breakage of the insulating layer 30, which causes short circuit and poor display, because of the existence of the buffer metal pads 41, the probability of the insulating layer 30 being broken due to pressing is greatly reduced, and the insulating layer 30 is not broken due to pressing, so that the length of the buffer area between the conductive leads 61 and the fanout lines 22 can be correspondingly reduced to be below 80um, even no buffer area is provided, that is, the distance from one end of each conductive lead 61 close to the fanout line 22 electrically connected with the bonding lead 21 corresponding to the conductive lead 61 is less than 80um, so as to fully utilize the space of the substrate 10, and narrow-frame display is realized.
Preferably, the substrate 10 is a glass substrate, the metal wiring layer 20 and the buffer metal pad 41 are made of a combination of one or more of molybdenum, aluminum and copper, and the conductive lead 61 is made of Indium Tin Oxide (ITO).
Referring to fig. 15, the present invention further provides a method for manufacturing a fan-out routing structure of a display panel, including the following steps:
step S1, please refer to fig. 7 to 9 or fig. 10 to 12, providing a substrate 10, and forming a metal routing layer 20 on the substrate 10, wherein the metal routing layer 20 includes: a plurality of bonding leads 21 arranged in parallel at intervals, and a plurality of fanout lines 22 respectively corresponding to the plurality of bonding leads 21 one by one and electrically connected to the plurality of bonding leads.
Specifically, the step S1 specifically includes depositing a metal thin film on the substrate 10, and then patterning the metal thin film through a yellow light process and a wet etching process to obtain the metal routing layer 20.
Preferably, the material of the metal routing layer 20 is a combination of one or more of molybdenum, aluminum and copper, and the substrate 10 is a glass substrate.
Specifically, in step S1, a plurality of scan lines are formed simultaneously with the bonding lead 21 and the fanout line 22, and each scan line is correspondingly connected to one fanout line 22.
In step S2, please refer to fig. 8 to 9 or fig. 11 to 12, an insulating layer 30 is covered on the metal routing layer 20 and the substrate 10.
In step S3, please refer to fig. 7 to 9 or fig. 10 to 12, a plurality of buffer metal pads 41 arranged at intervals are formed on the insulating layer 30 above the fanout line 22, and each buffer metal pad 41 correspondingly covers one side of the fanout line 22 close to the bonding wire 21.
Specifically, in step S3, a plurality of data lines are formed simultaneously with the buffer metal pad 41, and each data line is correspondingly connected to one fanout line 22 through a via penetrating through the insulating layer 30.
Specifically, the step S3 specifically includes depositing a metal film on the insulating layer 30, and then patterning the metal film through a yellow light process and a wet etching process to obtain the buffer metal pad 41.
Preferably, buffer metal pad 41 extends from the connection point of fanout line 22 and bonding wire 21 in a direction away from bonding wire 21, and the extended length range is 50um to 100 um.
Further, as shown in fig. 7, in the first embodiment of the present invention, the buffer metal pad 41 has a shape of a continuous uninterrupted flat plate, more specifically, a rectangular plate.
Further, as shown in fig. 10, in the second embodiment of the present invention, the buffer metal pad 41 has the same pattern as the fanout line 22 located therebelow, for example, the fanout line 22 in fig. 6 is a wave-shaped winding, and at this time, the buffer metal pad 41 can also be made into a wave-shaped winding.
In step S4, please refer to fig. 8 to 9 or fig. 11 to 12, a passivation layer 50 is covered on the buffer metal pad 41 and the insulating layer 30.
Specifically, the passivation protection layer 50 is formed in step S4 by physical vapor deposition and chemical vapor deposition.
In step S5, please refer to fig. 8 to 9 or fig. 11 to 12, a connection via 51 penetrating through the insulating layer 30 and the passivation layer 50 is formed corresponding to each bonding wire 21.
In step S6, please refer to fig. 7 to 9 or fig. 10 to 12, a plurality of conductive leads 61 arranged in parallel and at intervals are formed on the passivation layer 50 above the bonding lead 21, and each conductive lead 61 is electrically connected to one bonding lead 21 through a corresponding connecting via 51.
Specifically, in step S6, a pixel electrode is further included, which is formed simultaneously with the conductive wiring 61.
That is, the bonding wire 21, the fanout line 22 and the scan line are formed at the same time, the buffer metal pad 41 and the data line are formed at the same time, and the conductive wire 61 and the pixel electrode are formed at the same time.
As shown in fig. 13 and 14, the buffer metal pad 41 functions as: when the COF signal lines 81 are aligned and pressed onto the conductive leads 61, the insulating layer 30 is supported to prevent the insulating layer 30 from being broken due to an excessive pressing force during pressing, so as to ensure that the COF signal lines 81 are not broken to cause the COF signal lines 81 to be misplaced and connected to other fanout lines 22 due to the breakage of the insulating layer 30, which causes short circuit and poor display, because of the existence of the buffer metal pads 41, the probability of the insulating layer 30 being broken due to pressing is greatly reduced, and the insulating layer 30 is not broken due to pressing, so that the length of the buffer area between the conductive leads 61 and the fanout lines 22 can be correspondingly reduced to be below 80um, even no buffer area is provided, that is, the distance from one end of each conductive lead 61 close to the fanout line 22 electrically connected with the bonding lead 21 corresponding to the conductive lead 61 is less than 80um, so as to fully utilize the space of the substrate 10, and narrow-frame display is realized.
In summary, the present invention provides a fan-out routing structure of a display panel, including: the circuit board comprises a substrate, a metal wiring layer positioned on the substrate, an insulating layer covering the metal wiring layer and the substrate, a plurality of buffer metal cushion layers which are arranged in parallel at intervals and positioned on the insulating layer, a passivation protective layer covering the insulating layer and the buffer metal cushion layers, and a plurality of conductive leads which are arranged in parallel at intervals and positioned on the passivation protective layer; the metal routing layer comprises: the fan-out wire comprises a plurality of bonding leads arranged in parallel at intervals and a plurality of fan-out wires which correspond to the bonding leads one by one and are electrically connected with the bonding leads respectively; each buffer metal pad correspondingly covers one side of one fanout line close to the bonding lead; through the setting of buffering metal pad, can form the support to the insulating layer, prevent that the insulating layer from crushing when counterpointing the pressfitting, reduce COF signal line and the risk of fan-out line short circuit appear when the position pressfitting of COF signal line, realize narrow frame and show. The invention also provides a manufacturing method of the fan-out wiring structure of the display panel, which can reduce the risk of short circuit of the COF signal line and the fan-out line when the COF signal line is in bit alignment.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.

Claims (10)

1. A display panel fan-out routing structure, comprising: the circuit board comprises a substrate (10), a metal wiring layer (20) positioned on the substrate (10), and an insulating layer (30) covering the metal wiring layer (20) and the substrate (10);
the metal routing layer (20) comprises: the wire drawing device comprises a plurality of bonding leads (21) which are arranged in parallel at intervals and a plurality of fanout wires (22) which correspond to the bonding leads (21) one by one and are electrically connected with the bonding leads respectively;
it is characterized by comprising: the insulating layer (30) is provided with a plurality of buffer metal cushion layers (41) which are arranged in parallel at intervals, a passivation protective layer (50) which covers the insulating layer (30) and the buffer metal cushion layers (41), and a plurality of conductive leads (61) which are arranged in parallel at intervals and are arranged on the passivation protective layer (50);
each buffer metal pad (41) correspondingly covers one side of one fanout line (22) close to the bonding lead (21);
correspond each bonding lead (21) and all be formed with the connection via hole (51) that runs through insulating layer (30) and passivation protective layer (50), each electrically conductive lead (61) all correspond and a bonding lead (21) electric connection through connecting via hole (51).
2. The display panel fan-out routing structure of claim 1, wherein the length of the buffer metal pad (41) in the extending direction of the fan-out line (22) is 50um to 100 um.
3. The display panel fan-out routing structure of claim 1, wherein the buffer metal pad (41) is in a shape of a continuous uninterrupted flat plate.
4. The display panel fan-out routing structure of claim 1, wherein the buffer metal pads (41) have the same pattern as fan-out lines (22) located thereunder.
5. The fan-out wiring structure of display panel according to claim 1, wherein the conductive leads (61) are used for bonding COF signal lines (81), and a distance from one end of each conductive lead (61) close to the fanout line (22) electrically connected to the bonding lead (21) corresponding to the conductive lead (61) is less than 80 um.
6. A manufacturing method of a fan-out routing structure of a display panel comprises the following steps:
step S1, providing a substrate (10), and forming a metal routing layer (20) on the substrate (10), wherein the metal routing layer (20) comprises: the wire drawing device comprises a plurality of bonding leads (21) which are arranged in parallel at intervals and a plurality of fanout wires (22) which correspond to the bonding leads (21) one by one and are electrically connected with the bonding leads respectively;
step S2, covering an insulating layer (30) on the metal wiring layer (20) and the substrate (10);
the method is characterized by comprising the following steps:
step S3, forming a plurality of buffer metal pads (41) arranged at intervals on the insulating layer (30) above the fan-out line (22), wherein each buffer metal pad (41) correspondingly covers one side, close to the bonding lead (21), of one fan-out line (22);
step S4, covering a passivation protection layer (50) on the buffer metal pad (41) and the insulating layer (30);
step S5, forming a connecting through hole (51) penetrating through the insulating layer (30) and the passivation protective layer (50) corresponding to each bonding lead (21);
and step S6, forming a plurality of conductive leads (61) which are arranged in parallel at intervals on the passivation protective layer (50) above the bonding lead (21), wherein each conductive lead (61) is correspondingly and electrically connected with one bonding lead (21) through a connecting through hole (51).
7. The method for manufacturing the fan-out routing structure of the display panel according to claim 6, wherein the length of the buffer metal pad (41) in the extending direction of the fan-out line (22) is 50um to 100 um.
8. The method for manufacturing the fan-out routing structure of the display panel according to claim 6, wherein the buffer metal pad (41) is shaped as a continuous and uninterrupted flat plate.
9. The method for manufacturing the fan-out routing structure of the display panel according to claim 6, wherein the buffer metal pad (41) has the same pattern as the fan-out line (22) located thereunder.
10. The method for manufacturing the fan-out wiring structure of the display panel according to claim 6, wherein the conductive leads (61) are used for bonding COF signal lines (81), and a distance from one end of each conductive lead (61) close to the fan-out line (22) electrically connected to the bonding lead (21) corresponding to the conductive lead (61) is less than 80 μm.
CN201810708953.1A 2018-07-02 2018-07-02 Fan-out wiring structure of display panel and manufacturing method thereof Active CN108845465B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810708953.1A CN108845465B (en) 2018-07-02 2018-07-02 Fan-out wiring structure of display panel and manufacturing method thereof
PCT/CN2018/113365 WO2020006946A1 (en) 2018-07-02 2018-11-01 Fan-out wiring structure of display panel and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810708953.1A CN108845465B (en) 2018-07-02 2018-07-02 Fan-out wiring structure of display panel and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN108845465A CN108845465A (en) 2018-11-20
CN108845465B true CN108845465B (en) 2020-07-28

Family

ID=64200874

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810708953.1A Active CN108845465B (en) 2018-07-02 2018-07-02 Fan-out wiring structure of display panel and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN108845465B (en)
WO (1) WO2020006946A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109884830B (en) * 2019-02-28 2021-09-21 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof, display device and mask plate
CN210954556U (en) * 2020-01-02 2020-07-07 京东方科技集团股份有限公司 Substrate and display panel
CN113031357B (en) * 2021-03-18 2022-09-09 绵阳惠科光电科技有限公司 Array substrate, liquid crystal display panel and liquid crystal display device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1892322A (en) * 2005-06-30 2007-01-10 三星电子株式会社 Display substrate, display device having the same, and method thereof
CN104269415A (en) * 2014-08-07 2015-01-07 友达光电股份有限公司 Array Substrate And Display

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000066953A (en) * 1999-04-22 2000-11-15 김영환 Data pad region of liquid crystal panel
JP3329328B2 (en) * 2000-03-28 2002-09-30 日本電気株式会社 Mounting structure of liquid crystal display device and method of manufacturing the same
KR20080001975A (en) * 2006-06-30 2008-01-04 삼성전자주식회사 Display substrate and display device having the same
CN100552770C (en) * 2007-09-20 2009-10-21 友达光电(苏州)有限公司 LCD circuit protection structure and its assemble method
TWI441122B (en) * 2011-12-30 2014-06-11 Au Optronics Corp Array substrate structure of display panel and method of making the same
CN103676342B (en) * 2013-12-27 2015-12-09 深圳市华星光电技术有限公司 The fanout area structure of narrow frame liquid crystal display
CN105093729B (en) * 2015-09-17 2018-02-27 京东方科技集团股份有限公司 Array base palte and preparation method thereof, display device
WO2018068183A1 (en) * 2016-10-10 2018-04-19 Boe Technology Group Co., Ltd. Display panel, display apparatus, and method of repairing a signal line thereof
CN107121855B (en) * 2017-07-04 2019-10-01 京东方科技集团股份有限公司 A kind of array substrate and preparation method thereof, display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1892322A (en) * 2005-06-30 2007-01-10 三星电子株式会社 Display substrate, display device having the same, and method thereof
CN104269415A (en) * 2014-08-07 2015-01-07 友达光电股份有限公司 Array Substrate And Display

Also Published As

Publication number Publication date
WO2020006946A1 (en) 2020-01-09
CN108845465A (en) 2018-11-20

Similar Documents

Publication Publication Date Title
US11488987B2 (en) Display substrate, splicing screen and manufacturing method thereof
US8031316B2 (en) Liquid crystal display device
US10283064B2 (en) Liquid crystal display, device and connection structure of display panel and system circuit
KR101826898B1 (en) Display panel
CN110349979B (en) Flexible display
US20230080422A1 (en) Display panel with narrow lower border and electronic device
CN109638061B (en) Display panel and method for manufacturing the same
CN108845465B (en) Fan-out wiring structure of display panel and manufacturing method thereof
CN111367125A (en) Array substrate and display panel
KR102371358B1 (en) Semiconductor packages and package modules using the same
CN113193017B (en) Display panel and display device
KR20080005101A (en) Electro-optical device, method for manufacturing electro-optical device, and electronic apparatus
US12096675B2 (en) Display panel
CN112255849A (en) Display substrate and electronic device
KR101119184B1 (en) Array substrate, display apparatus having the same and method of manufacturing the same
KR20170005254A (en) Display Device
US10359873B2 (en) Touch display screen
KR102632269B1 (en) Organic light emitting display device
JP2018073246A (en) Display apparatus
US11985863B2 (en) Display device and method of manufacturing the same
US20230116544A1 (en) Display panel and electronic device having same
CN102394231A (en) Chip connecting structure used for liquid crystal display
CN111308804A (en) Display panel
KR20180079481A (en) Organic light emitting display device
KR20100007612A (en) Display device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant