KR20180079481A - Organic light emitting display device - Google Patents

Abstract

The present disclosure discloses an organic light emitting display device. The organic light emitting display device includes: a substrate having a display region and a bending region; a first wiring electrically connected to a member in the display region, disposed on the substrate, and extending from the bending region to the display region; a first pattern member disposed on the substrate and spaced apart from a periphery of the first wiring in the bending region; a first planarization layer directly covering the first wiring and the first pattern member in the bending region; a second wiring disposed on the first planarization layer and extending from the bending region to the display region; a second pattern member disposed on the first planarization layer and spaced apart from a periphery of the second wiring in the bending region; and a second planarization layer directly covering the second wiring and the second pattern member in the bending region. Therefore, a short between wirings in the bending region is minimized and the stresses applied to the wirings are minimized.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting diode (OLED) display, and more particularly, to an OLED display capable of minimizing a short circuit between wirings in a bending region and minimizing stress caused by wiring.

Recently, as the information age has come to a full-fledged information age, a display field for visually expressing electrical information signals has been rapidly developed. In response to this, various display devices having excellent performance of thinning, light weight, Has been developed and is rapidly replacing existing cathode ray tubes (CRTs).

Specific examples of such a display device include a liquid crystal display (LCD), an organic light emitting display (OLED), an electroluminescent display, an electrophoretic display (EPD), and an electrowetting display device (EWD) . Particularly, an organic light emitting display device is a next generation display device having self-emission characteristics, and has excellent characteristics in terms of a viewing angle, a contrast, a response speed, and a power consumption as compared with a liquid crystal display device.

2. Description of the Related Art In recent years, organic light-emitting display devices which are manufactured such that a display portion, a wiring, and the like are formed on a flexible substrate such as a flexible plastic material and the like,

It is an important task to secure the flexibility of the substrate, the various insulating layers formed on the substrate, and the wiring formed of the metal material while manufacturing the organic light emitting display device using the flexible substrate.

The inventors of the present invention have been aware of the problems related to the flexibility with respect to wiring, and have come up with the following technical concept as a solution.

SUMMARY OF THE INVENTION The present invention provides an organic light emitting display device capable of minimizing stress applied to a wiring disposed in a bending region.

SUMMARY OF THE INVENTION The present invention provides an organic light emitting display device that minimizes a portion of a conductive material remaining in the vicinity of a wiring disposed in a bending region.

The present invention provides an organic light emitting display device capable of maximally securing a space in which wiring lines can be arranged in a non-display area by using a planarization layer composed of two sub-layers.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

An OLED display according to an embodiment of the present invention is provided. The organic light emitting display includes a substrate having a display region and a bending region, a first wiring electrically connected to a member in the display region, positioned on the substrate, and extending from the bending region to the display region, A first pattern member located on the substrate and spaced apart from the periphery of the first wiring in the bending region, a first planarization layer directly covering the first wiring and the first pattern member in the bending region, A second wiring located on the first planarization layer and extending from the bending area to the display area; a second wiring located on the first planarization layer and extending from the bending area to a second And a second planarization layer directly covering the second wiring and the second pattern member in the bending area.

The first pattern member is disposed in an area other than an area where the first wiring is located in the bending area.

The second pattern member is disposed in an area other than the area where the second wiring is located in the bending area.

The first wiring or the second wiring may have a buffer layer on a lower surface thereof.

The first pattern member or the second pattern member may be formed of the same material as the buffer layer.

And an inorganic layer covering the first wiring or the second wiring in the display region, wherein the inorganic layer is an insulating layer not disposed in the bending region.

The second wiring is characterized in that no layer is disposed between the second wiring and the second planarization layer and between the second wiring and the first planarization layer.

And the second wiring is surrounded by the first planarization layer and the second planarization layer.

The first wiring is characterized in that no layer is disposed between the first wiring and the first planarizing layer and between the first wiring and the substrate.

The first wiring is surrounded by the first planarization layer and the substrate.

Wherein at least one of the first wiring and the second wiring is formed in a planar manner in a planar shape that is repeatedly formed to receive a digonal segment structure, a zig-zag shape, a honeycomb shape, a herringbone pattern, In pattern.

According to another aspect of the present invention, there is provided an organic light emitting diode display comprising: a substrate having a bending region; a planarization layer disposed on the substrate in the bending region and having two sublayers; A first short prevention wiring pattern portion located between the planarization layers and having a plurality of first wirings and a second short wiring pattern portion located between the two sublayers in the bending region, Prevention wiring pattern portion is realized with a structure in which a break between the first wiring and a breakage in bending the first wiring is minimized, and the second short- And the second wiring is formed in a structure in which a break between the second wiring and a breakage of the second wiring when bending are minimized.

The first short-prevention wiring pattern portion may include a first buffer layer located between the substrate and the planarization layer and not contacting the first wiring, wherein the first wiring is located near the first buffer layer And a short circuit between the first wires is minimized because no foreign matter remains.

The first buffer layer is provided to improve both the uniformity of the surface of the substrate and the protection of the surface of the substrate.

The second short-prevention wiring pattern portion may include a second buffer layer located between the two sub-layers and not contacting the second wiring, wherein the second wiring is located near the second buffer layer, The short circuit between the second wires is minimized.

The second buffer layer is provided to improve the uniformity of the surface of the first planarization layer and to protect the surface of the first planarization layer.

The first wiring and the second wiring do not contact with the inorganic layer, so that breakage is minimized when bending.

One embodiment of the present invention does not dispose the inorganic layer in the adjacent region of the wiring in the bending region of the organic light emitting display, thereby minimizing the breakage of the wiring in the bending region.

One embodiment of the present invention can minimize a short between adjacent wirings in the bending region of the organic light emitting display.

In embodiments of the present invention, the wiring is formed in a non-display area of the organic light emitting diode display in a multi-layered structure, thereby realizing a narrow bezel.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a plan view for explaining an organic light emitting display according to an embodiment of the present invention.
FIG. 2A is a cross-sectional view of the organic light emitting diode display according to II-II 'of FIG.
FIG. 2B is an enlarged view of region A of FIG. 2A.
2C is a plan view for explaining a wiring structure for the region A in FIG. 2A.
3 is a cross-sectional view illustrating the compressive and tensile forces received by the layers disposed above and below the neutral plane, respectively, when the support layer is bent.
4A and 4B are cross-sectional views illustrating an OLED display according to another embodiment of the present invention.
5 is a schematic cross-sectional view illustrating a structure of the organic light emitting display shown in FIG. 2 in a final bending state.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

As the size and the resolution of the organic light emitting diode display have progressed, space for disposing the wiring in the non-display area has become insufficient. Therefore, when the non-display area is increased in order to arrange the wirings, it may be difficult to implement the miniaturization, thinning, narrow bezel / zero bezel shape.

In the case of wiring, when the substrate on which the wiring is formed is bent, cracks may be generated in the wiring due to stress caused by bending. If a crack is generated in the wiring, normal signal transmission is not performed, so that the thin film transistor or the organic light emitting element can not operate normally, leading to the failure of the organic light emitting display.

Further, in the case of the insulating layer in the non-display area, the flexibility is significantly lowered compared to the wiring formed of metal. Therefore, when the substrate on which the insulating layer is formed is bent, the insulating layer is also cracked . When cracks are generated in a part of the insulating layer, the generated cracks propagate to other regions of the insulating layer and propagate to the wiring in contact with the insulating layer, leading to defective display of the organic light emitting display.

Therefore, the inventors of the present invention have contemplated a method of minimizing the occurrence of cracks in the insulating layer and the wiring formed in the non-display area while placing the wiring more freely in the limited space in the non-display area of the organic light emitting display .

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a plan view for explaining an organic light emitting display according to an embodiment of the present invention.

1, the OLED display 100 includes an inactive area I / A surrounding an active area A / A and a display area A / A. do. In the display area A / A, an array of pixels is arranged. Although the organic light emitting display 100 is shown as having one display area A / A, the display area A / A may be plural.

The display area A / A is a region in which the image is displayed in the organic light emitting display device 100, and the display area A / A is variously driven for driving the organic light emitting device 160 and the organic light emitting device 160. The devices can be arranged.

The non-display area I / A may be disposed around the display area A / A. Specifically, the non-display area I / A may surround the display area A / A. Although the non-display area I / A is shown to surround the rectangular display area A / A, the non-display area I / A may be arranged in a non-display area A / A adjacent to the display area A / (I / A) is not limited to this. For example, in the case of a wearable display device of a user, the display device may have a circular shape such as a general wristwatch or a free-form display device applicable to a vehicle instrument panel or the like. Concepts may be applied.

The non-display area I / A is a region in which various signal lines such as the scan lines SL and the circuit parts such as the wiring lines 170 and the gate driver 190 are formed. The gate driver 190 may be arranged in a GIP form. Also, the data driver can be disposed in the non-display area I / A.

A pad 195 is disposed in the non-display area I / A. A pad 195 is disposed on one side of the substrate 110 in the non-display area I / A. The pad 195 is a metal pattern to which an external module, for example, a flexible printed circuit board (FPCB), a chip on film (COF), or the like is bonded. Although the pad 195 is shown as being disposed on one side of the substrate 110, the shape and arrangement of the pad 195 is not limited thereto.

And the wiring 170 is arranged in the non-display area I / A. The wiring 170 is a wiring 170 for transmitting a signal (voltage) from an external module bonded to the pad 195 to a circuit portion such as the display area A / A or the gate driver 190. For example, various signals for driving the gate driver 190 through the wiring 170, data signals, high voltage VDD, low voltage VSS, and the like can be transmitted. The wiring 170 may be formed simultaneously with the same material as the various conductive elements disposed in the display area A / A.

A bending area (B / A) is located in the non-display area I / A adjacent to the display area A / A. The bending area B / A is an area for disposing an external module bonded to the pad 195 and the pad 195 on the back side of the substrate 110. [ That is, as the bending area B / A is bent, the external module bonded to the pad 195 of the substrate 110 moves to the backside of the substrate 110, The external module may not be visible. Also, as the bending area B / A is bent, the size of the non-display area I / A, which is visible on the substrate 110, is reduced, and a narrow bezel can be realized. However, the bending area B / A is not limited to the bending area B / A in the non-display area I / A. And the bending area B / A located in the display area A / A can bend the display area A / A itself in various directions.

FIG. 2A is a cross-sectional view of the organic light emitting diode display according to II-II 'of FIG. The organic light emitting diode display 100 according to an embodiment of the present invention shown in FIG. 2A includes a plurality of organic light emitting display devices 100 each having a structure in which light emitted from the organic light emitting device 160 is emitted onto the organic light emitting display device 100 through the cathode 163 Emitting display device of the top emission type.

As shown in FIG. 2A, the substrate 110 supports various components of the OLED display 100. The substrate 110 may be made of a plastic material having flexibility, and may be made of, for example, polyimide (PI). In the case where the substrate 110 is made of polyimide (PI), the manufacturing process is performed in the state where the support substrate made of glass is disposed under the substrate 110, and the support substrate is released after the manufacturing process is completed have. Further, after the supporting substrate is released, a back plate for supporting the substrate may be disposed under the substrate 110. [

The buffer layer 111 is disposed on the substrate 110. The buffer layer 111 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) which is an inorganic material or a multilayer of silicon nitride (SiNx) and silicon oxide (SiOx). The buffer layer 111 improves adhesion between the layers formed on the buffer layer 111 and the substrate 110 and blocks alkaline components and the like flowing out from the substrate 110. However, the buffer layer 111 is not an essential component and may be omitted based on the type and material of the substrate 110, the structure and type of the thin film transistor 130, and the like.

The thin film transistor 130 is disposed on the buffer layer 111. The thin film transistor 130 includes an active layer 131 made of polysilicon, a gate electrode 134, a source electrode 132, and a drain electrode 133. The thin film transistor 130 is a driving thin film transistor and the gate electrode 134 is a thin film transistor of a top gate structure in which the active layer 131 is disposed. For convenience of explanation, only the driving thin film transistor among the various thin film transistors that can be included in the organic light emitting display 100 is shown. However, other thin film transistors such as switching thin film transistors may be included in the organic light emitting display 100. For convenience of explanation, the thin film transistor 130 is described as a coplanar structure, but the thin film transistor 130 may be implemented with another structure such as a staggered structure.

The active layer 131 of the thin film transistor 130 is disposed on the buffer layer 111. The active layer 131 includes a chanel area CA in which a channel is formed when the thin film transistor 130 is driven, a source area SA and a drain area DA on both sides of the channel area CA. ). The channel region CA, the source region SA and the drain region DA are defined by ion doping (impurity doping).

The active layer 131 of the thin film transistor 130 may be made of polysilicon. Thus, polysilicon is formed by depositing an amorphous silicon (a-Si) material on the buffer layer 111, performing a dehydrogenation process, a crystallization process, an activation process, and a hydrogenation process, (131) may be formed. When the active layer 131 is formed of polysilicon, the thin film transistor 130 may be an LTPS thin film transistor 130 using low temperature poly-silicon (LTPS). The polysilicon material has a high mobility, and when the active layer 131 is made of polysilicon, it has an advantage of low energy consumption and excellent reliability.

A gate insulating layer 112 is disposed on the active layer 131 and the buffer layer 111. The gate insulating layer 112 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) which is an inorganic material or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). The source electrode 132 and the drain electrode 133 of the gate insulating layer 112 each have a contact hole for making contact with the source region SA and the drain region DA of the active layer 131, respectively.

The gate electrode 134 is disposed on the gate insulating layer 112. A metal layer such as molybdenum (Mo) is formed on the gate insulating layer 112, and a gate electrode 134 is formed by patterning the metal layer. The gate electrode 134 is disposed on the gate insulating layer 112 so as to overlap the channel region CA of the active layer 131.

An interlayer insulating layer 115 is disposed on the gate electrode 134. The interlayer insulating layer 115 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) which is an inorganic material or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). A contact hole is formed in the interlayer insulating layer 115 so that each of the source electrode 132 and the drain electrode 133 contacts each of the source region SA and the drain region DA of the active layer 131.

The source electrode 132 and the drain electrode 133 are disposed on the interlayer insulating layer 115. The source electrode 132 and the drain electrode 133 may be formed of a conductive metal material and may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) Each of the source electrode 132 and the drain electrode 133 is connected to each of the source region SA and the drain region DA of the active layer 131 via the contact hole.

A storage capacitor 120 is disposed on the substrate 110. The storage capacitor 120 includes a first electrode 121 disposed on the gate insulating layer 112 and a second electrode 122 disposed on the interlayer insulating layer 115. The first electrode 121 of the storage capacitor 120 is simultaneously formed of the same material as the gate electrode 134 of the thin film transistor 130 and the second electrode 122 of the storage capacitor 120 is formed of the same material as the thin film transistor 130. [ The source electrode 132 and the drain electrode 133 may be formed of the same material. Accordingly, the storage capacitor 120 can be formed during the manufacturing process of the thin film transistor 130 without requiring any additional process, so that there is efficiency in terms of process cost and process time.

The passivation layer 116 may be disposed on the thin film transistor 130 and the storage capacitor 120. The passivation layer 116 is an insulating layer for protecting the thin film transistor 130 and the storage capacitor 120. The passivation layer 116 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), which are inorganic materials. The passivation layer 116 has a contact hole through which the anode 161 of the organic light emitting diode 160 is connected to the thin film transistor 130. The passivation layer 116 is not necessarily a necessary component and may be omitted depending on the design of the OLED display 100. [

The first planarization layer 113 is disposed on the passivation layer 116. The first planarization layer 113 is an insulating layer for planarizing the upper portion of the thin film transistor 130, and may be formed of an organic material. Since the passivation layer 116 is formed along the top of the thin film transistor 130 and the storage capacitor 120, the passivation layer 116 can not be planarized by the thin film transistor 130 and the storage capacitor 120, Can exist. The first planarization layer 113 may be formed over the thin film transistor 130 and the storage capacitor 120 to more reliably form the organic light emitting diode 160. A contact hole for exposing the source electrode 132 of the thin film transistor 130 is formed in the first planarization layer 113.

The additional buffer layer 118 is disposed on the first planarization layer 113. The additional buffer layer 118 protects the various conductive elements formed on the additional buffer layer 118 such as the intermediate electrode 139, the third electrode 123 of the storage capacitor 120, the additional wiring 140, . The additional buffer layer 118 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). However, the additional buffer layer 118 is not necessarily a necessary component, and may be omitted depending on the design of the organic light emitting display 100.

An intermediate electrode 139 is disposed on the additional buffer layer 118. The intermediate electrode 139 is connected to the source electrode 132 of the thin film transistor 130 through the passivation layer 116 and the contact hole of the first planarization layer 113. The intermediate electrode 139 may be laminated so as to be connected to the source electrode 132, and the data line may also be formed in a multi-layer structure. That is, the data line may be formed of a structure in which a lower layer made of the same material as the source electrode 132 and the drain electrode 133, and an upper layer made of the same material as the intermediate electrode 139 are connected. Therefore, the data line can be implemented in a structure in which two lines are connected to each other in parallel, so that the wiring resistance of the data line can be reduced.

A third electrode 123 of the storage capacitor 120 formed simultaneously with the intermediate electrode 139 is disposed on the additional buffer layer 118. Accordingly, the storage capacitor 120 includes a first electrode 121, a second electrode 122, and a third electrode 123. Accordingly, the storage capacitor 120 includes a capacitor having both the first electrode 121 and the second electrode 122 as its both terminals, and a capacitor having the second electrode 122 and the third electrode 123 as both terminals, And thus the capacitance of the storage capacitor 120 can be increased.

Further, on the additional buffer layer 118, an additional wiring 140, which is formed simultaneously with the same material as the intermediate electrode 139, is disposed. As the additional wiring 140 is disposed in the first planarizing layer 113, the number of wirings 170 for transmitting signals in the display area A / A can be more easily ensured.

The additional passivation layer 119 is disposed on the first planarization layer 113 to cover the intermediate electrode 139, the third electrode 123 of the storage capacitor 120, and the additional wiring 140. The additional passivation layer 119 is a layer for protecting the intermediate electrode 139, the third electrode 123 of the storage capacitor 120 and the additional wiring 140. The additional passivation layer 119 may be formed of silicon nitride (SiNx) or silicon oxide ) Or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). However, the additional passivation layer 119 is not necessarily a necessary component, and may be omitted according to the design of the organic light emitting display 100.

A second planarization layer 117 is disposed to planarize the intermediate electrode 139, the third electrode 123 of the storage capacitor 120, and the additional wiring 140. The second planarization layer 117 may have the same function as the first planarization layer 113 and may be formed of the same material. The anode 161 of the organic light emitting diode 160 is connected to the intermediate electrode 139 through the contact holes of the second planarization layer 117 and the additional passivation layer 119 and is connected to the thin film transistor 130 may be electrically connected to the source electrode 132 of the pixel electrode.

The organic light emitting device 160 is disposed on the second planarization layer 117. The organic light emitting device 160 includes an anode 161 formed on the second planarization layer 117 and electrically connected to the source electrode 132 of the TFT 130, an organic layer 162 disposed on the anode 161, And a cathode 163 formed on the organic layer 162. Since the OLED display 100 is a top emission type OLED display device, the anode 161 includes a reflective layer for reflecting light emitted from the organic layer 162 toward the cathode 163, and a reflective layer for reflecting holes emitted from the organic layer 162 to the organic layer 162 And may include a transparent conductive layer for supplying. However, the anode 161 may include only the transparent conductive layer, and the reflective layer may be defined as being a separate component from the anode 161. [ The organic layer 162 may include one of a red organic light emitting layer, a green organic light emitting layer, a blue organic light emitting layer, and a white organic light emitting layer as an organic layer for emitting light of a specific color. If the organic layer 162 includes a white organic light emitting layer, a color filter may be disposed on the organic light emitting device 160 to convert white light from the white organic light emitting layer into light having a different color. The organic layer 162 may further include various organic layers 162 such as a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer in addition to the organic emission layer. The cathode 163 may be made of a transparent conductive material, for example, a transparent conductive oxide such as IZO or ytterbium (Yb).

The bank 114 is disposed on the anode 161 and the second planarization layer 117. The bank 114 defines a pixel region in such a manner as to distinguish adjacent pixel regions in the display region A / A. The bank 114 may be made of organic material. For example, the bank 114 may be made of polyimide, acryl or benzocyclobutene (BCB) resin, but is not limited thereto.

An encapsulant may be formed on the organic light emitting diode 160 to protect the organic light emitting diode 160, which is vulnerable to moisture, from exposure to moisture. For example, the sealing portion may have a structure in which an inorganic layer and an organic layer are alternately stacked.

A first short prevention wiring pattern portion 191 and a second short prevention wiring pattern portion 192 are disposed in the bending area B / A.

The first short-prevention wiring pattern portion 191 includes a plurality of first wirings 171 and a first buffer layer 181. The first wiring 171 may be positioned between the substrate 110 and the planarization layers 113 and 117, which are composed of two sub-layers, in the bending area B / A. The first buffer layer 181 may be positioned between the substrate 110 and the planarization layers 113 and 117, which are composed of two sub-layers, in the bending region B / A. At this time, the first buffer layer 181 may not be in contact with the first wiring 171.

The second short-circuit prevention wiring pattern portion 192 includes a plurality of second wirings 172 and a second buffer layer 182. The second wiring 172 may be located between the sublayers of the planarization layers 113 and 117, which are composed of two sublayers in the bending region B / A. The second buffer layer 182 may be located between the sublayers of the planarization layers 113 and 117, which are composed of two sublayers in the bending region B / A. At this time, the second buffer layer 182 may not be in contact with the second wiring 172.

The wiring 170 may be formed of the same conductive material as the conductive element disposed in the display area A / A. For example, the first wiring 171 may be formed of the same conductive material as the source electrode 132 and the drain electrode 133. The second wiring 172 may be formed of the same conductive material as the intermediate electrode 139. However, it can be formed of other materials without being limited thereto.

There is a limit in the fineness of the etching process when the conductive material for forming the wiring 170 is deposited in the bending region B / A and then the conductive material is etched in the shape of the wiring 170 to be formed, There is a limit in narrowing the interval between the wirings 170. [ Therefore, since a large space is required to form the wiring 170 in the bending area B / A, the area of the non-display area I / A becomes large, which may cause difficulties in realizing the narrow bezel.

At this time, a space for forming a specific number of wirings 170 can be minimized by forming the wiring 170 in the bending area B / A in a multi-layer structure. For example, the first short prevention wiring pattern portion 191 in the bending region B / A is formed in the bending region B / A in the planarization layer (B / A) composed of the substrate 110 and two sub- 113 and 117, respectively. In addition, the second short prevention wiring pattern portion 192 may be located between the sub-layers of the planarization layers 113 and 117, which are composed of two sub-layers in the bending region B / A. Therefore, in the bending area B / A, the first short-circuit protection wiring pattern part 191 and the second short-circuit protection wiring pattern part 192 are formed by the planarization layers 113 and 117 composed of two sub- . Therefore, the implementation of the narrow bezel of the OLED display 100 is easy.

In order to form the wiring 170 in the bending area B / A in a multilayer structure, the planarization layers 113 and 117 formed of two sub-layers may be used. In the case where the planarization layers 113 and 117 formed of two sub-layers are used, various signal lines such as a scan line SL and a data line disposed in the display area A / A as well as the bending area B / And may be implemented as planarization layers 113 and 117 composed of two sub-layers. That is, in the display area A / A, various driving elements such as the thin film transistor 130, the storage capacitor 120, and the like are disposed, and the scan line SL and the source electrode 132 and the drain electrode 133 may be arranged in a multi-layer structure. That is, it is possible to minimize the disposition of the wirings arranged in the display area A / A. Thus, it is easy to secure an extra conductive layer for using the scan lines SL and the data lines in a multi-layered structure, so that the resistance of various signal lines such as the scan lines SL and the data lines can be reduced.

Further, in order to connect the storage capacitors 120 in parallel, a plurality of electrodes are required to overlap each other. In order to secure a plurality of electrodes, a plurality of conductive layers must be secured. At this time, by using the planarization layers 113 and 117 constituting the two sub-layers, it is possible to secure a plurality of conductive layers arranged so as to overlap each other in the multi-layer structure, and to form a plurality of electrodes superimposed on each other. Accordingly, it is possible to increase the capacitance of the storage capacitor 120 by implementing a storage capacitor 120 having a structure in which a plurality of capacitors are connected in parallel to each other.

In addition, since the wiring 170 is disposed in the bending region B / A, the wiring 170 itself may be damaged (or cracked) in the process of bending the substrate 110. [ In this case, when a plurality of wires 170 are used to transmit one signal, signals may be transmitted through other wires even if one wire breaks (or cracks). Therefore, it is minimized that the corresponding signal due to breakage of the wiring 170 can not be transmitted.

In the bending region B / A, the wiring layer 170 may not contact the inorganic layer. In the bending area B / A, the wiring 170 can protect the wiring 170 by contacting the organic material layer. For example, the first wiring 171 in the bending region B / A may be covered with the planarization layers 113 and 117. The second wiring 172 in the bending region can be surrounded by the sublayers of the planarization layers 113 and 117, which are composed of two sublayers. At this time, the first wiring 171 or the second wiring 172 may have a buffer layer 111 on the bottom surface thereof.

At this time, the first wiring may be encompassed between the substrate 110 and the planarization layers 113 and 117. And the second wiring may be encompassed between the two sublayers of the planarization layers 113 and 117. Accordingly, the inorganic layer may not contact the first wiring and / or the second wiring. Further, the first wiring and / or the second wiring can contact the organic layer constituting the planarization layers 113 and 117. The inorganic layer is more susceptible to stress due to bending than the organic material layer and the conductive material, so that breakage (or crack) is easily generated. At this time, since the inorganic layer is not brought into contact with the first wiring and / or the second wiring, it is possible to minimize the propagation of breakage (or crack) generated in the inorganic layer to the first wiring and / or the second wiring. Therefore, the bending of the first wiring and / or the second wiring can be realized with a structure in which breakage (or crack) is minimized. Accordingly, the wiring 170 can not transmit a signal due to breakage of the wiring 170, or the resistance of the wiring 170 is greatly increased, so that it is minimized that a desired signal can not be transmitted.

In the case where the wiring 170 is formed so as not to contact the inorganic layer in the bending area B / A, the wiring 170 is formed by depositing a conductive material for forming the wiring 170 in the bending area B / A , And patterning the conductive material in the shape of the wiring 170 to be formed by a process such as etching. In this case, the substrate 110 or the planarization layers 113 and 117 on which the conductive material is deposited may be formed of an organic material. Therefore, the substrate 110 or the planarization layers 113 and 117 may be partially damaged by, for example, an etchant or other materials before the conductive material is deposited. Accordingly, the uniformity of the surface of the substrate 110 or the planarization layers 113 and 117 can be reduced. Therefore, when a conductive material is deposited on the bending region B / A and then patterned by a process such as etching, a part of the conductive material remains on the surface of the substrate 110 or the planarization layers 113 and 117 to become a foreign material (or a remainder) . Also, when a conductive material is deposited and then patterned by a process such as etching, a part of the conductive material to be patterned and removed may become a foreign matter. A current may flow between the wirings 170 adjacent to each other due to the foreign matter, and a short may be generated in the wiring 170 formed by patterning the conductive material.

At this time, the buffer layer 180 may be disposed in the vicinity of the wiring 170. The buffer layer 180 may be formed by patterning in the bending region B / A before the conductive material is deposited. Specifically, the buffer layer 180 may be formed at a portion other than a portion where the wiring 170 is formed by patterning a conductive material. Therefore, the buffer layer 180 can improve the uniformity of the surface of the substrate 110 or the planarization layers 113 and 117. Accordingly, when the wiring 170 is formed, a conductive material is deposited on the bending region B / A, and then patterned by a process such as etching, a portion of the conductive material is formed on the surface of the substrate 110 or the planarization layers 113 and 117 The foreign matter can be minimized. Therefore, a short circuit between the adjacent wirings 170 can be minimized by foreign matter.

The buffer layer 180 may protect the surface of the substrate 110 or the planarization layers 113 and 117 when the conductive material is deposited in the bending region B / A and then patterned by a process such as etching. Therefore, when the wiring 170 is formed, a conductive material may be deposited on the bending region B / A and over-etching may be performed so as to prevent foreign matter from remaining when the conductive material is patterned by a process such as etching. Accordingly, it is possible to minimize a portion of the conductive material remaining on the surface of the substrate 110 or the planarization layers 113 and 117 as a foreign matter. Therefore, a short between adjacent wirings 170 that may be caused by foreign matter can be minimized.

For example, the first buffer layer 181 may be disposed in the vicinity of the first wiring 171, and the second buffer layer 182 may be disposed in the vicinity of the second wiring 172. The first buffer layer 181 can minimize foreign matter remaining in the vicinity of the first wiring 171. Therefore, a short between the first wirings 171 that can be generated by foreign matter can be minimized. In addition, the second buffer layer 182 can minimize foreign matter remaining in the vicinity of the second wiring 172. Therefore, a short between the second wirings 172, which may be caused by foreign matter, can be minimized.

FIG. 2B is an enlarged view of region A of FIG. 2A. FIG. 2B is a cross-sectional view illustrating the organic light emitting diode display 100 according to the exemplary embodiment of the present invention, in which the micro cover layer 150 is applied to the region A of FIG. 2A.

As shown in FIG. 2B, the first wiring 171 is disposed on the substrate 110 in the bending region B / A. The first wiring 171 extends from the bending area B / A to the display area A / A so as to be electrically connected to the member on the substrate 110 in the display area A / A. At this time, a buffer layer 111 is disposed on the substrate 110, and a first wiring 171 is disposed on the buffer layer 111. In the bending area B / A, the first pattern member 181 is disposed on the substrate 110. The first pattern member 181 may be spaced apart from the periphery of the first wiring 171.

At this time, the first pattern member 181 may be formed of the same material and / or structure as the buffer layer 111. Therefore, the process of forming the first pattern member 181 can be simplified. Accordingly, the first pattern member 181 may be referred to as a first buffer layer.

A first planarization layer 113 is disposed on the first wiring 171 and the first pattern member 181. At this time, no layer is disposed between the first wiring 171 and the first planarization layer 113 in the bending area B / A. Also, no layer is disposed between the first pattern member 181 and the first planarization layer 113 in the bending region B / A. Accordingly, the first planarization layer 113 may directly cover the first wiring 171 and the first pattern member 181. [ Thus, the first wiring 171 can be surrounded by the buffer layer 111 and the first planarization layer 113. The first pattern member 181 may be surrounded by the substrate 110 and the first planarization layer 113.

In the bending region B / A, the second wiring 172 is disposed on the first planarization layer 113. The second wiring 172 extends from the bending area B / A to the display area A / A so as to be electrically connected to the member on the substrate 110 in the display area A / A. At this time, the second wiring 172 in the bending area B / A is disposed on the first planarization layer 113. Further, an additional buffer layer may be disposed on the first planarization layer 113, and a second wiring 172 may be disposed on the additional buffer layer. In the bending region B / A, the second pattern member 182 is disposed on the first planarization layer 113. The second pattern member 182 may be located apart from the periphery of the second wiring 172.

At this time, the second pattern member 182 may be formed of the same material and / or structure as the additional buffer layer 118. Therefore, the process of forming the second pattern member 182 can be simplified. Accordingly, the second pattern member 182 may be referred to as a second buffer layer.

A second planarization layer 117 is disposed on the second wiring pattern 172 and the second pattern member 182. At this time, no layer is placed between the second wiring 172 and the first planarization layer 113 in the bending area B / A, and no layer is formed between the second wiring 172 and the second planarization layer 117 Will not be published. No layer is disposed between the second pattern member 182 and the first planarization layer 113 in the bending region B / A and between the second pattern member 182 and the second planarization layer 117 No layers are posted. Accordingly, the second planarization layer 117 may directly cover the second wiring 172 and the second pattern member 182. [ Accordingly, the second wiring 172 and the second pattern member 182 may be surrounded by the first planarization layer 113 and the second planarization layer 117.

At this time, the second wiring 172 is disposed on the substrate 110 in the display area A / A or a member disposed on the substrate 110 in the display area A / A and connected with the first wiring 171, The connected member may be located at the top or bottom of the inorganic layer. At this time, the inorganic layer may be an insulating layer that prevents electrical connection between members in the display area (A / A). But are not limited to, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 115, an additional buffer layer 118, an additional passivation layer 119, and the like. At this time, the insulating layer is located in the display area A / A and can cover the first wiring 171 or the second wiring 172 in the display area A / A. That is, the inorganic layer covers the first wiring 171 or the second wiring 172 in the display area A / A and the first wiring 171 or the second wiring 172 in the bending area B / . Therefore, when the first wiring 171 or the second wiring 172 is bent in the bending area B / A, the inorganic layer does not contact the first wiring 171 or the second wiring 172, It is possible to minimize the propagation of damage to the first wiring 171 or the second wiring 172. The first wiring 171 or the second wiring 172 can not transmit a signal due to breakage of the first wiring 171 or the second wiring 172 or a signal is not transmitted due to a large resistance increase Failure can be minimized.

At this time, the first pattern member 181 can be formed before the first wiring 171 in which the inorganic layer is not in contact is formed. The first pattern member 181 may be patterned in the bending region B / A before the conductive material for forming the first wiring 171 is deposited. At this time, the first pattern member 181 may be patterned in a region other than the region where the first wiring 171 is located in the bending region B / A. At this time, the first pattern member 181 can improve the uniformity of the surface of the substrate 110. Accordingly, when the first wiring 171 is formed, a part of the conductive material is left on the surface of the substrate 110 when the conductive material is deposited in the bending region B / A and then patterned by a process such as etching Can be minimized.

The first pattern member 181 may be formed by depositing a conductive material for forming the first wiring 171 in the bending region B / A and then patterning the surface of the substrate 110 Can be protected. Therefore, when the first wiring 171 is formed, a conductive material is deposited on the bending region B / A, and then patterned by a process such as etching, a conductive material is deposited on the surface of the substrate 110 through overetching. The remaining part can be minimized.

In other words, no foreign matter remains between the first wiring 171 and another first wiring 171 adjacent to the first wiring 171 by the first pattern sub-element 181 in the process of forming the first wiring 171, (171) can be minimized.

Further, the second pattern member 182 can be formed before the second wiring 172 in which the inorganic layer is not in contact is formed. The second pattern member 182 may be patterned and formed in the bending region B / A before the conductive material for forming the second wiring 172 is deposited. At this time, the second pattern member 182 may be patterned in an area other than the area where the second wiring 172 is located in the bending area B / A. At this time, the second pattern member 182 can improve the uniformity of the surface of the first planarization layer 113. Accordingly, when the second wiring line 172 is formed, a conductive material is deposited on the bending area B / A and then patterned by a process such as etching to form a part of the conductive material on the surface of the first planarization layer 113 Remaining can be minimized.

The second pattern member 182 may be formed by depositing a conductive material for forming the second wiring 172 in the bending region B / A and then patterning the first planarization layer 113, The surface can be protected. Therefore, when the second wiring line 172 is formed, the conductive material is deposited on the bending area B / A, and then patterned by a process such as etching. In this case, the surface of the first planarization layer 113 is electrically conductive Part of the material can be minimized.

That is, in the process of forming the second wiring 172, no foreign matter remains between the second wiring 172 and the second wiring 172 adjacent to the second wiring 172 due to the second pattern sub- The short-circuit between the electrodes 172 can be minimized.

Since the first wiring 171 and the second wiring 172 are arranged in a multi-layered structure of the first planarizing layer 113 and the second planarizing layer 117, when the same number of wirings are arranged in a single layer The area occupied by the wiring can be reduced. At this time, the first pattern member 181 is formed in a region where the first wiring 171 is not formed in the bending region B / A and the second pattern member 182 is formed in a region where the second wiring member 171 is not formed in the bending region B / The area of the non-display area I / A can be reduced by arranging the first wirings 171 and the second wirings 172 in a multi-layered structure, The bezel can also be implemented.

In addition, in the organic light emitting diode display 100, the position of the neutral plane NP can be adjusted to minimize the breakage of components arranged in the bending region B / A.

Hereinafter, the first wiring 171, the second wiring 172, the buffer layer 111, the first planarization layer 113, and the second planarization layer 117 are formed so as to minimize breakage in the bending region B / A To illustrate, FIG. 3 will be described first.

3 is a cross-sectional view for explaining the compressive and tensile forces received by the layers disposed above and below the neutral plane, respectively, when the support layer is bent. 3, the first layer L1 is disposed on the upper surface of the support layer M, the second layer L2 is disposed on the lower surface of the support layer M, It is assumed that the two layers (L2) are formed of the same material and the same thickness. 3 corresponds to the substrate 110. The first layer L1 or the second layer L2 corresponds to the first wiring 171, the second wiring 172, the buffer layer 111, The first planarization layer 113, and the second planarization layer 117. [0064]

A neutral plane (NP) is a virtual plane that is not subjected to stress because the compressive force and the tensile force applied to the structure are canceled each other when the structure is bent. The first layer L1 is disposed on the upper surface of the support layer M and the second layer L2 is disposed on the lower surface of the support layer M so that both ends of the support layer M are lowered, It can be assumed that the support layer M is bent in a shape in which the support layer M is bent upward. At this time, since the first layer (L1) disposed on the upper surface of the support layer (M) is extended, the second layer (L2) disposed on the lower surface of the support layer (M) receives the tensile force and is compressed. The neutral plane NP is disposed on the support layer M in the middle portion in the structure in which the first layer L1, the support layer M and the second layer L2 are laminated. That is, when the other side of the supporting layer M is bent downward in a state where one side of the supporting layer M is fixed, the first layer L1 positioned above the neutral plane NP receives a tensile force and the neutral plane NP And the second layer (L2) located under the first layer (L2) is subjected to compressive force. However, when the first wiring 171, the second wiring 172, the buffer layer 111, the first planarization layer 113, and the second planarization layer 117 are subjected to a tensile force of compressive force and tensile force of the same size, It is more likely that the first layer L1 is cracked than the second layer L2, provided that the distance from the neutral plane NP is the same.

2B, the first wiring 171, the second wiring 172, the buffer layer 111, the first planarization layer 113, and the second planarization layer 113 disposed in the bending region B / It is very important to optimize the neutral plane (NP) to minimize the magnitude of the force when the layer 117 is not subjected to tensile force or is subjected to tensile force.

In the organic light emitting diode display 100, the neutral plane NP may be positioned on the second wiring 172. In the structure of the bending region B / A of the OLED display 100, the buffer layer 111, the first wiring 171, the second wiring 172, the first planarization A compressive force may be applied to the layer 113 and the second planarization layer 117. [ The first wiring 171, the second wiring 172, the buffer layer 111, the first planarization layer 113, and the second planarization layer 117, which are disposed in the bending area B / A, It is very important to optimize the neutral plane (NP) to minimize the magnitude of the force even if it is subjected to tensile force.

The neutral plane NP is determined in consideration of the thickness, Young's modulus, and the like of the components disposed in the corresponding region. In the OLED display 100, the neutral plane (B / A) NP may be positioned on the second wiring 172. At this time, a micro cover layer 150 is disposed on the second planarization layer 117.

The micro cover layer 150 disposed in the bending area B / A is configured such that the neutral plane NP at the time of bending the substrate 110 is positioned on the second wiring 172 in the bending area B / A . At this time, the thickness d of the micro cover layer 150 and the position of the neutral plane NP can be determined by the constituent material.

As the thickness d of the micro cover layer 150 disposed on the second planarization layer 117 is thicker, the neutral plane NP can rise. The thickness d of the micro cover layer 150 is determined such that the thickness d of the micro cover layer 150 has a large value so that the neutral plane NP is disposed on the second wiring 172 It is possible.

In addition, the neutral plane NP may be determined depending on the constituent material of the micro cover layer 150. [ Specifically, the position of the neutral plane NP can be determined according to the Young's modulus of the material constituting the micro-cover layer 150. Young's modulus is a value indicating the ductility of a material and is a characteristic characteristic of a material which indicates the degree of resistance to tensile or compression of the material. When the Young's modulus of a specific material is high, the shape is not easily deformed because the tensile is also resistant to compression, and when the Young's modulus of a specific material is low, the shape and strain can be easily deformed because the tensile and compressive resistance are small. When the Young's modulus of the constituent material of the micro cover layer 150 is large, the position of the neutral plane NP can be raised. Also, if the Young's modulus of the constituent material of the micro cover layer 150 is excessively large, the micro cover layer 150 itself may be broken during the bending process. Also, if the Young's modulus of the constituent material of the micro-cover layer 150 is excessively small, the neutral plane NP may be disposed under the second wiring 172. Accordingly, while the neutral plane NP is disposed on the second wiring 172, the constituent material of the micro cover layer 150 is determined such that the micro cover layer 150 has a Young's modulus value such that the Young's modulus does not break due to an increase in the Young's modulus .

When the thickness d of the micro cover layer 150 and the constituent materials are adjusted so that the neutral plane NP is disposed on the second wiring 172 as described above, the first wiring 171 and the second wiring 172, the buffer layer 111, and a portion of the first planarization layer 113 and the second planarization layer 117 are disposed below the neutral plane NP. As a result, the first wiring 171, the second wiring 172, the buffer layer 111, and portions of the first planarization layer 113 and the second planarization layer 117 are subjected to a compressive force at the time of bending, The damage to the wiring 171, the second wiring 172, the buffer layer 111, the first planarization layer 171, and the second planarization layer 172 can be minimized

2C is a plan view for explaining a wiring structure for the region A in FIG. 2A. 2C, only the first wiring 171, the first pattern member 181, the second wiring 172, and the second pattern member 182 are illustrated for convenience of explanation.

As described above, if the area occupied by the wiring 170 is kept the same, the number of wirings 170 for transmitting one signal can be increased. For example, the wiring 170 may be configured so that two adjacent first wires 171 carry one signal and two adjacent second wires 172 transmit another signal. have. Further, the first wiring 171 and the second wiring 172 on the plane may be alternately arranged. At this time, at least one of the first wiring 171 and the second wiring 172 in the bending area B / A is formed in a planar shape in a diagonal segment structure, a zig-zag shape, Shape, a herringbone pattern, and a repetitive pattern that accommodates substrate bending.

It is preferable to maximize the interval between the first wiring 171 and the second wiring 172 because the first wiring 171 and the second wiring 172 located in different layers transmit different signals. That is, as the distance between the first wiring 171 and the second wiring 172 is narrowed, the possibility of interference with signals transmitted through the first wiring 171 and the second wiring 172 increases, It is desirable that the interval between the first wiring 171 and the second wiring 172 is maximized within a design-possible range. Thus, the first wiring 171 and the second wiring 172 do not overlap each other, and the second wiring 172 is provided between adjacent first wirings 171, for example, between neighboring first wirings 171 171, respectively.

Each of the first wiring 171 and the second wiring 172 may be formed to extend in a direction different from the extending direction of the first wiring 171 and the second wiring 172. That is, although the first wiring 171 and the second wiring 172 extend in the downward direction, the direction in which the first wiring 171 and the second wiring 172 are actually formed may be a diagonal direction. Accordingly, the force applied to the first wiring 171 and the second wiring 172 during bending can be dispersed, and the buffer layer 111 surrounding the first wiring 171 and the second wiring 172, 1 < / RTI > planarization layer 113 and the second planarization layer 117 can also be dispersed.

The first batten member 181 may be disposed on an area other than the area where the first wiring 171 is located on the same layer as the first wiring 171, The second pattern member 182 may be disposed in an area other than the area where the two wirings 172 are located. The first pattern member 181 may be overlapped with the second wiring 172 and the second pattern member 182 may be overlapped with the first wiring 171. [ At this time, the portion of the conductive material remaining between the adjacent first wirings 171 by the first pattern member 181 can be minimized. In addition, the second pattern member 182 can minimize the portion of the conductive material remaining between the adjacent second wirings 172. [ Therefore, shorting between adjacent wirings can be minimized by the first pattern member 181 and the second pattern member 182. [

4A and 4B are cross-sectional views illustrating an OLED display according to another embodiment of the present invention. 4A is a cross-sectional view of an OLED display 200 according to another embodiment of the present invention. 4B is an enlarged view of region A of FIG. 4A. 4B is a cross-sectional view illustrating the organic light emitting diode display 200 according to another embodiment of the present invention to which the micro cover layer 150 for the A region of FIG. 4A is applied. The organic light emitting diode display 200 shown in FIGS. 4A and 4B is different from the OLED display 100 shown in FIGS. 2A and 2B in that the structure related to the bending area B / A is changed, The components are substantially the same, so redundant descriptions are omitted.

4A and 4B, the first wiring 271 is disposed on the substrate 110 in the bending area B / A. The first wiring 271 extends from the bending area B / A to the display area A / A so as to be electrically connected to the member on the substrate 110 in the display area A / A. At this time, the first wiring 271 is disposed on the substrate 110. In the bending region B / A, the first pattern member 281 is disposed on the substrate 110. The first pattern member 281 may be spaced apart from the periphery of the first wiring 271.

At this time, the first pattern member 281 may be formed of the same material and / or structure as the buffer layer 111. Therefore, the process of forming the first pattern member 281 can be simplified. Accordingly, the first pattern member 281 may be referred to as a first buffer layer.

A first planarization layer 113 is disposed on the first wiring 271 and the second pattern member 281. At this time, no layer is placed between the first wiring 271 and the first planarization layer 113 in the bending area B / A. Also, no layer is shown between the first pattern member 281 and the first planarization layer 113 in the bending region B / A. Accordingly, the first planarization layer 113 may directly cover the first wiring pattern 271 and the first pattern member 281. No layer is disposed between the first wiring 271 and the substrate 110. Accordingly, the first wiring 271 can be surrounded by the substrate 110 and the first planarization layer 113. The first pattern member 281 may be surrounded by the substrate 110 and the first planarization layer 113.

In the bending region B / A, the second wiring line 272 is disposed on the first planarization layer 113. The second wiring 272 extends from the bending area B / A to the display area A / A so as to be electrically connected to the member on the substrate 110 in the display area A / A. At this time, the second wiring 272 in the bending area B / A is disposed on the first planarization layer 113. In the bending region B / A, the second pattern member 282 is disposed on the first planarization layer 113. And the second pattern member 282 may be spaced apart from the periphery of the second wiring 272.

At this time, the second pattern member 282 may be formed of the same material and / or structure as the additional buffer layer 118. Therefore, the process of forming the second pattern member 282 can be simplified. Accordingly, the second pattern member 282 may be referred to as a second buffer layer.

A second planarization layer 117 is disposed on the second wiring 272 and the second pattern member 282. At this time, no layer is placed between the second wiring 272 and the first planarization layer 113 in the bending region B / A, and no layer is formed between the second wiring 272 and the second planarization layer 117 Will not be published. No layer is disposed between the second pattern member 282 and the first planarization layer 113 in the bending region B / A and between the second pattern member 282 and the second planarization layer 117 No layers are posted. Thus, the second planarization layer 117 may directly cover the second wiring 272 and the second pattern member 282. [ Accordingly, the second wiring 272 and the second pattern member 282 can be surrounded by the first planarization layer 113 and the second planarization layer 117.

At this time, the second wiring 272 is disposed on the substrate 110 in the display area A / A or a member disposed on the substrate 110 and connected with the first wiring 271, The connected member may be located at the top or bottom of the inorganic layer. At this time, the inorganic layer may be an insulating layer that prevents electrical connection between members in the display area (A / A). But are not limited to, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 115, an additional buffer layer 118, an additional passivation layer 119, and the like. At this time, the insulating layer may be located only in the display area A / A without being positioned in the bending area B / A. Therefore, the insulating layer is disposed under the first wiring 271 or the second wiring 272 in the display area A / A to protect the first wiring 271 or the second wiring 272, And may cover the first wiring 271 or the second wiring 272 by being positioned on the second wiring 271 or the second wiring 272.

That is, the inorganic layer can protect or cover the first wiring 271 or the second wiring 272 only in the display area A / A, and in the bending area B / A, the first wiring 271 or the second wiring 272, The wiring 272 is not protected or covered. Therefore, when the first wiring 271 or the second wiring 272 is bent in the bending area B / A, the inorganic layer does not contact the bending area B / A, 1 wiring 271 or the second wiring 272 can be minimized. As a result, the first wiring 271 or the second wiring 272 can not transmit signals due to breakage of the first wiring 271 or the second wiring 272, or the resistance is greatly increased, Failure can be minimized.

At this time, the first pattern member 281 may be formed before the first wiring 271 in which the inorganic layer is not in contact is formed. The first pattern 271 is formed between the first wirings 271 and another first wirings 271 adjacent to the first wirings 271 by the first pattern members 281 when the first wirings 271 are formed after the first pattern members 281 are formed. Foreign objects may not be left. Therefore, a short circuit between adjacent first wirings 271 can be minimized.

Further, the second pattern member 282 can be formed before the second wiring 272 in which the inorganic layer is not in contact is formed. When the second pattern member 282 is formed and then the second pattern member 282 is formed between the second wiring 272 and another adjacent second wiring 272 at the time of forming the second wiring 272 Foreign objects may not be left. Therefore, a short between the adjacent second wirings 272 can be minimized.

Since the first wiring 271 and the second wiring 272 are arranged in a multi-layered structure of the first planarizing layer 113 and the second planarizing layer 117, when the same number of wirings are arranged in a single layer The area occupied by the wiring can be reduced. At this time, the first pattern member 281 is formed in a region where the first wiring 271 is not formed in the bending region B / A, and the second pattern member 282 is formed in the region where the second wiring member 272 is formed in the bending region B / The area of the non-display area I / A can be reduced by disposing the first wirings 271 and the second wirings 272 in a multi-layered structure, The bezel can also be implemented.

In the organic light emitting diode display 200, the neutral plane NP may be positioned on the second wiring 272. In the structure of the bending region B / A of the OLED display 200, the first wiring 271, the second wiring 272, the first planarization layer 113, A compressive force may be applied to the second planarizing layer 117. Even if the first wiring 271, the second wiring 272, the first planarization layer 113 and the second planarization layer 117 disposed in the bending region B / A are neither subjected to tensile force nor subjected to a tensile force It is very important to optimize the neutral plane (NP) to minimize the magnitude of the force.

The thickness d of the micro cover layer 150 and the constituent material are adjusted so that the neutral plane NP is not in contact with the neutral plane NP because the neutral plane NP has the same magnitude of the compressive force and the tensile force, 2 wiring 272. In this way, At this time, a portion of the first wiring 271, the second wiring 272, the first planarization layer 113 and the second planarization layer 117 is disposed below the neutral plane NP. Accordingly, since the first wiring 271, the second wiring 272, the first planarizing layer 113 and the second planarizing layer 117 are subjected to a compressive force at the time of bending, the first wiring 271, 2 wiring 272, the first planarization layer 113, and the second planarization layer 117 can be minimized

FIG. 5 is a cross-sectional view illustrating a structure of the organic light emitting display shown in FIG. 2 in a final bending state. FIG. 5 shows a final bending structure of the OLED display 100 shown in FIG. 5, only the micro-cover layer 150 among various components disposed on the substrate 110 is shown for convenience of explanation.

A barrier film (101) is disposed on a substrate (110). The barrier film 101 may be arranged to correspond to at least a display area A / A of the organic light emitting display 100, for protecting various components of the organic light emitting display 100. The barrier film 101 may be made of a material having adhesiveness and serve to fix the polarizing plate 102 on the barrier film 101. [ The micro cover layer 150 may be formed so as to cover one side of the barrier film 101. [

A back plate 103 is disposed under the substrate 110. In the case where the substrate 110 is made of a plastic material such as polyimide (PI), the manufacturing process of the organic light emitting display 100 proceeds in a state where a support substrate made of glass is disposed under the substrate 110, The support substrate may be released after the manufacturing process of the apparatus 100 is completed. However, a back plate 103 for supporting the substrate 110 may be disposed under the substrate 110, since a component for supporting the substrate 110 is required even after the supporting substrate is released. The back plate 103 may be disposed adjacent to the bending area B / A in another area of the substrate 110 except for the bending area B / A. Back plate 103 may be formed of a plastic film formed of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), other suitable polymers, a combination of these polymers, and the like.

A supporting member 105 is disposed between the two back plates 103 and the supporting member 105 can be adhered to the back plate 103 by the adhesive layer 104. [ The support member 105 may be formed of a plastic material such as polycarbonate (PC), polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), other suitable polymers, . The strength of the support member 105 formed of such plastic materials may be controlled by providing additives to increase the thickness and / or strength of the support member 105. [ The support member 105 may be formed with a desired color (e.g., black, white, etc.). In addition, the support member 105 may be formed of glass, ceramic, metal or other rigid materials or combinations of the foregoing materials.

The COF 106 may be disposed on the pad 195 disposed on one side of the substrate 110, as described above with reference to FIG. Various IC chips may be disposed in the COF 106. In addition, the micro cover layer 150 may be disposed to cover one side of the COF 106.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

110: substrate
111: buffer layer
112: gate insulating layer
113: first planarization layer
114: bank
115: interlayer insulating layer
116: Passivation layer
117: second planarization layer
118: additional buffer layer
119: Additional passivation layer
120, 420: storage capacitor
121: first electrode
122: second electrode
123: third electrode
130: thin film transistor
131: active layer
132: source electrode
133: drain electrode
134: gate electrode
SA: source region
DA: drain region
CA: Channel area
139: intermediate electrode
140: Additional wiring
150: Micro cover layer
160: Organic light emitting device
161: anode
162: organic layer
163: cathode
170, 270: Wiring
171, 271: first wiring
172, 272: second wiring
180: buffer layer
181, 281: a first buffer layer (or first pattern member)
182, 282: a second buffer layer (or second pattern member)
190: Gate driver
195: Pad
100, 200: organic light emitting display
A / A: active area
I / A: Non-display area
B / A: Bending area
SL: scan line
NP: Neutral side
M: Support layer
L1: first layer
L2: Second layer

Claims (16)

A substrate having a display region and a bending region;
A first wiring electrically connected to a member in the display region, the first wiring being located on the substrate and extending from the bending region to the display region;
A first pattern member located on the substrate and spaced apart from the periphery of the first wiring in the bending region;
A first planarization layer directly covering the first wiring and the first pattern member in the bending region;
A second wiring located on the first planarization layer and extending from the bending area to the display area;
A second pattern member located on the first planarization layer and spaced apart from the periphery of the second wiring in the bending region; And
And a second planarization layer directly covering the second wiring and the second pattern member in the bending region. The method according to claim 1,
Wherein the first pattern member is disposed in an area other than an area where the first wiring is located in the bending area,
Wherein the second pattern member is disposed in an area other than an area where the second wiring is located in the bending area. 3. The method of claim 2,
Wherein the first wiring or the second wiring includes a buffer layer on a lower surface thereof. The method of claim 3,
Wherein the first pattern member or the second pattern member is formed of the same material as the buffer layer. 3. The method of claim 2,
And an inorganic layer covering the first wiring or the second wiring in the display region, wherein the inorganic layer is an insulating layer not disposed in the bending region. 6. The method of claim 5,
Wherein the second wiring is not disposed between the second wiring and the second planarization layer and between the second wiring and the first planarization layer. The method according to claim 6,
And the second wiring is surrounded by the first planarization layer and the second planarization layer. 8. The method of claim 7,
Wherein the first wiring does not include any layer between the first wiring and the first planarization layer and between the first wiring and the substrate. 9. The method of claim 8,
Wherein the first wiring is surrounded by the first planarization layer and the substrate. 10. The method of claim 9,
Wherein at least one of the first wiring and the second wiring is formed in a planar manner in a planar shape that is repeatedly formed to receive a digonal segment structure, a zig-zag shape, a honeycomb shape, a herringbone pattern, Wherein the organic light emitting display device is one of a plurality of organic light emitting display devices. A substrate having a bending region;
A planarization layer positioned on the substrate in the bending region and consisting of two sublayers;
A first short prevention wiring pattern portion located between the substrate and the planarization layer in the bending region and having a plurality of first wirings; And
And a second short prevention wiring pattern portion located between the two sublayers in the bending region and having a plurality of second wirings,
The first short-prevention wiring pattern portion is implemented with a structure in which breakage between the first wiring and the bending of the first wiring is minimized,
Wherein the second short-circuit prevention wiring pattern portion is implemented with a structure that minimizes short-circuiting between the second wirings and breakage of the second wiring when bending. 12. The method of claim 11,
The first short-prevention wiring pattern portion may include a first buffer layer located between the substrate and the planarization layer and not contacting the first wiring,
Wherein the first wiring is located in the vicinity of the first buffer layer so that a foreign matter is not left, and a short circuit between the first wiring is minimized. 13. The method of claim 12,
Wherein the first buffer layer is provided to improve the uniformity of the surface of the substrate and to protect the surface of the substrate. 14. The method of claim 13,
The second short-prevention wiring pattern portion may include a second buffer layer located between the two sub-layers and not contacting the second wiring,
Wherein the second wiring is located near the second buffer layer so that a foreign matter is not left and a short circuit between the second wiring is minimized. 15. The method of claim 14,
Wherein the second buffer layer enhances the uniformity of the surface of the first planarization layer and protects the surface of the first planarization layer. 14. The method of claim 13,
Wherein the first wiring and the second wiring are formed in a structure in which breakage is minimized when bending because the first wiring and the second wiring do not contact the inorganic layer.

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