CN107039523A - 于主动区域中具有栅极接触的三维半导体晶体管 - Google Patents
于主动区域中具有栅极接触的三维半导体晶体管 Download PDFInfo
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Abstract
一种于主动区域中具有栅极接触的三维半导体晶体管,该三维晶体管包含半导体衬底、连结至该衬底的鳍片,该鳍片包含横跨该鳍片的顶部的主动区域,该主动区域包含源极、漏极及在该源极与漏极之间的沟道区域。该晶体管更包含位在该沟道区域上方的栅极、以及位在该主动区域中的栅极接触,没有部分该栅极接触电性连结至该源极或漏极。该晶体管在制造期间是通过移除位在该栅极接触下方的该源极/漏极接触的一部分而达成。
Description
技术领域
本发明一般是关于三维半导体晶体管及其制造。尤其,本发明是关于用于三维半导体晶体管的栅极接触及其在主动区域中没有栅极至源极/漏极短路的制造。
背景技术
现有的鳍式场效应晶体管(FinFET)半导体结构的制造将栅极接触放置在主动区域的外部,以避免栅极接触至源极/漏极接触短路。然而,此方法可能造成设计限制并使用更多的面积。当半导体装置持续缩减时,半导体面积损耗的问题愈来愈多。
因此,存在减少三维半导体晶体管的占用面积同时允许向下缩减的需求。
发明内容
在一个态样中,本发明通过于主动区域中形成栅极接触的方法,克服先前技艺的缺点并提供额外的优点。该方法包含提供初始半导体结构,该结构包含半导体衬底、连结至该衬底的至少一个鳍片、围绕该至少一个鳍片的底部的隔离材料、在各鳍片的顶部的外延半导体材料、在该外延半导体上方的沟槽硅化物接触、与具有遮盖及间隔物的栅极结构。该方法更包含移除在该栅极结构下方的该沟槽硅化物接触的一部分。
依据另一个态样,本发明提供一种半导体结构。该结构包含半导体衬底及连结至该半导体衬底的至少一个鳍片,且该鳍片具有以源极、漏极及栅极围绕该至少一个鳍片的一部分的主动区域。该结构更包含用于接触各该源极与漏极及栅极接触的沟槽硅化物接触,各接触位于该主动区域中,该沟槽硅化物接触为部分地凹陷以低于该栅极接触。
依据又另一个态样,本发明提供一种三维半导体晶体管。该晶体管包含半导体衬底、连结至该衬底的鳍片,该鳍片包含横跨该鳍片的顶部的主动区域,该主动区域包含源极、漏极及在该源极及漏极之间的沟道区域。该晶体管更包含位在该沟道区域上方的栅极及位在该主动区域中的栅极接触,没有部分该栅极接触电性连结至该源极或漏极。
本发明的这些及其它目的、特征及优点,从本发明下列的各种态样结合附加的图式的详细说明将变得显而易见。
附图说明
图1为依据本发明的一个或多个的态样,包含初始半导体结构的一个例子的三个剖面图,该结构包含半导体衬底、连结至该衬底的鳍片、由隔离材料所围绕的该鳍片的底部、及使用外延材料于其上(源极/漏极)所凹陷的该鳍片的顶部、与在该外延材料上方的沟槽硅化物接触,该结构也包含栅极结构,各栅极结构围绕鳍片的一部分并包含由间隔物及栅极遮盖所围绕的一个或多个的传导材料,该栅极结构由上方介电层所围绕。
图2为依据本发明的一个或多个的态样,说明图1的该初始半导体结构的主要部分的一个例子的俯视图(top-down view),该主要部分包含栅极结构、鳍片及沟槽硅化物接触,以及显示于图1的各种剖面图。
图3为依据本发明的一个或多个的态样,描绘在形成遮罩层于该结构上方及图案化以曝露出沟槽硅化物接触的一部分之后的图1的该结构的一个例子。
图4为依据本发明的一个或多个的态样,描绘在移除硅化物的一部分、移除掩模及平坦化之后的图3的该结构的一个例子。
图5为依据本发明的一个或多个的态样,描绘在形成覆盖的额外介电层于该结构上方及移除该覆盖的额外介电层的一部分,以曝露出该沟槽硅化物接触的顶面之后的图4的该结构的一个例子。
图6为依据本发明的一个或多个的态样,描绘在形成类似于图3的掩模层的覆盖共形(blanket conformal)掩模层,图案化栅极接触且移除该额外介电层的一部分(例如,通过固定时间的蚀刻),以曝露出该栅极遮盖之后的图5的该结构的一个例子。
图7为依据本发明的一个或多个的态样,描绘在选择性移除该栅极遮盖及所结合的间隔物的顶部,以曝露出该栅极之后的图6的该结构的一个例子。
图8为依据本发明的一个或多个的态样,描绘在例如使用灰化(ashing)制造方法移除该掩模层之后的图7的该结构的一个例子。
图9为依据本发明的一个或多个的态样,描绘在对于该源极/漏极及栅极以一个或多个的传导材料填覆该开孔(源极/漏极及栅极接触,个别地或一起),以建立接触之后的图8的该结构的一个例子。
图10为依据本发明的一个或多个的态样,描绘图9的该结构的主要部分包含接触的俯视图的一个例子。
具体实施方式
本发明的态样与特定的特征、优点及其细节,参考附加图式中的非限定的例子于下文中做更完整地说明。已熟知的材料、制造工具、加工技术等等的描述,将会忽略以免非必要地遮掩本发明的细节。然而,应该了解的是细部的描述及特定的例子,虽然显示本发明的态样,为仅给定说明的目的,并且不在于限定的目的。各种替代、修改、增加及/或配置,均在下文的本发明概念的精神及/或范畴内,本揭露对于本领域技术人员将是显而易见的。
近似的语言,如同在整个说明书及权利要求书于此所使用的,可以适用于修饰能够允许改变的任何量化的表示而不会造成在相关于该基本功能上的改变。因此,由术语或多个术语所修饰的数值,诸如“大约”,不在于限定所界定的精确的数值。在某些例子中,该接近的语言可以对应于用于量测该数值的仪器的精确性。
在此所使用的术语仅是用于描术特定例子的目的而并非意在本发明的限定。如同在此所使用的,单数形式“一”、“一个”及“该”也意在包含多形式,除非前后文另外明确标示。更进而了解的是术语“包括”(以及任何形式的包括,诸如“包含”及“含有”)、“具有”(以及任何形式的具有,诸如“拥有”及“含有”)、“包含”(以及任何形式的包含,诸如“包括”及“含有”)、与“含有”(以及任何形式的含有,诸如“具有”及“包含”)是开放式的联结动词。因此,“包括”、“具有”、“包含”或“含有”一个或多个的步骤或元件的方法或装置拥有该一个或多个的步骤或元件,但并非限定于仅拥有该一个或多个的步骤或元件。同样地,“包括”、“具有”、“包含”或“含有”一个或多个的特征的方法的步骤或装置的元件拥有该一个或多个的特征,但是并非意在仅拥有该一个或多个的特征。再者,以特定方式经由配置的装置或结构是至少以该方式配置,但是也可能以未列出的方式配置。
如本文所用的,术语“连接”,当使用于两个实体元件时,意指在该两个实体元件之间的直接连接。然而,术语“连结”可以意指直接连接或通过一个或多个的中介元件的连接。
如本文所用的,术语“可”及“可以是”显示在一组情况中发生的可能性;具有某种属性、特性或功能;及/或通过表示一个或多个的能力、性能或可能性修饰另一个动词而结合该修饰的动词。因此,“可”及“可以是”的使用显示修饰的术语是明显适当的、能够的或适合于指定的性能、功能或使用,尽管考量在某些情况下该修饰的术语可能有时不是适当的、能够的或适合的。例如,在某些情况下,事件或性能可能无法发生-该区别是由该术语“可”及“可以是”所获得。
参考下列图式,图式为了便于了解并非以比例绘制,其中,相同的图式标号使用于全文不同的图式中以指定相同或类似的组件。
图1为依据本发明的一个或多个的态样,包含初始半导体结构100的一个例子的三个剖面图101、103及105,该结构包含半导体衬底102、连结至该衬底的鯺片104、由隔离材料106所围绕的该鳍片的底部、及使用外延材料110于其上(源极/漏极,例如,通过成长)所凹陷的该鳍片的顶部108、与在该外延材料110上方的沟槽硅化物接触112,该结构也包含栅极结构114,各栅极结构围绕鳍片的一部分并包含由间隔物(例如间隔物118)及栅极遮盖(例如,栅极遮盖120)所围绕的一个或多个的传导材料116,该栅极结构及硅化物由上方介电层122(例如,内层介电物)所围绕。该栅极结构可以是虚设(dummy)栅极结构或传导的(金属)栅极结构。
该初始结构可以是以传统的制造,例如使用已知的制造方法及技术。再者,除非另外提及,可以使用现有的制造方法及技术以达到在此所描述的该制造制造方法的个别步骤。然而,虽然为了简化目的仅部分显示,应该要了解的是,在实施上,许多此类的结构通常包含在相同的块体衬底上。
在一个例子中,衬底102可以包含任何含硅的衬底,包含但不限于硅(Si)、单晶硅、多晶硅、非晶硅、悬空硅(SON,Silicon-On-Nothing)、绝缘体上硅(SOI,silicon-On-Insulator)、或替代绝缘体上硅(SRI,Silicon-on-Replacement Insulator)或硅锗衬底及类似者。衬底102可以另外或替代包含各种隔离物、掺杂及/或装置架构。该衬底可以包含其它适当的基本半导体,例如,单晶锗(Ge);复合半导体,诸如碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)、及/或锑化铟(InSb)或其组合;合金半导体,包含磷砷化镓(GaAsP)、砷铟化铝(AlInAs)、砷铟化镓(GaInAs)、磷铟化镓(GaInP)、或砷磷化镓铟(GaInAsP)或其组合。
在一个例子中,该鯺片104可以从块体衬底蚀刻而得,并且可以包含,例如,上方所列出的任何该材料可用于该衬底者。再者,某些或所有鳍片可以包含添加的不纯物(例如,通过掺杂),使该鳍片成为n型或p型。
图2为依据本发明的一个或多个的态样,说明图1的该初始半导体衬底100的主要部分124的一个例子的俯视图,该主要部分包含栅极结构114、鳍片104及沟槽硅化物接触112,以及显示于图1的各种剖面图101、103、105。
图3为依据本发明的一个或多个的态样,描绘在形成掩模层126于该结构上方及图案化以曝露出该沟槽硅化物接触112的一部分(例如,部分128)之后的图1的该结构的一个例子。参见图10用于该掩模层开孔的俯视图。
在一个例子中,图3的掩模层可以包含例如有机平坦化材料,并且可以使用例如光刻而形成。
图4为依据本发明的一个或多个的态样,描绘在移除可能与尚未制造的栅极接触造成短路的该硅化物112的一部分129及移除该掩模(126,图3)之后的图3的该结构的一个例子。
在一个例子中,沟槽硅化物接触可以包含在该源极/漏极外延材料上方的薄层的硅化物(例如,大约5纳米)、以及在该硅化物上方的一种或多种例如为钨的传导金属,且也可以包含例如为钛或氮化钛的衬层材料,并可以使用例如固定时间的干蚀刻制造方法以部分移除该传导金属而完成。在本例子中,该接触剩余的沟槽硅化物部分的部分具有粗略L形。
图5为依据本发明的一个或多个的态样,描绘在形成覆盖的额外介电层130于该结构上方及移除该覆盖的额外介电层的一部分132,以曝露出该沟槽硅化物接触112的顶面134之后的图4的该结构的一个例子。
在一个例子中,图5的结构可以通过例如使用化学气相沉积制造方法形成介电层(例如,二氧化硅)、例如使用化学机械研磨制造方法平坦化该介电层、及执行额外的光刻/蚀刻制造方法而实现,以形成曝露该沟槽硅化物接触的该沟槽。参见图10,用于该沟槽的俯视图。
图6为依据本发明的一个或多个的态样,描绘在形成类似于图3的该掩模层的覆盖共形掩模层136,图案化栅极接触且移除该额外介电层130的一部分(例如,通过固定时间的蚀刻),以露出该栅极遮盖(例如,栅极遮盖120)之后的图5的该结构的一个例子。
图7为依据本发明的一个或多个的态样,描绘在选择性移除该栅极遮盖(例如,栅极遮盖120)及所结合的间隔物(例如,间隔物118)顶部,以曝露出该栅极(例如,栅极116)之后的图6的该结构的一个例子。
在一个例子中,选择性移除该栅极遮盖及该间隔物的顶部可以使用,例如,对围绕介电层(例如,氧化物)具选择性的干式蚀刻制造方法移除氮化硅遮盖及间隔物而完成。
图8为依据本发明的一个或多个的态样,描绘在例如使用灰化制造方法移除该掩模层(136,图7)之后的图7的该结构的一个例子。
图9为依据本发明的一个或多个的态样,描绘在对于该源极/漏极及栅极(图7,138、140及142)以一个或多个的传导材料填覆该开孔(源极/漏极及栅极接触,个别地或一起),以各别地建立接触144、146及148之后的图8的该结构的一个例子。
在一个例子中,使用于填覆的传导材料可以包含例如钨,且该填覆可以包含例如过度填覆,且接着平坦化向下至该介电材料(例如,使用化学机械研磨制造方法)。
图10为依据本发明的一个或多个的态样,描绘图9的该结构的主要部分包含接触144、146及148的俯视图的一个例子。
在第一态样中,本发明于上述揭露一种方法。该方法包含提供初始半导体结构,该结构包含半导体衬底、连结至该衬底的鳍片、围绕该鳍片的底部的隔离材料、在各鳍片的顶部的外延半导体材料、在该外延半导体材料上方的沟槽硅化物接触、与具有遮盖及间隔物的栅极结构。该方法更包含移除在该栅极结构下方的该沟槽硅化物接触的一部分。
在一个实施例中,该方法更可以包含,例如,曝露出该沟槽硅化物接触的未移除部分的一部分、曝露出该栅极、与形成用于该源极、漏极及栅极的接触。
在一个实施例中,在该第一态样的方法中移除在该栅极结构下方的该沟槽硅化物接触的一部分可以包含,例如,形成保护层在除了该沟槽硅化物接触的该部分上方之外的该结构上方,并移除该沟槽硅化物接触的该部分。在一个例子中,该保护层可以包含例如有机平坦化层,且该移除可以包含例如执行灰化制造方法。
在一个例子中,曝露出该沟槽硅化物接触的未移除部分的一部分包括使用光刻及蚀刻制造方法。
在一个例子中,在该第一态样的方法中曝露出该栅极可以包括,例如,形成覆盖共形介电层于该结构上方、形成保护层在除了该至少一个栅极上方之外的该结构上方、曝露出该栅极遮盖及该间隔物的顶部、并移除该曝露的栅极遮盖及该间隔物的顶部,以曝露出该栅极。
在一个例子中,该保护层可以包含例如有机平坦化层(OPL),且曝露出该栅极遮盖及间隔物可以包含例如执行固定时间的蚀刻。在另一个例子中,移除该曝露的栅极遮盖及该间隔物的顶部可以包含,例如,对该覆盖共形介电层执行具选择性的蚀刻。
在一个例子中,在该第一态样的方法中形成用于该栅极的接触可以包含,例如,形成功函数材料层。
在一个例子中,在该第一态样的方法中形成用于该栅极的接触可以包含,例如,填覆一种或多种金属。
在一个例子中,在该第一态样的该方法中形成用于该源极、漏极及栅极的接触可以包含,例如,共用的金属填覆(common metal fill)。
在第二态样中,本发明于上文揭露一种半导体结构。该结构包含半导体衬底及连结至该半导体衬底的鳍片、且该鳍片具有以源极、漏极及栅极围绕该鳍片的一部分的主动区域。该结构更包含用于各源极与漏极及栅极接触的沟槽硅化物接触,各接触位于该主动区域中,该沟槽硅化物接触为部分凹陷以低于该栅极接触。
在一个例子中,该沟槽硅化物接触各自包含硅化物及传导金属。
在第三态样中,本发明于上文所揭露为一种三维半导体晶体管。该晶体管包含半导体衬底、连结至该衬底的鳍片,该鳍片包含横跨该鳍片的顶部的主动区域,该主动区域包含源极、漏极及在该源极与漏极之间的沟道区域。该晶体管更包含位在该沟道区域上方的栅极、及位在该主动区域中的栅极接触,没有部分该栅极接触电性连结至该源极或漏极。
在一个例子中,该晶体管更可以包含例如源极接触及漏极接触,各该源极接触及该漏极接触包括其经移除低于该源极接触及该漏极接触的一部分,同时与该源极及漏极维持着完整的电性接触。在一个例子中,各该源极接触及该漏极接触可以具有,例如,大致L形的部分以直接接触该源极及漏极。
在一个例子中,该第三态样的该三维晶体管的该半导体衬底可以包含,例如,具有该鳍片连结至其上的块体半导体衬底。
虽然本发明的数个态样已经在此作说明及描绘,另外的态样对于本领域技术人员可能是有效的以完成该相同的目的。因此,本发明意在通过附加的权利要求书以涵括所有此类的替代态样而落在本发明的真正的精神及范畴内。
Claims (17)
1.一种方法,包括:
提供初始半导体结构,该结构包括:半导体衬底、连结至该衬底的至少一个鳍片、围绕该至少一个鳍片的底部的隔离材料、在各鳍片的顶部的外延半导体材料、在该外延半导体材料上方的沟槽硅化物接触、与具有遮盖及间隔物的栅极结构;以及
移除在该栅极结构下方的该沟槽硅化物接触的一部分。
2.如权利要求1所述的方法,更包括:
曝露出该沟槽硅化物接触的非移除部分的一部分;
曝露出该栅极;以及
形成用于该源极、漏极及栅极的接触。
3.如权利要求1所述的方法,其中,移除在该栅极结构下方的该沟槽硅化物接触的一部分包括:
形成保护层在除了该沟槽硅化物接触的该部分上方之外的该结构上方;以及
移除该沟槽硅化物接触的该部分。
4.如权利要求3所述的方法,其中,该保护层包括有机平坦化层,且其中,该移除包括执行灰化制造方法。
5.如权利要求1所述的方法,其中,曝露出该沟槽硅化物接触的非移除部分的一部分包括使用光刻及蚀刻制造方法。
6.如权利要求1所述的方法,其中,曝露出该栅极包括:
形成覆盖共形介电层于该结构上方;
形成保护层在除了该至少一个栅极上方之外的该结构上方;
曝露出该栅极遮盖及该间隔物的顶部;以及
移除该曝露的栅极遮盖及该间隔物的顶部,以曝露出该栅极。
7.如权利要求6所述的方法,其中,该保护层包括有机平坦化层(OPL),且其中,曝露出该栅极遮盖及间隔物包括执行固定时间的蚀刻。
8.如权利要求6所述的方法,其中,移除该曝露的栅极遮盖及该间隔物的顶部包括对该覆盖共形介电层选择性蚀刻。
9.如权利要求1所述的方法,其中,形成用于该至少一个栅极的接触包括形成一个或多个功函数材料层。
10.如权利要求1所述的方法,其中,形成用于该至少一个栅极的接触包括填覆一种或多种金属。
11.如权利要求1所述的方法,其中,形成用于该至少一个源极、至少一个漏极及至少一个栅极的接触包括共用的金属填覆。
12.一种半导体结构,包括:
半导体衬底及连结至该半导体衬底的至少一个鳍片,且该鳍片具有以源极、漏极及栅极围绕该至少一个鳍片的一部分的主动区域;
用于各该源极与漏极及栅极接触的沟槽硅化物接触,各接触位于该主动区域中;以及
其中,该沟槽硅化物接触为部分地凹陷以低于该栅极接触。
13.如权利要求12所述的半导体结构,其中,各该沟槽硅化物接触包括硅化物及至少一种传导金属。
14.一种三维半导体晶体管,包括:
半导体衬底;
连结至该衬底的鳍片,该鳍片包括横跨该鳍片的顶部的主动区域,该主动区域包括源极、漏极及在该源极与漏极之间的沟道区域;
位在该沟道区域上方的栅极;以及
位在该主动区域中的栅极接触,其中,没有部分该栅极接触电性连结至该源极或漏极。
15.如权利要求14所述的三维晶体管,更包括源极接触及漏极接触,各该源极接触及该漏极接触包括其经移除低于该栅极接触的一部分,同时与该源极及漏极维持着完整的电性接触。
16.如权利要求15所述的三维晶体管,其中,各该源极接触及该漏极接触具有大致L形的部分以直接接触该源极及漏极。
17.如权利要求14所述的三维晶体管,其中,该半导体衬底包括具有多个该鳍片连结至其上的块体半导体衬底。
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