CN106992250A - A kind of Nonvolatile resistance variation memory cell with multilevel storage characteristic based on ferroelectricity hetero-junctions and preparation method thereof - Google Patents
A kind of Nonvolatile resistance variation memory cell with multilevel storage characteristic based on ferroelectricity hetero-junctions and preparation method thereof Download PDFInfo
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- 230000005621 ferroelectricity Effects 0.000 title claims abstract description 64
- 238000003860 storage Methods 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 35
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- 229910052760 oxygen Inorganic materials 0.000 claims description 14
- 239000001301 oxygen Substances 0.000 claims description 14
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
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- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000004549 pulsed laser deposition Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 4
- 229910019653 Mg1/3Nb2/3 Inorganic materials 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 3
- 238000004062 sedimentation Methods 0.000 claims description 3
- 239000013077 target material Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229910015846 BaxSr1-xTiO3 Inorganic materials 0.000 claims description 2
- 229910003327 LiNbO3 Inorganic materials 0.000 claims description 2
- 229910002113 barium titanate Inorganic materials 0.000 claims description 2
- 229910000765 intermetallic Inorganic materials 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000001771 vacuum deposition Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
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- 229910052709 silver Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910018507 Al—Ni Inorganic materials 0.000 description 1
- 229910017398 Au—Ni Inorganic materials 0.000 description 1
- -1 ITO Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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Abstract
A kind of Nonvolatile resistance variation memory cell with multilevel storage characteristic based on ferroelectricity hetero-junctions and preparation method thereof, belongs to semiconductor solid-state memory technology field.It is made up of write-in hearth electrode, ferro-electricity single crystal substrate, change resistance layer and top electrode；Prepared by the lower surface of ferro-electricity single crystal substrate have write-in hearth electrode, and prepared by upper surface have change resistance layer；Being prepared on change resistance layer has top electrode, and top electrode is made up of four strip electrodes, and middle two strip electrodes are the reading electrode of resistance states, and two strip electrodes being symmetrically distributed in the outside for reading electrode are write-in top electrode, are connected with outer lead；Or top electrode is made up of an annular electrode and two strip electrodes, annular electrode symmetrical ring is around being distributed in around two strip electrodes, and annular electrode is write-in top electrode, and two strip electrodes are the reading electrode of resistance states；Write-in top electrode together form the write-in electrode of resistance states with write-in hearth electrode.With simple in construction, stability is strong, low manufacture cost, the characteristics of room temperature can be operated in.
Description
Technical field
The invention belongs to semiconductor solid-state memory technology field, and in particular to it is a kind of based on ferroelectricity hetero-junctions have it is many
It is worth Nonvolatile resistance variation memory cell of storage characteristics and preparation method thereof.
Background technology
Information recording device is one of elemental device in modern information industry, mostly has its in most of electronic products
In the presence of, including mobile phone, computer, camera, automobile electronic system, global positioning system etc..Classify by data can be preserved after power-off,
Memory is broadly divided into, nonvolatile memory and the major class of volatile memory two.It can not be preserved after volatile memory power-off
Data, and remain to preserve data after nonvolatile memory power-off.
Traditional non-volatile memory is mainly based upon magnetic storage and optical storage, and solid-state memory does not have read/write head, is not required to
Rotate, thus little power consumption, shock resistance are strong, and solid-state memory electronically written and the mode of reading, it is possible to achieve more speed
Data write-in and read.Instantly the solid-state memory based on semiconductor technology is obtained rapidly due to its excellent performance advantage
Development.Particularly dynamic RAM (DRAM) and flash memory (Flash) occur, and have led a revolution of field of storage.
However, causing technology to continue to develop high storage density and the high demand for reading writing speed, device size constantly reduces,
DRAM and Flash will narrow down to its physics limit.After the characteristic size for entering more than ten nanometers, quantum effect is clearly demarcated by ten
It is aobvious, it is simple to realize that the technology path of higher storage density is walked to be at the end at last by the reduction of memory cell characteristic size.
By taking dynamic memory as an example, if the electric capacity in memory cell is too small, it is impossible to provide the electronics of enough quantity to
Amplifier, it is impossible to obtain enough signal to noise ratio, the reliability of information storage can not be guaranteed.As can be seen here, it is impossible to Jin Jinyi
The demand of high density data storage faced is solved by the reduction of device size, therefore is stored in a memory cell multiple
The multilevel storage technology of bit seems more and more important.Because in traditional memory cell, only two states " conducting ", " absolutely
Two Resistance states of edge ", i.e. "ON" and "Off", correspondence and " 0 " and " 1 " in binary system.Realized in single memory cell multiple
The storage of state will greatly improve the storage density of memory.
The content of the invention
The present invention is in view of the above-mentioned problems, propose a kind of has multilevel storage characteristic based on ferroelectricity hetero-junctions at room temperature
Non-volatile variable-resistance memory unit and preparation method thereof.
A kind of non-volatile variable-resistance memory unit with multilevel storage characteristic based on ferroelectricity hetero-junctions, as shown in figure 1, by
Write hearth electrode, ferro-electricity single crystal substrate, change resistance layer and top electrode composition；Write hearth electrode (thickness of electrode is 0.1~100 μm)
By elemental metals material (such as Al, Pt, Au, W, Ag), metal alloy compositions (such as Au-Ni, Al-Ni, Au-Ti), lead
One or more in electric metal compound (such as ITO, IZGO) are made, and prepare the lower surface in ferro-electricity single crystal substrate；Iron
Electric monocrystal chip, can select the monocrystal material of ferroelectric properties, such as BaTiO3、BaxSr1-xTiO3、LiNbO3、(1-x)Pb
(Mg1/3Nb2/3)O3/xPbTiO3(0 ＜ x ＜ 1) etc. (thickness is 0.3~0.6mm)；Being prepared in the upper surface of ferro-electricity single crystal substrate has
TiO2Film change resistance layer, thickness is 10~70nm；In TiO2Being prepared on film change resistance layer has top electrode (material of top electrode is by list
One or more in the metallic compound of matter metal material, metal alloy compositions and conduction are made, and thickness is 10~100nm),
Top electrode is made up of four strip electrodes, and middle two strip electrodes are the reading electrode of resistance states, is reading the outer of electrode
Two strip electrodes that side is symmetrically distributed are write-in top electrode, are connected with outer lead；Or top electrode is by an annular electrode
Constituted with two strip electrodes, annular electrode symmetrical ring is around being distributed in around two strip electrodes, and annular electrode pushes up for write-in
Electrode, two strip electrodes are the reading electrode of resistance states；Write-in top electrode together form resistance shape with write-in hearth electrode
The write-in electrode of state.
Another aspect of the present invention provides a kind of non-volatile resistive with multilevel storage characteristic based on ferroelectricity hetero-junctions
The preparation method of memory cell, its step is as follows：
(1) cleaning of ferro-electricity single crystal substrate
Ferro-electricity single crystal substrate is cleaned by ultrasonic using acetone, ethanol and deionized water successively, or uses plasma
Cleaning machine is cleaned, and makes monocrystal chip surface no-pollution；
(2) pulsed laser deposition has the TiO of Lacking oxygen on ferro-electricity single crystal substrate2Film is used as change resistance layer
With pulsed laser deposition technique, high-purity (purity is selected>99.9%) TiO2Ceramics are used as target material, oxygen
There is the TiO of Lacking oxygen under environment in ferro-electricity single crystal deposition on substrate2Film；Target is 50 apart from the spacing of ferroelectricity monocrystal chip
Partial pressure of oxygen in~60mm, chamber is 0.05~1Pa, and ferro-electricity single crystal substrate temperature is 650~750 DEG C, the frequency of pulse laser
For 1~4Hz, sedimentation time is 0.5~2 hour, and ferro-electricity single crystal substrate is naturally cooled into room temperature after the completion of deposition；
(3) prepare electrode and obtain multivalue variable-resistance memory unit；
The preparation method of electrode is the methods such as vacuum coating, magnetron sputtering, laser deposition or silk-screen printing.Hearth electrode is whole
The bottom surface of ferro-electricity single crystal substrate is covered, top electrode is prepared in TiO2Film surface；The reading electrode of resistance states is connected to outer
On the resistance measurement element in portion, the write-in electrode of resistance states is connected on the voltage output component of outside；So as to be prepared into
To the non-volatile variable-resistance memory unit with multilevel storage characteristic of the present invention based on ferroelectricity hetero-junctions.
The present invention realizes that multilevel storage is to be based on TiO2Lacking oxygen in film change resistance layer can be moved in the presence of electric field
The general principle of shifting.By in TiO2Film surface builds resistance write-in top electrode, is built in the lower surface of ferro-electricity single crystal substrate
Resistance writes hearth electrode, and impressed DC voltage can realize Lacking oxygen in TiO between write-in top/hearth electrode2The upper table of film
Migrated between face and film and ferroelectric substrate interface.In TiO2Film surface builds the reading electrode of resistance, and Lacking oxygen is different
State can be to reading electrode and TiO2The barrier height and width of the Schottky contacts of film produce influence, and then obtain different
Resistance states.Under room temperature condition, Lacking oxygen in film can keep its in space relative after outside write-in electric field removes
Position, therefore the state of the resistance of film can realize prolonged holding.The backing material selected in the present invention is ferroelectricity list
Crystalline substance, because ferroelectric single crystal material has spontaneous polarization, residual polarization can be on the boundary of film and substrate after external electrical field is removed
Face adsorption charge is simultaneously kept.Thus when additional electric field exceedes coercive field, ferro-electricity single crystal substrate polarized state can be entered
Row modulation, and then realize to TiO2The regulation and control of carrier concentration in film, obtain the bigger rate of change between high low resistance state.
TiO can be realized by the extra electric field write between electrode2Film reads a variety of resistance states between electrode, enters
And realize the storage of multiple resistance states.Different resistance states are encoded, realize long number information storage, it is this
The storage of multivalue is realized on same unit, it will greatly improve the density of information storage.
Advantages of the present invention：
The present invention is using typically conventional pulsed laser deposition growing method, in the conventional ferroelectricity list that can directly buy
On brilliant substrate, TiO is grown2Film, then make variable-resistance memory unit.The variable-resistance memory unit can pass through at ambient temperature
The write signal of different size voltage, the resistance of change resistance layer is energized into different states, and different resistance states can be with
It is prolonged at ambient temperature to keep, it is a kind of non-volatile storage mode.Different resistance states are subjected to coding real
The information storage of existing long number, it will greatly improve the density of information storage.The variable-resistance memory unit, it is simple in construction, stably
Property it is strong, low manufacture cost can be compatible with current CMOS technology.
Brief description of the drawings
Fig. 1 is the structural representation of the multilevel memory cell of the present invention based on ferroelectricity hetero-junctions；
Each several part is entitled：Write hearth electrode 1, ferro-electricity single crystal substrate 2, TiO2Film change resistance layer 3, write-in top electrode 4, reading
Power taking pole 5；
Under Fig. 2 room temperature conditions, the multilevel memory cell of ferroelectricity hetero-junctions of the invention (is respectively under different write-in voltages
35V, 50V, 60V, 100V, 150V, 200V, 300V) cyclic curve；
Under Fig. 3 is room temperature condition, the multilevel memory cell of ferroelectricity hetero-junctions of the invention under different write-in voltages (respectively
For 35V, 50V, 60V, 100V, 150V, 200V, 300V) on-off ratio curve；
Under Fig. 4 is room temperature condition, the multilevel memory cell of ferroelectricity hetero-junctions of the invention is under ± 60V pulses write-in voltage
Storage characteristics test chart；
Under Fig. 5 is room temperature condition, the multilevel memory cell of ferroelectricity hetero-junctions of the invention is under ± 70V pulses write-in voltage
Storage characteristics test chart.
Under Fig. 6 is room temperature condition, the retention performance test chart after resistance write-in.
Embodiment
Embodiment 1
Step 1：The cleaning of ferro-electricity single crystal substrate.
Ferro-electricity single crystal substrate is from the 0.7Pb (Mg that surface normal direction is the 0.5mm thickness that (001) is orientated1/3Nb2/3)O3/
0.3PbTiO3Single-sided polishing monocrystal chip.Acetone, ethanol and deionized water is used alternatingly to be cleaned by ultrasonic, makes ferro-electricity single crystal
Substrate surface is pollution-free.
Step 2：The TiO with Lacking oxygen is prepared based on pulsed laser deposition on ferro-electricity single crystal substrate2Film is used as resistance
Change layer.
Select TiO2(purity>99.9%) ceramics are used as target material, 0.7Pb (Mg1/3Nb2/3)O3/0.3PbTiO3For ferroelectricity
Monocrystal chip, target is 60mm apart from the spacing of ferroelectricity monocrystal chip.Partial pressure of oxygen and ferro-electricity single crystal the substrate temperature difference of deposition
For 0.1Pa and 700 DEG C, the frequency of KrF pulse lasers is 4Hz, and sedimentation time is 0.5 hour, ferro-electricity single crystal base after the completion of deposition
Piece naturally cools to room temperature.Prepared TiO2The thickness of film is 40nm.
Step 3：Hearth electrode and top electrode are prepared, variable-resistance memory unit is constituted.
In TiO2Film surface covers the mask of electrode, and by way of vacuum thermal evaporation plated film, argent is deposited
To TiO2Film surface prepares write-in top electrode, and (4 strip electrodes, length is 3mm, and width is 0.5mm, electrode with electrode is read
Spacing is 1mm, and thickness of electrode is 30nm).At the back side of ferro-electricity single crystal substrate the write-in hearth electrode (thickness of electrode is prepared with silver paste
For 50 μm), two are read electrode and are connected via wires on the resistance measurement element (Keithley2400 digital sourcemeters) of outside, are write
Enter top electrode and write-in hearth electrode is connected via wires on the voltage output component (Keithley6487 voltage sources) of outside, from
And obtain described resistor-type multilevel memory cell.
Memory cell provided by the present invention based on ferroelectricity hetero-junctions, is that a kind of can realize the non-volatile of multilevel storage
Property memory cell., can be in TiO when by writing electrode additional different size of electric field pulse under room temperature condition2On film
Realize different resistance states, it is possible to the size of the resistance is read by reading electrode.Using between high-impedance state and low resistance state
The ratio of resistance characterize the on-off ratio of memory cell.
With reference to shown in Fig. 2, at ambient temperature, the Nonvolatile resistance with multilevel storage characteristic based on ferroelectricity hetero-junctions
Become memory cell, pass through the scanning in the write-in additional different size of electrode (35V, 50V, 60V, 100V, 150V, 200V, 300V)
Voltage signal, is circulated (mode of circulation is 0 → V → 0 →-V → 0), different size of cyclical voltage low resistance state
Size is basically identical, and high-impedance state differs greatly, you can different to be energized into resistive element using different write-in voltage
High-impedance state, and the high-impedance state of resistive element can keep after external voltage is removed.With reference to shown in Fig. 3, additional write in difference
Enter under voltage, on-off ratio (resistance of resistance/low resistance state of the high-impedance state) change of high low resistance state.It can be seen that with write-in voltage
Increase, the on-off ratio between high low resistance state gradually increases.Resistive element thus can be realized using different write-in voltage
Multilevel storage.
With reference to shown in Fig. 4, at ambient temperature, the Nonvolatile resistance with multilevel storage characteristic based on ferroelectricity hetero-junctions
Become memory cell, during by adding as the voltage pulse signal of+60 volts outside write-in electrode, the resistance of memory cell is high-impedance state,
During by adding as the voltage pulse signal of -60 volts outside write-in electrode, the resistance of memory cell returns to initial low resistance state, height
The on-off ratio of resistance state is 10.5.And after positive negative pulse stuffing is alternately written into, on-off ratio keeps stable.
With reference to shown in Fig. 5, at ambient temperature, base provided by the present invention has multilevel storage based on ferroelectricity hetero-junctions
The Nonvolatile resistance variation memory cell of characteristic outside write-in electrode when by adding as the voltage pulse signal of+70 volts, and storage is single
The resistance of member is high-impedance state, and during by adding as the voltage pulse signal of -70 volts outside write-in electrode, the resistance of memory cell is returned to
Initial low resistance state, the on-off ratio of high low resistance state is 17.And after positive negative pulse stuffing is alternately written into, on-off ratio keeps stable.
It is at ambient temperature, provided by the present invention to have multilevel storage special based on ferroelectricity hetero-junctions with reference to shown in Fig. 6
Property Nonvolatile resistance variation memory cell resistance by write-in electrode outside add as+125V volt voltage pulse signal after,
The high-impedance state of memory cell is 10 megohms, and after adding as the voltage pulse signal of -125V volts outside write-in electrode, storage is single
Member returns to initial low resistance state, and the high-impedance state and low resistance state can keep stable in the range of longer time, show this
The characteristics of resistive characteristic that memory cell has has good non-volatile.
The resistance of film in memory cell can be modulated to not by different size of write-in voltage pulse as can be seen here
With the state of size.Different resistance states are subjected to coding and realize that the information of long number is stored, and not exclusively conventional store
Its non-"ON" is that "Off" can only realize binary storage.This storage that multivalue is realized on same unit, it will greatly carry
The density of high information storage.
Claims (6)
1. a kind of non-volatile variable-resistance memory unit with multilevel storage characteristic based on ferroelectricity hetero-junctions, it is characterised in that：By
Write hearth electrode, ferro-electricity single crystal substrate, change resistance layer and top electrode composition；Write following table of the hearth electrode preparation in ferro-electricity single crystal substrate
Face；Being prepared in the upper surface of ferro-electricity single crystal substrate has TiO2Film change resistance layer, thickness is 10~70nm；In TiO2Film change resistance layer
Upper preparation has top electrode, and top electrode is made up of four strip electrodes, and middle two strip electrodes are the reading electrode of resistance states,
Two strip electrodes being symmetrically distributed in the outside for reading electrode are write-in top electrode, are connected with outer lead；Or top electrode
It is made up of an annular electrode and two strip electrodes, annular electrode symmetrical ring is around being distributed in around two strip electrodes, ring
Shape electrode is write-in top electrode, and two strip electrodes are the reading electrode of resistance states；Write top electrode and write-in hearth electrode one
Act the write-in electrode for constituting resistance states.
2. a kind of non-volatile resistance-change memory list with multilevel storage characteristic based on ferroelectricity hetero-junctions as claimed in claim 1
Member, it is characterised in that：Hearth electrode and top electrode are write in elemental metals material, metal alloy compositions, conductive metallic compound
One or more be made.
3. a kind of non-volatile resistance-change memory list with multilevel storage characteristic based on ferroelectricity hetero-junctions as claimed in claim 1
Member, it is characterised in that：Ferro-electricity single crystal substrate is BaTiO3、BaxSr1-xTiO3、LiNbO3Or (1-x) Pb (Mg1/3Nb2/3)O3/
xPbTiO3, wherein 0 ＜ x ＜ 1.
4. a kind of non-volatile resistance-change memory list with multilevel storage characteristic based on ferroelectricity hetero-junctions as claimed in claim 1
Member, it is characterised in that：The thickness for writing hearth electrode is 0.1~100 μm, and the thickness of ferro-electricity single crystal substrate is 0.3~0.6mm,
The thickness of top electrode is 10~100nm.
5. a kind of non-volatile variable-resistance memory unit with multilevel storage characteristic based on ferroelectricity hetero-junctions described in claim 1
Preparation method, its step is as follows：
(1) cleaning of ferro-electricity single crystal substrate
Ferro-electricity single crystal substrate is cleaned by ultrasonic using acetone, ethanol and deionized water successively, or uses plasma cleaning
Machine is cleaned, and makes monocrystal chip surface no-pollution；
(2) pulsed laser deposition has the TiO of Lacking oxygen on ferro-electricity single crystal substrate2Film is used as change resistance layer
With pulsed laser deposition technique, the TiO of high-purity is selected2Ceramics are as target material, in ferro-electricity single crystal base under oxygen atmosphere
TiO of the deposition with Lacking oxygen on piece2Ferro-electricity single crystal substrate is naturally cooled into room temperature after the completion of film, deposition；
(3) prepare electrode and obtain multivalue variable-resistance memory unit；
The preparation method of electrode is vacuum coating, magnetron sputtering, laser deposition or method for printing screen；Hearth electrode is all covered
The bottom surface of ferro-electricity single crystal substrate, top electrode is prepared in TiO2Film surface；The reading electrode of resistance states is connected to the electricity of outside
Hinder on measuring cell, the write-in electrode of resistance states is connected on the voltage output component of outside；It is based on so as to prepare
The non-volatile variable-resistance memory unit with multilevel storage characteristic of ferroelectricity hetero-junctions.
6. a kind of non-volatile variable-resistance memory unit with multilevel storage characteristic based on ferroelectricity hetero-junctions described in claim 5
Preparation method, it is characterised in that：TiO2Ceramic target is apart from the oxygen that the spacing of ferroelectricity monocrystal chip is in 50~60mm, chamber
Partial pressure is 0.05~1Pa, and ferro-electricity single crystal substrate temperature is 650~750 DEG C, and the frequency of pulse laser is 1~4Hz, sedimentation time
For 0.5~2 hour.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107681016A (en) * | 2017-09-19 | 2018-02-09 | 北京师范大学 | Voltage-controlled, photoconductive thin-film device and control method in positive and negative reversible change |
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| CN108054277A (en) * | 2017-12-25 | 2018-05-18 | 扬州大学 | BaTiO3The preparation method of base superelevation on-off ratio resistive device |
| CN108328565A (en) * | 2018-02-07 | 2018-07-27 | 华中科技大学 | A kind of device based on controllable nano crackle and preparation method thereof and control method |
| WO2022104742A1 (en) * | 2020-11-20 | 2022-05-27 | 华为技术有限公司 | Ferroelectric memory and electronic device |
| CN112510147A (en) * | 2020-12-04 | 2021-03-16 | 武汉理工大学 | Full-inorganic quantum dot-based resistive random access memory and preparation method thereof |
| CN113113536A (en) * | 2021-04-07 | 2021-07-13 | 中国石油大学(华东) | Transparent multi-value nonvolatile resistance change memory unit and preparation method thereof |
| WO2024000324A1 (en) * | 2022-06-29 | 2024-01-04 | 华为技术有限公司 | Ferroelectric memory array and preparation method therefor, and memory and electronic device |
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