CN106992212A - 具有增大的栅‑漏电容的晶体管器件 - Google Patents

具有增大的栅‑漏电容的晶体管器件 Download PDF

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CN106992212A
CN106992212A CN201611080618.9A CN201611080618A CN106992212A CN 106992212 A CN106992212 A CN 106992212A CN 201611080618 A CN201611080618 A CN 201611080618A CN 106992212 A CN106992212 A CN 106992212A
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transistor device
drift region
type
area
compensating basin
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CN106992212B (zh
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A.马穆德
E.维西诺巴斯克斯
A.维尔梅罗特
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Infineon Technologies Austria AG
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Abstract

本发明涉及具有增大的栅‑漏电容的晶体管器件。公开了一种晶体管器件。该晶体管器件包括：半导体本体，具有有源区和焊盘区；至少一个晶体管单元，包括通过栅电介质与本体区介质绝缘的栅电极，其中本体区布置在有源区中；电极层，布置在焊盘区上方并且通过另外的电介质与焊盘区介质绝缘；以及栅焊盘，布置在电极层上方并且电气连接到至少一个晶体管单元的栅电极和电极层。另外的电介质的厚度等于或小于栅电介质的厚度。

Description

具有增大的栅-漏电容的晶体管器件
技术领域
本公开大体涉及晶体管器件，特别涉及超结晶体管器件。
背景技术
具有绝缘栅电极的场效应控制的晶体管器件被广泛地用作汽车、工业、家庭或消费者电子应用中的电子开关。这些晶体管器件有几伏特和几千伏之间的电压阻断能力。具有绝缘栅电极的场效应控制的晶体管器件包括第一掺杂类型（导电类型）的源区，其在与第一掺杂类型互补的第二掺杂类型的本体区中。第一导电类型的漂移区邻接本体区并且位于本体区与漏区之间。栅电极邻近本体区，通过栅电介质与本体区介质绝缘，并且用来控制源区和漂移区之间的本体区中的传导通道。这种类型的晶体管器件通常被称为MOS（金属氧化物半导体）晶体管器件，尽管栅电极未必包括金属并且栅电介质未必包括氧化物。MOS晶体管器件的示例包括MOSFET（金属氧化物场效应晶体管）和IGBT（绝缘栅双极型晶体管）。
MOS晶体管器件的设计中的一个挑战是在给定电压阻断能力下实现低面积特定导通电阻（R0N·A）。该面积特定导通电阻是导通状态中的晶体管器件的欧姆电阻（R0N）与芯片面积（A）的乘积。
随着面积特定导通电阻的改进，在给定导通电阻和给定电压阻断能力下，芯片面积（芯片尺寸）变得更小。芯片面积的减小还导致电容的减小，诸如栅-源电容和栅-漏电容。那些电容影响晶体管器件的切换速度。切换速度是晶体管器件从导通状态到关断状态以及在另一方向上切换得多快的度量。减小的电容使得晶体管器件切换得更快。晶体管器件的快速切换与跨晶体管器件的电压、跨晶体管器件所操作的负载的电压或者通过晶体管器件的电流的陡峭边缘相关联。那些陡峭边缘关于电磁干扰可能是关键的。
因此，可能所期望的是在晶体管器件中具有低导通电阻以软化切换行为。
发明内容
一个示例涉及一种晶体管器件。该晶体管器件包括具有有源区和焊盘区的半导体本体、至少一个晶体管单元、电极层和栅焊盘。至少一个晶体管单元包括通过栅电介质与本体区介质绝缘的栅电极，其中本体区布置在有源区中。电极层布置在焊盘区上方并且通过另外的电介质与焊盘区介质绝缘。栅焊盘布置在电极层上方并且电气连接到电极层和至少一个晶体管单元的栅电极。另外的电介质的厚度等于或小于栅电介质的厚度。
附图说明
以下参照附图解释示例。附图用来图示某些原理，使得仅图示了对于理解这些原理所必要的方面。附图未必成比例。在附图中，相同参考符号表示同样特征。
图1示出了根据一个示例的包括有源区和焊盘区的晶体管器件的竖直横截面视图；
图2示出了根据一个示例的在图1中示出的类型的晶体管器件的水平横截面视图；
图3示出了根据另一个示例的在图1中示出的类型的晶体管器件的水平横截面视图；
图4A-4B示出了在图1中示出的类型的一个晶体管器件的区段的水平横截面视图；
图5A-5B示出了在图1中示出的类型的晶体管器件的边缘区中的一个区段的水平横截面视图（图5A）和竖直横截面视图（图5B）；
图6A-6B示出了在图1中示出的类型的一个晶体管器件的区段的水平横截面视图；
图7-9示意性图示了根据不同示例的晶体管器件的有源区和焊盘区中的掺杂轮廓；
图10示出了根据一个示例的焊盘区的一个区段的竖直横截面视图；
图11示出了根据另一个示例的焊盘区的一个区段的竖直横截面视图；
图12-15示出了在图11中示出的类型的焊盘区的不同示例的水平横截面视图；
图16示出了根据另一个示例的焊盘区的竖直横截面视图；
图17示出了在图16中示出的类型的焊盘区的水平横截面视图；
图18示出了根据一个示例的焊盘区的水平横截面视图；以及
图19示出了根据又一个示例的焊盘区的竖直横截面视图。
具体实施方式
在以下详细描述中，对附图进行参照。附图形成描述的部分并且通过图示的方式示出了其中可以实践本发明的特定实施例。要理解到，本文描述的各种实施例的特征可以彼此组合，除非另外特别指出。
图1示出了根据一个示例的晶体管器件的一个区段的竖直横截面视图。晶体管器件包括具有有源区110和焊盘区120的半导体本体100。半导体本体100可以包括常规半导体材料，诸如例如硅（Si）、碳化硅（SiC）、氮化镓（GaN）、砷化镓（GaAs）等。在图1中，示出了有源区110的区段和焊盘区120的邻接区段。在有源区110中，晶体管器件包括具有栅电极41的至少一个晶体管单元，栅电极41通过栅电介质31与本体区21介质绝缘。本体区21是半导体本体100的有源区110中的掺杂半导体区。在图1中示出的示例中，栅电极布置在半导体本体100的第一表面101上方。然而，这仅仅是示例。根据另一个示例（未示出），栅电极是位于从第一表面延伸到半导体本体中的沟槽中的沟槽电极。
参照图1，电极层42布置在半导体本体100的焊盘区120上方并且通过另外的电介质34与焊盘区120介质绝缘。在下文中，电极层42被称为焊盘电极并且另外的电介质层34被称为焊盘电介质。栅焊盘52布置在栅电极层42上方。栅焊盘52电气连接到焊盘电极层42和至少一个晶体管单元的栅电极41。那些连接仅示意性地被图示在图1中。以下进一步解释可以如何实现栅电极41与栅焊盘52之间以及栅焊盘层42与栅焊盘52之间的那些连接的示例。
焊盘电介质34的厚度等于或小于栅电介质31的厚度。焊盘电介质34的厚度限定焊盘区120中的半导体本体100的第一表面101和焊盘电极层42之间的最短距离。栅电介质31的厚度限定栅电极41和本体区21之间的最短距离。
在图1中示出的半导体器件还包括漂移区11。漂移区11邻接至少一个晶体管单元的本体区21并且与本体区21形成pn结。参照图1，漂移区11布置在有源区110和焊盘区120中。漂移区11布置在漏区13和至少一个晶体管单元的本体区21之间。漏区13可以邻接漂移区11（如示出）。根据另一个示例（未示出），具有与漂移区11相同的掺杂类型但是比漂移区11更高掺杂的场停止区布置在漂移区11和漏区13之间。此外，晶体管器件在有源区110中包括与漂移区11的掺杂类型互补的掺杂类型的至少一个补偿区22，并且可以在焊盘区120中包括与漂移区11的掺杂类型互补的掺杂类型的至少一个补偿区23。在下文中，有源区110中的补偿区22被称为第一类型补偿区，并且焊盘区120中的补偿区22被称为第二类型补偿区。根据一个示例，至少一个第一类型补偿区22邻接至少一个晶体管单元的本体区21。根据一个示例，晶体管器件包括多个晶体管单元，并且每一个晶体管单元包括邻接相应晶体管单元的本体区21的补偿区22。在作为与第一表面101垂直的方向的半导体本体100的竖直方向上，至少一个第一类型补偿区22和可选的至少一个第二类型补偿区23朝向漏区13延伸。根据一个示例，第一类型补偿区22和第二类型补偿区与漏区13间隔开，使得在漏区13与第一类型和第二类型补偿区22,23之间存在漂移区11的区段。
参照图1，晶体管器件还包括源电极51。源电极51电气连接到至少一个晶体管单元的本体21和源区12。该源电极51形成源节点S或者电气连接到晶体管器件的源节点S。栅焊盘52形成栅节点G或者电气连接到晶体管器件的栅节点G。晶体管器件还包括电气连接到漏区13的漏节点D。电气连接到漏区13的漏电极可以形成漏节点D。然而，这样的漏电极未被明确示出在图1中。
晶体管器件可以是n型晶体管器件或者p型晶体管器件。器件类型由源区12的掺杂类型限定。在n型晶体管器件中，源区11是n型区，本体区21是p型区，具有与本体区21的掺杂类型互补的掺杂类型的漂移区11是n型区，至少一个第一类型补偿区22是p型区，并且可选的至少一个第二类型补偿区23是p型区。在p型晶体管器件中，源区12是p型区，本体区21是n型区，漂移区11是p型区，至少一个第一类型补偿区22是n型区，并且可选的至少一个第二类型补偿区23是n型区。晶体管器件可以被实现为MOSFET或IGBT。在MOSFET中，漏区13具有与漂移区11相同的掺杂类型，并且在IGBT中，漏区13（其还可以被称为集电极区）具有与漂移区11的掺杂类型互补的掺杂类型。例如，漏区13的掺杂浓度选自1E18和1E19 cm-3之间的范围，漂移区11和补偿区23的掺杂浓度选自1E15和5E16 cm-3之间的范围，并且本体区21的掺杂浓度选自8E16 cm-3和2E17 cm-3之间。
图2示出了根据一个示例的总体晶体管器件的顶视图，并且图3示出了根据另一个示例的总体晶体管器件的顶视图。在这些示例中的每一个中，半导体本体100基本上具有矩形形状。在图2中示出的示例中，栅焊盘52位于邻近半导体本体100的四个角落之一。键合导线B可以连接到栅焊盘52。键合导线B可以用来将栅焊盘52电气连接到其它电路元件（未示出）或者电气连接到从外壳（封装）突出的端子（未示出），半导体本体100可以布置在外壳（封装）中。在图3中示出的示例中，栅焊盘52与半导体本体100的角落间隔开，但是仍旧接近半导体本体100的边缘102。“边缘”102在横向方向上终止半导体本体100，横向方向是与以上解释的竖直方向垂直的方向。
图4A示出了一个示例晶体管器件的有源区110的一个区段在第一截平面B-B中的水平横截面视图，并且图4B示出了示例晶体管器件的有源晶体管器件110的一个区段在第二截平面C-C中的水平横截面视图。第一截平面B-B接近于第一表面101而延伸通过半导体本体100，并且第二截平面C-C延伸通过栅电极51。图4A示出了两个晶体管单元的源区12和本体区21。在该示例中，源区12和本体区21是伸长的半导体区。对应的晶体管单元在下文中被称为伸长的晶体管单元或者条带（stripe）单元。参照图1，源电极51通过电极区段电气连接到个体晶体管单元的本体区21和源区12，电极区段在竖直方向上通过电介质层32、栅电极41和栅电介质31而延伸到半导体本体100中。电介质层32将栅电极41与源电极51分离。电极区段53在下文中被称为源通孔。在图4A-4B中示出的实施例中，这些源通孔53，比如源区12和本体区21，是伸长的源通孔。这些伸长的源通孔53通过电介质33与栅电极41介质绝缘，并且在几个伸长的栅电极区段中细分平面栅电极41。
参照图5A，其示出了半导体本体100的边缘区中的有源区110的一个区段的水平横截面视图，伸长的栅电极41区段可以在横向方向上延伸超出源电极51。半导体本体100的“边缘区”是接近于半导体本体100的边缘102的区。在图5A中，未示出源电极，因为在图5A中图示的截平面C-C没有延伸通过源电极51。然而，源电极52的外边缘的位置在图5A中通过点划线图示。源电极51的“外边缘”在横向方向上终止源电极。在该示例中，伸长的栅电极41区段通过栅流道（runner）54电气连接到栅焊盘52，栅流道54在图2和3中以点线来图示。该栅流道54可以围绕源电极51并且与源电极51介质绝缘。栅流道54在图5A中看不到。在图5A中以54标记的点线表示栅流道54的内边缘。栅流道54的“内边缘”是面向源电极51的栅流道的边缘。
图5B示出了栅流道54在图5A中示出的截平面E-E中的竖直横截面视图。参照图5B，栅流道54可以通过栅通孔55而连接到栅电极区段41，栅通孔55在竖直方向上从栅流道54延伸到个体栅电极区段41。与源电极51类似，栅流道54可以布置在电介质层35上方，其中栅通孔55从栅流道54通过该电介质层35延伸到个体栅电极41区段。以其中栅电极41区段连接到栅流道44的相同方式，焊盘电极层42可以连接到栅焊盘52。也就是说，晶体管器件可以包括栅焊盘52下方的栅通孔，其通过电介质层35延伸到电极层42。
栅流道44是可选的。在其中栅电极41和焊盘电极层42形成连续电极层的那些示例中，栅流道54可以被省略，并且可能足以通过焊盘区120中的栅通孔（也就是说，通过栅焊盘52和电极层42之间的栅通孔）将该连续电极层电气连接到栅焊盘52。
图6A-6B示出了另一个晶体管器件分别在截平面B-B和C-C中的水平横截面视图。在该晶体管器件中，个体晶体管单元的本体区21和源区12基本上在水平平面中为矩形。个体源通孔53彼此间隔开，使得栅电极41形成有源区110中的连续电极层。后者可以从图6B看出。栅电极41邻接例如如图1中示出的焊盘电极层42，使得栅电极41和焊盘电极层42形成连续电极层。在该晶体管器件中，栅流道54是可选的。应当指出的是，利用矩形形状实现本体区21和源区12仅仅是一个示例。也可以使用可替换的形状，诸如六边形形状、任何其它多边形形状或椭圆形状。
在下文中解释本文之前解释的半导体器件的一种操作方式。可以像常规MOS晶体管那样操作晶体管器件。也就是说，可以通过在栅节点G和源节点S之间应用适当驱动电压VGS（参见图1）而接通和关断晶体管器件。当驱动电压VGS使得在源区12和漂移区11之间的本体区21中存在传导通道时，晶体管器件处于导通状态。在晶体管器件的导通状态中，当在漏节点D和源节点S之间应用适当电压VDS时，电流可以在漏节点D和源节点S之间流动。当驱动电压VGS使得在源区12和漂移区11之间的本体区21中不存在传导通道时，晶体管器件处于关断状态。如果在关断状态中在漏节点D和源S之间应用反向偏置本体区21和漂移区11之间的pn结的电压VDS，则空间电荷区（耗尽区）在pn结处开始在漂移区11中扩展。如果例如晶体管器件是n型晶体管器件，则当在漏节点D和源节点S之间应用正电压VDS时，pn结反向偏置。
在关断状态中，漏节点D和栅节点G之间的电压不同于零。这使得为晶体管器件的栅-漏电容CGD充电。“栅-漏电容”是在栅节点G和漏节点D之间电气有效（active）的电容。这样的栅-漏电容CGD的电路符号被图示在图1中。参照图1，该栅-漏电容CGD包括焊盘区120中的焊盘电极层42和栅焊盘52作为第一电容器电极、焊盘区120中的半导体本体100和电极层42之间的焊盘电介质34作为电容器电介质、以及焊盘区120中的漏区130和漂移区11作为第二电容器电极。该栅-漏电容CGD的电容值尤其取决于焊盘区120的面积的大小和电介质层34的厚度。该电容值随着面积大小的增大而增大，并且随着电介质层34的厚度的减小而增大。凭借焊盘电介质34具有等于或小于栅电介质31的厚度的厚度，可以获得栅-漏电容CGD的相对高电容值。根据一个示例，厚度选自20纳米（nm）和200纳米之间的范围，特别地在80纳米和120纳米之间。鉴于晶体管器件的软切换行为，薄焊盘电介质是有益的。栅-漏电容CGD的电容值越高，栅-漏电容CGD在晶体管器件从关断状态切换到导通状态时放电就花费时间越长，并且晶体管器件从关断状态改变成导通状态就花费时间越长。这花费时间越长，晶体管器件的切换行为就越软。
在图1中示出的实施例中，焊盘区120中的半导体本体100内部的器件结构类似于有源区110中的器件结构，并且与有源区110中的器件结构的仅有不同在于，在焊盘区220中不存在本体和源区。在该示例中，漂移区11的掺杂浓度N11可以在有源区110和焊盘区120中相同。此外，第一类型补偿区22的掺杂浓度N22可以等于第二类型补偿区的掺杂浓度N23。这被图示在图7中，图7示意性图示了在图1中示出的第一横向方向x上的水平截平面D-D中的掺杂浓度。漂移区11的掺杂浓度N11可以选自以上解释的范围，并且第一类型补偿区23的掺杂浓度N22、N23可以选自以上解释的范围。
然而，以与有源区110中的基本上相同的器件结构和相同的掺杂参数实现焊盘区120中的器件结构仅仅是示例。可以如何实现焊盘区120中的器件结构的其它示例以下参照本文中的图8-19进行解释。
根据图8中示出的一个示例，漂移区11在焊盘区120中具有比有源区110中更低的掺杂浓度。在图8中，N111表示有源区110中的掺杂浓度，并且N112表示焊盘区120中的掺杂浓度。根据一个示例，有源区110中的漂移区11的掺杂浓度N111和焊盘区120中的漂移区11的掺杂浓度N112之间的比率N111/N112高于1.25、高于2.5、高于10或者高于100。在图8中示出的示例中，第二类型补偿区23的掺杂浓度N23低于第一类型补偿区22的掺杂浓度N22。根据一个示例，比率N22/N23高于2.5、高于10或者高于100。
参照图1，漂移区11包括分别布置在补偿区22和23之间的漂移区区段，以及位于补偿区22,23和漏区13之间的漂移区区段113。根据一个示例，该漂移区区段113具有比有源区110中的补偿区22之间的漂移区11更低的掺杂浓度。根据一个示例，比率N111/N113在2和10之间，其中N111是在补偿区22之间和有源区110中的漂移区11中的掺杂浓度N111，并且N113是位于补偿区22,23和漏区13之间的漂移区区段113中的掺杂浓度。参照图1，具有较低掺杂浓度的该区段113可以是在水平方向上在有源区110和焊盘区120上方延伸的连续区。这样的区段113仅被示出在图1中，但是可以被实现在本文解释的每一个示例中。
根据图9中示出的另一个示例，漂移区11基本上在焊盘区120中是固有的。也就是说，漂移区11的有效掺杂浓度低于1E13cm-3。有效掺杂浓度由n型浓度和p型浓度的差异给定。固有漂移区11的有效掺杂浓度可以是n型或p型掺杂浓度。根据一个示例，焊盘区120中的固有漂移区11通过为p型掺杂剂和n型掺杂剂提供基本上相同的掺杂浓度（使得差异小于1E13cm-3）而获得。例如，该掺杂浓度高于1E15cm-3。此外，在该示例中，在焊盘区120中不存在第二类型补偿区。
根据图9中示出的一个示例，焊盘电极层42和半导体本体100的第一表面101之间的电介质层34可以包括其中该电介质层34的厚度比其它区段中的更高的一个或多个区段。图10示出了其中电介质层34的厚度为d1的一个区段，以及其中厚度为d2的另一个区段，其中d1＜d2。在下文中，具有第一厚度的区段被称为第一区段，并且具有第二厚度d2的区段被称为第二区段。第一区段中的厚度d1等于栅电介质31的厚度或者小于栅电介质31的厚度。第二区段中的厚度d2高于栅电介质31的厚度。根据一个示例，厚度d2在栅电介质31的厚度的1.1倍与2微米之间。
根据一个示例，并且如图1中示出的，第一类型补偿区22经由本体区21、源通孔53和源电极51而电气连接到源节点S。第二类型补偿区23可以是浮置的，使得它们没有通过其掺杂类型的半导体区连接到源节点S或漏节点D。当晶体管器件处于关断状态并且在漏节点D和源节点S之间应用电压VDS时，空间电荷区不仅在本体区21和漂移区11之间的pn结处开始在漂移区11中扩展，而且在漂移区11和补偿区22,23之间的pn结处开始在漂移区11和补偿区22,23中扩展。因而，在晶体管器件的关断状态中，漂移区11和补偿区22,23中的掺杂剂原子被电离。这等同于补偿区22,23在晶体管器件的关断状态中充电。当晶体管器件从关断状态切换到导通状态时，补偿区22,23需要放电以便使晶体管器件实现低导通电阻。“导通电阻”是在导通状态中漏节点D和源节点S之间的晶体管器件的电阻。第一类型补偿区22通过连接到源节点S而放电。浮置的第二类型补偿区23可以仅经由漂移区11而放电。这可能花费一些时间并且可能进一步延迟从关断状态向导通状态的转移并且引起附加电气损耗。
在其中这样的延迟不可接受的情况下，可以采取措施以在晶体管器件从关断状态切换到导通状态时促进使第二类型补偿区23放电。根据图11中示出的一个示例，晶体管器件包括与第二类型补偿区23相同的掺杂类型的放电区24。这些放电区邻接第二类型补偿区23并且可以布置在第二类型补偿区23与半导体本体100的第一表面101之间。这些放电区24具有比第二类型补偿区23更高的掺杂浓度。例如，这些放电区14的掺杂浓度选自8E16 cm-3和2E17 cm-3之间。
图12示出了延伸通过放电区24的截平面F-F中的水平横截面视图。放电区24下方的第二类型补偿区23的位置以点线被图示在图12中以及以下解释的图13-15中。在该示例中，第二类型补偿区23是伸长的区。放电区24也是伸长的半导体区并且可以沿个体第二类型补偿区23的完整长度延伸。
图13示出了根据另一个示例的晶体管器件的焊盘区120的一个区段的水平横截面视图。在该示例中，第二类型补偿区23（比如在图12中示出的示例中）是伸长的半导体区。放电区24也是伸长的半导体区，但是跨第二类型补偿区23延伸。也就是说，第二类型补偿区23和放电区24之间的角度不同于零。在图13中示出的示例中，这些角度基本上是直角。然而，这仅仅是示例。可以使用0°和90°之间（特别是在45°和90°之间）的任何角度。
图14示出了将图12和13中示出的示例进行组合的示例。在图14中示出的示例中，晶体管器件包括各自沿第二类型补偿区23中的相关联的一个延伸的若干放电区24，以及跨第二类型补偿区23延伸的若干放电区24。一般地，存在沿相关联的第二类型补偿区23的长度的至少一部分延伸的至少一个放电区24，并且存在跨两个或更多个相关联的第二类型补偿区23延伸的至少一个放电区24。
图15示出了放电区24的另一个示例。在该示例中，放电区24具有网格形状，使得放电区24的区段沿第二类型补偿区23延伸并且其它区段跨第二类型补偿区23延伸。
图16示出了根据另一个示例的晶体管器件的竖直横截面视图。在该示例中，晶体管器件包括与漂移区11相同掺杂类型但是比漂移区11更高掺杂的放电区14。例如，这些放电区14的掺杂浓度选自8E16cm-3和2E17cm-3之间。这些放电区14可以邻接焊盘区120中的第一表面101并且邻近补偿区23。图17示出了在图16中示出的类型的一个示例晶体管器件的截平面F-F中的水平横截面视图。在该示例中，放电区14是基本上与伸长的第二类型补偿区23平行地延伸的伸长区。在晶体管器件的导通状态中，至少在接近于有源区110的区中的这些放电区14可以承载负载电流的一部分并且因此可以有助于减小导通电阻。
图18示出了根据另一个示例的晶体管器件的竖直横截面视图。在该示例中，焊盘区120中的第二类型补偿区23具有不同长度。一个第二类型补偿区23的“长度”是半导体本体的竖直方向上（也就是说，在与第一表面101垂直的方向上）的第二类型补偿区23的尺度。根据一个示例，第二类型补偿区23和有源区110之间的横向方向上的距离越长，相应补偿区23的长度就越短。也就是说，个体第二类型补偿区23的长度朝向焊盘区120的中心而减小。“焊盘区120的中心”是最远离有源区110的焊盘区120的区段。
图19示出了根据另一个示例的焊盘区120的一个区段的竖直横截面视图。在该示例中，焊盘区120包括其中省略补偿区23的漂移区11的区段11'。该区11'的掺杂浓度可以等于有源区110中的补偿区22之间的漂移区11的掺杂浓度N111，或者可以高于N111，诸如例如在1E15 cm-3和1E17 cm-3之间。半导体本体100可以包括漂移区区段11'和漏区13之间的参照图1解释的较低掺杂区段113。然而，这样的区段113未被示出在图19中。
漂移区区段11'可以在一侧上邻接漏区13并且在另一侧上邻接第一表面101。由于失去的补偿区23和/或更高的掺杂浓度，漂移区区段11'在晶体管器件的关断状态中不能完全耗尽，并且充当第二电容器电极的部分以及有助于进一步增大栅-漏电容CGD的电容值。在该更高掺杂的11'和有源区110之间，焊盘区120包括漂移区11的以下区段：该区段可以具有与有源区110中的漂移区11相比相同的掺杂浓度，或者具有在更高掺杂区的掺杂浓度和有源区中的漂移区11的掺杂浓度之间的掺杂浓度。此外，晶体管器件可以包括更高掺杂区11'和有源区110之间的该区段中具有不同长度的补偿区23。这些第二类型补偿区23的长度可以朝向更高掺杂区11'而减小。在该示例中，在更高掺杂区11'中不存在补偿区。第二类型补偿区23和其中嵌入第二类型补偿区23的漂移区11区段充当边缘终止部，其在晶体管器件的关断状态中吸收漂移区11的电势与更高掺杂区11'的电势之间的电压差。在关断状态中，更高掺杂区11'的电势基本上等于漏节点D的电势，而在有源区110中的漂移区11中，电势在晶体管器件的竖直方向上在接近于漏区13的区中的漏电势与接近于第一表面101的区中的源电势之间变化，使得特别地，接近于第一表面101存在有源区101和更高掺杂区11'之间的电压，其被边缘终止结构所吸收。

Claims (22)

1.一种晶体管器件，包括：
半导体本体，具有有源区和焊盘区；
至少一个晶体管单元，包括通过栅电介质与本体区介质绝缘的栅电极，其中本体区布置在有源区中；
电极层，布置在焊盘区上方并且通过另外的电介质与焊盘区介质绝缘；以及
栅焊盘，布置在电极层上方并且电气连接到至少一个晶体管单元的栅电极和电极层，
其中另外的电介质的厚度等于或小于栅电介质的厚度。
2.权利要求1的晶体管器件，包括多个晶体管单元，每一个晶体管单元包括布置在半导体本体的有源区中的本体区。
3.权利要求1或2的晶体管器件，还包括半导体本体的焊盘区和有源区中的漂移区，其中漂移区与至少一个晶体管器件的本体区形成pn结。
4.权利要求3的晶体管器件，
其中至少一个晶体管器件还包括通过本体区与漂移区分离的源区，以及通过漂移区与本体区分离的漏区。
5.权利要求3或4的晶体管器件，还包括：
有源区中的至少一个第一类型补偿区，其中至少一个第一类型补偿区邻接漂移区，并且具有与漂移区的掺杂类型互补的掺杂类型。
6.权利要求5的晶体管器件，其中至少一个补偿区邻接至少一个晶体管单元的本体区。
7.权利要求5或6的晶体管器件，还包括：
焊盘区中的至少一个第二类型补偿区，其中至少一个第二类型补偿区邻接漂移区，并且具有与漂移区的掺杂类型互补的掺杂类型。
8.权利要求7的晶体管器件，其中至少一个第二类型补偿区的形状和掺杂浓度等于至少一个第一类型补偿区的形状和掺杂浓度。
9.权利要求7的晶体管器件，其中至少一个第二类型补偿区的掺杂浓度低于至少一个第一类型补偿区的掺杂浓度。
10.权利要求9的晶体管器件，其中焊盘区的至少一个区段中的漂移区的掺杂浓度低于有源区中的漂移区的掺杂浓度。
11.权利要求9的晶体管器件，包括多个第二补偿区，其中这些补偿区中的至少一些的掺杂浓度取决于相应补偿区与有源区之间的距离，其中该距离越长，掺杂浓度就越低。
12.权利要求7的晶体管器件，包括多个第二类型补偿区，其中这些第二类型补偿区中的至少一个的竖直长度低于至少一个第一类型补偿区的竖直长度。
13.权利要求12的晶体管器件，其中补偿区中的至少一些的竖直长度取决于相应补偿区与有源区之间的距离，其中该距离越长，竖直长度就越低。
14.权利要求3-13中的一个的晶体管器件，其中焊盘区中的漂移区的掺杂浓度等于有源区中的漂移区的掺杂浓度。
15.权利要求3的晶体管器件，其中焊盘区的至少一个区段中的漂移区具有比有源区中的漂移区更高的掺杂浓度。
16.权利要求13的晶体管器件，还包括：
边缘终止结构，在焊盘区中在焊盘区的至少一个区段与有源区之间。
17.权利要求16的晶体管器件，其中边缘终止结构包括至少一个补偿区，所述至少一个补偿区邻接漂移区并且具有与漂移区的掺杂类型互补的掺杂类型。
18.权利要求17的晶体管器件，包括多个补偿区，其中这些补偿区中的至少一些的竖直长度取决于相应补偿区与有源区之间的距离，其中该距离越长，竖直长度就越低。
19.权利要求7的晶体管器件，还包括：
具有与至少一个第二类型补偿区相同的掺杂类型并且比至少一个第二类型补偿区更高掺杂的放电区，
其中放电区邻接至少一个第二类型补偿区。
20.权利要求19的晶体管器件，其中放电区延伸到有源区或者延伸到有源区中。
21.权利要求19或20的晶体管器件，其中放电区邻接焊盘区中的半导体本体的表面。
22.权利要求4的晶体管器件，还包括：
掺杂区，具有与漂移区相同的掺杂类型并且具有比漂移区更高的掺杂浓度，其中所述掺杂区邻接焊盘区中的漂移区。
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