CN106981518A - A kind of SOI lateral high-voltage devices with super-junction structure - Google Patents
A kind of SOI lateral high-voltage devices with super-junction structure Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- 239000001301 oxygen Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims abstract description 5
- 238000012163 sequencing technique Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 230000005684 electric field Effects 0.000 description 31
- 238000005516 engineering process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The present invention provides a kind of SOI lateral high-voltage devices with super-junction structure, its structure cell includes substrate, substrate contact electrode, oxygen buried layer, thick soi layer, PXing Ti areas, thick dielectric layer, N-type heavily doped drain region, ultra-thin top layer silicon, NXing Tiao areas and PXing Tiao areas, p-type heavy doping body contact zone and N-type heavy-doped source polar region, gate oxide, Source contact electrode, polysilicon gate, drain contact electrode, NXing Tiao areas and PXing Tiao areas constitute super-junction structure and are alternately embedded in the thick soi layer of source-end region in Z-direction, the longitudinal direction that the present invention bears higher-pressure region by drain terminal ultra-thin top layer silicon raising device drain terminal is pressure-resistant, best transverse direction is obtained by substantial amounts of theory deduction pressure-resistant, it is significantly reduced while holding power MOS high breakdown voltages using superjunction close to source-end region simultaneously and compare conducting resistance, there is relatively low conduction loss, it is finally reached and effectively reduces device area, reduce the purpose of device cost.
Description
Technical field
The present invention relates to semiconductor power device technology field, and in particular to a kind of SOI with super-junction structure is laterally high
Voltage device.
Background technology
Compared with conventional bulk silicon technology, SOI technology have high speed, low-power consumption, high integration, minimum ghost effect with
And the advantages of good isolation characteristic, and reduce latch up effect and possess strong Radiation hardness, make the reliability of integrated circuit
Greatly improved with anti-soft error ability, be increasingly becoming the integrated electricity of manufacture high speed, low-power consumption, high integration and high reliability
The mainstream technology on road.
SOI high voltage integrated circuits (High Voltage IC, abbreviation HVIC) based on SOI lateral high-voltage devices, make
For a new and developing branch in smart-power IC (Smart Power IC, abbreviation SPIC) field, obtain in recent years fast
The development of speed.The relatively low longitudinal direction of SOI lateral high-voltage devices is pressure-resistant to limit its application in HVIC, is increased according to SOI media
(ENhanced DIelectric layer Field, abbreviation ENDIF) Universal Theory, SOI can be improved using ultra-thin top layer silicon by force
The longitudinal direction of device is pressure-resistant, but also results in larger ratio conducting resistance simultaneously.
The content of the invention
The problem of purpose of the present invention exists aiming at above-mentioned traditional lateral high-voltage device has superjunction knot there is provided one kind
The SOI lateral high-voltage devices of structure, reduce the ratio conducting resistance of device while retainer member high breakdown voltage.
For achieving the above object, technical solution of the present invention is as follows：
A kind of SOI lateral high-voltage devices with super-junction structure, its structure cell includes substrate, the substrate of substrate lower surface
Contact electrode, the oxygen buried layer of substrate top surface, the thick soi layer of oxygen buried layer upper surface, the PXing Ti areas on the left of thick soi layer, thickness SOI
Thick dielectric layer, the N-type heavily doped drain region run through along the longitudinal direction and be embedded in thick dielectric layer right-hand member inside layer, longitudinal direction are upper
The NXing Tiao areas and PXing Tiao areas, position between ultra-thin top layer silicon, PXing Ti areas and thick dielectric layer between thick dielectric layer and oxygen buried layer
Separate p-type heavy doping body contact zone and N-type heavy-doped source polar region inside PXing Ti areas, it is arranged on N-type heavy-doped source
Gate oxide, the Source contact electrode being in contact with the upper surface in PXing Ti areas, the gate oxide of polar region and PXing Ti areas upper surface
The polysilicon gate of top, the drain contact electrode for being arranged on N-type heavily doped drain region upper surface, the upper surface of the oxygen buried layer with
Thick soi layer is connected with the lower surface of ultra-thin top layer silicon, the lower surface of the thick dielectric layer and the upper surface phase of ultra-thin top layer silicon
Contact, the NXing Tiao areas and PXing Tiao areas constitute super-junction structure and are alternately embedded in Z-direction close in N-type drift region
In the thick soi layer of source-end region, the upper surface of p-type heavy doping body contact zone and N-type heavy-doped source polar region and the upper table in PXing Ti areas
Face is in contact, the left end of the right end portion covering N-type heavy-doped source polar region of the Source contact electrode, a left side for the gate oxide
The right-hand member of end part covering N-type heavy-doped source polar region, gate oxide is not in contact with Source contact electrode.
According to ENDIF Universal Theories, the longitudinal direction for improving SOI device using ultra-thin top layer silicon close to drain terminal is pressure-resistant, close to source
Hold using thick silicon layer drift region reduction device than conducting resistance, the thick soi layer of the present invention close source-end region in N-type drift region
The middle staggered NXing Tiao areas of embedded Z-direction and PXing Tiao areas constitute super-junction structure, by complicated theory deduction, draw electric field
With the new relation of doping concentration, proposed new construction is obtained, has broken power device conducting resistance and pressure-resistant 2.5 power
" the silicon limit ".
The total technical scheme of the present invention, is used first in the N-type drift region of SOI lateral high-voltage devices close to drain-end region
Part ultra-thin top layer silicon, it is theoretical according to ENDIF when drain terminal plus malleation, increased by improving the method for critical breakdown electric field of silicon
Strong oxygen buried layer electric field, so as to improve longitudinal breakdown voltage of SOI device, secondly, uses horizontal for the ultra-thin top layer silicon of drift region
To linear varying doping, improve the transverse electric field distribution close to drain terminal drift region, it is more evenly distributed, the transverse direction for improving device is hit
Wear voltage；Then close to source-end region, using thick soi layer, horizontal linear varying doping is also used for the thick soi layer in drift region, is adjusted
Control surface Electric Field Distribution, and embedded staggered NXing Tiao areas and PXing Tiao areas constitute super-junction structure in thick soi layer.Device
During forward conduction, due to greatly improving for doping concentration, under identical breakdown voltage, greatly reduce, make than conducting resistance
It significantly reduces than conducting resistance while holding power MOS high breakdown voltages, there is relatively low conduction loss,
It is finally reached and effectively reduces device area, reduces the purpose of device cost.In addition, junction extend direction, NXing Tiao areas with
PXing Ti has spacing between area.In actual process, in Withstand voltage layer central region, the power line that the ionized donor in NXing Tiao areas is sent
The ionization acceptor in PXing Tiao areas is directed to, so Withstand voltage layer central region, electric field cross stream component is caused by ionized impurity electric charge
Zero；Only in NXing Tiao areas close to the part in PXing Ti areas, the power line that ionized donor is sent points to PXing Ti areas, equally, in p-type
Bar area is close to the part of N-type heavily doped drain region, and the power line that ionization acceptor sends is pointed to close to N-type heavily doped drain region, because
This, electric field is at NXing Tiao areas and PXing Ti areas knot, A points as shown in Figure 7, and PXing Tiao areas and N-type heavily doped drain region, such as
B points shown in Fig. 7, produce electric field peak, power device can be caused to puncture in advance.
Specifically, the drain terminal of the device contains N-type buffer areas.Further regulation drain terminal bears the electric field point of higher-pressure region
Cloth.
Specifically, the NXing Tiao areas and PXing Tiao areas are unequal in the width of Z-direction.
Specifically, the length of the NXing Tiao areas and PXing Tiao areas in the Y direction is less than or equal to the thickness of thick soi layer.
Specifically, the thick soi layer of the drift region ultra-thin top layer silicon and drift region is mixed by linear varying doping or uniformly respectively
A kind of doping way in miscellaneous or discrete doping is formed；Or formed respectively by N sections of linear varying doping modes, N=1,2,3,
4……。
Specifically, be shaped as circular arc of the NXing Tiao areas close to the one end in PXing Ti areas, the PXing Tiao areas are situated between close to thick
One end of matter layer is shaped as circular arc.
Specifically, the NXing Tiao areas are rectangle, the distance in NXing Tiao areas left end and PXing Ti areas is more than PXing Tiao areas left end and P
The distance in Xing Ti areas, the PXing Tiao areas are rectangle, and the distance of PXing Tiao areas right-hand member and thick dielectric layer is more than NXing Tiao areas right-hand member and thickness
The distance of dielectric layer.
Specifically, the right-hand member of the thick dielectric layer and N-type heavily doped drain region or N-type buffer areas are tangent.
Specifically, alternate sequencing is exchanged in z-direction for the NXing Tiao areas and PXing Tiao areas.
Specifically, the device also includes M layers of field plate, M=1,2,3,4 ... ..., the surface field of further adjusting device
Distribution, makes it bear higher voltage.M concrete numerical value is specifically changed according to the need for design.
Beneficial effects of the present invention are：By complicated theory deduction, electric field and the new relation of doping concentration are drawn, is proposed
New construction involved in the present invention, has broken " the silicon limit " of power device conducting resistance and pressure-resistant 2.5 power, and the present invention is carried
A kind of SOI lateral high-voltage devices with super-junction structure supplied are embedded in the thick soi layer of source-end region in N-type drift region
The NXing Tiao areas of Z-direction alternate and PXing Tiao areas constitute super-junction structure.It is big due to doping concentration during device forward conduction
Width is improved, under identical breakdown voltage, reduction more great than conducting resistance；According to SOI medium enhancing Universal Theories, in N
The longitudinal direction for improving device using part ultra-thin top layer silicon close to drain-end region in type drift region is pressure-resistant, and to ultra-thin top layer silicon and
Horizontal linear varying doping technology is respectively adopted in thick soi layer, modulates respective surface electric field distribution, comes while producing extra electric charge
Eliminate substrate-assisted depletion effect.Breakdown voltage finally determines the minimum value in pressure-resistant, device of the present invention with laterally pressure-resistant and longitudinal direction
The advantage of part structure is that the longitudinal direction for bearing higher-pressure region by drain terminal ultra-thin top layer silicon raising device drain terminal is pressure-resistant, by a large amount of
Theory deduction obtain that best transverse direction is pressure-resistant so that the pressure-resistant of device is attained a yet higher goal.Meanwhile, adopted close to source-end region
Make it while holding power MOS high breakdown voltages with super-junction structure, significantly reduce than conducting resistance, there is relatively low
Conduction loss, be finally reached effectively reduce device area, reduce device cost purpose.
Brief description of the drawings
Fig. 1 is traditional ultra-thin SOI lateral high-voltage device schematic diagram.
Fig. 2 is a kind of SOI lateral high-voltage device schematic diagrames with super-junction structure of the present invention.
Fig. 3 is the right-hand member not structural representation tangent with N-type heavily doped drain region of thick dielectric layer in device of the present invention.
Fig. 4 is the structural representation that drain terminal contains N-type buffer areas in device of the present invention.
Fig. 5 be the present invention device in thick dielectric layer the right-hand member not structural representation tangent with drain terminal N-type buffer areas.
Fig. 6 is the structural representation that device ZhongNXing Tiao areas of the invention are in contact with PXing Tiao areas with oxygen buried layer upper surface.
Fig. 7 is the device ZhongNXing Tiao areas of the invention containing drain terminal N-type buffer areas and PXing Tiao areas and oxygen buried layer upper surface
The structural representation being in contact.
Fig. 8 is the distribution map of the electric field for producing A, B point due to the superposition of superjunction electric field in theory.
Fig. 9 is that the present invention has super-junction structure for the one kind for avoiding surface superjunction from introducing designed by two superposition of electric field peak values
SOI lateral high-voltage device schematic diagrames.
Figure 10 is that the present invention is another with superjunction designed by two superposition of electric field peak values to avoid surface superjunction from introducing
The SOI lateral high-voltage device exemplary plots of structure.
Wherein, 1 it is substrate, 2 be oxygen buried layer, 3 be ultra-thin top layer silicon, 4 be thick soi layer, 5 be thick dielectric layer, 6 is p-type bar
Area, 7 be NXing Tiao areas, 8 be PXing Ti areas, 9 be p-type heavy doping body contact zone, 10 be N-type heavy-doped source polar region, 11 be that N-type is heavily doped
Miscellaneous drain region, 12 be gate oxide, 13 be Source contact electrode, 14 be polysilicon gate, 15 be drain contact electrode, 16 be substrate
Electrode is contacted, 17 be N-type buffer areas.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Embodiment 1
As shown in Fig. 2 a kind of SOI lateral high-voltage devices with super-junction structure, its structure cell includes substrate 1, substrate 1
Substrate contact electrode 16, the oxygen buried layer 2 of the upper surface of substrate 1, the thick soi layer 4 of the upper surface of oxygen buried layer 2, the thick soi layer 4 of lower surface
Thick dielectric layer 5 inside the PXing Ti areas 8 in left side, thick soi layer 4, the N for running through along the longitudinal direction and being embedded in the thick right-hand member of dielectric layer 5
It is located at ultra-thin top layer silicon 3, PXing Ti areas 8 and thick Jie between thick dielectric layer 5 and oxygen buried layer 2 on type heavily doped drain region 11, longitudinal direction
NXing Tiao areas 7 and PXing Tiao areas 6 between matter floor 5, the separate p-type heavy doping body contact zone 9 inside PXing Ti areas 8
With N-type heavy-doped source polar region 10, it is arranged on the gate oxide 12 and p-type of N-type heavy-doped source polar region 10 and the upper surface of PXing Ti areas 8
Source contact electrode 13 that the upper surface in body area 8 is in contact, the polysilicon gate 14 of the top of gate oxide 12, to be arranged on N-type heavily doped
The drain contact electrode 15 of the miscellaneous upper surface of drain region 11, the upper surface of the oxygen buried layer 2 and thick soi layer 4 and ultra-thin top layer silicon 3
Lower surface is connected, and the lower surface of the thick dielectric layer 5 is in contact with the upper surface of ultra-thin top layer silicon 3, the NXing Tiao areas 7 and P
Xing Tiao areas 6 constitute super-junction structure and are alternately embedded in the thick soi layer 4 in N-type drift region close to source-end region in Z-direction
In, the upper surface of p-type heavy doping body contact zone 9 and N-type heavy-doped source polar region 10 is in contact with the upper surface in PXing Ti areas 8, described
The left end of the right end portion covering N-type heavy-doped source polar region 10 of Source contact electrode 13, the left end portion of the gate oxide 12
The right-hand member of N-type heavy-doped source polar region 10 is covered, gate oxide 12 is not in contact with Source contact electrode 13.
Specifically, the NXing Tiao areas 7 and PXing Tiao areas 6 and the upper surface of oxygen buried layer 2 are nontangential.
Specifically, the thick soi layer 4 of the drift region ultra-thin top layer silicon 3 and drift region passes through linear varying doping or uniform respectively
A kind of doping way in doping or discrete doping is formed；Or formed respectively by N sections of linear varying doping modes, N=1,2,
3,4 ....
Specifically, the right-hand member of the thick dielectric layer 5 and N-type heavily doped drain region 11 are tangent.
Specifically, the device also includes M layers of field plate, M=1,2,3,4 ... ..., the surface field of further adjusting device
Distribution, makes it bear higher voltage.M concrete numerical value is specifically changed according to the need for design.
According to ENDIF Universal Theories, the longitudinal direction for improving SOI device using ultra-thin top layer silicon 3 close to drain terminal is pressure-resistant, close to source
Hold reduces device than conducting resistance using thick silicon layer drift region 4, the thick SOI of the present invention close source-end region in N-type drift region
Embedded staggered NXing Tiao areas 7 and PXing Tiao areas 6 constitute super-junction structure in floor 4, by complicated theory deduction, draw electric field
With the new relation of doping concentration, proposed new construction is obtained, has broken power device conducting resistance and pressure-resistant 2.5 power
" the silicon limit ".
The total technical scheme of the present invention, is used first in the N-type drift region of SOI lateral high-voltage devices close to drain-end region
Part ultra-thin top layer silicon 3, it is theoretical according to ENDIF when drain terminal plus malleation, increased by improving the method for critical breakdown electric field of silicon
Strong oxygen buried layer electric field, so as to improve longitudinal breakdown voltage of SOI device, secondly, uses horizontal for the ultra-thin top layer silicon 3 of drift region
To linear varying doping, improve the transverse electric field distribution close to drain terminal drift region, it is more evenly distributed, the transverse direction for improving device is hit
Wear voltage；Then, using thick soi layer 4, horizontal linear varying doping is also being used for the thick soi layer 4 in drift region close to source-end region,
Surface electric field distribution is modulated, and embedded staggered NXing Tiao areas 7 and PXing Tiao areas 6 constitute superjunction knot in thick soi layer 4
Structure.During device forward conduction, due to greatly improving for doping concentration, under identical breakdown voltage, than conducting resistance greatly
Reduction, makes it while holding power MOS high breakdown voltages, significantly reduces than conducting resistance, there is relatively low lead
Logical loss, is finally reached and effectively reduces device area, reduces the purpose of device cost.In addition, hanging down in junction bearing of trend
Nogata between NXing Tiao areas 7 and PXing Ti areas 8 to having spacing.In actual process, in Withstand voltage layer central region, NXing Tiao areas 7
The power line that ionized donor is sent is directed to the ionization acceptor in PXing Tiao areas 6, so Withstand voltage layer central region, ionized impurity electric charge
Caused electric field cross stream component is zero；Only in NXing Tiao areas 7 close to the part in PXing Ti areas 8, the power line that ionized donor is sent
PXing Ti areas 8 are pointed to, equally, the power line sent in PXing Tiao areas 6 close to the part of N-type heavily doped drain region 11, ionization acceptor
Point to close to N-type heavily doped drain region 11, therefore, electric field is at NXing Tiao areas 7 and the knot of PXing Ti areas 8, A points as shown in Figure 8,
With PXing Tiao areas 6 and N-type heavily doped drain region 11, B points as shown in Figure 8 produce electric field peak, power device can be caused to shift to an earlier date
Puncture.
Fig. 8 is the distribution map of the electric field for producing A, B point due to the superposition of superjunction electric field in theory.In Withstand voltage layer central region, N
The power line that the ionized donor in Xing Tiao areas 7 is sent is directed to the ionization acceptor in PXing Tiao areas 6, so Withstand voltage layer central region, ionization
Electric field cross stream component is zero caused by impurity charge；Only in NXing Tiao areas 7 close to the part in PXing Ti areas 8, ionized donor is sent
Power line point to PXing Ti areas 8, equally, in PXing Tiao areas 6 close to the part in N-type heavy doping drain region 11, ionization acceptor sends
Power line is pointed to close to N-type heavy doping drain region 11, and therefore, electric field is at NXing Tiao areas 7 and the knot of PXing Ti areas 8, as shown in Figure 8
A points, and PXing Tiao areas 6 and N-type heavy doping drain region 11, B points as shown in Figure 8, produce electric field peak, power device can be caused to carry
Before puncture.
Embodiment 2
The present embodiment and embodiment 1 are essentially identical, and difference is：The width of the NXing Tiao areas 7 and PXing Tiao areas 6 in Z-direction
Degree is unequal.
Embodiment 3
As shown in figure 3, the present embodiment and embodiment 1 are essentially identical, difference is：The right-hand member of thick dielectric layer 5 not with N-type weight
Doped drain region 11 is tangent.
Embodiment 4
As shown in figure 4, the present embodiment and embodiment 1 are essentially identical, difference is：Device drain terminal contains N-type buffer areas
17, further to adjust the Electric Field Distribution that drain terminal bears higher-pressure region.The right-hand member of the thick dielectric layer 5 and N-type heavily doped drain region
11 and N-type buffer areas 17 it is tangent.
Embodiment 5
As shown in figure 5, the present embodiment and embodiment 4 are essentially identical, difference is：The right-hand member of thick dielectric layer 5 not with drain terminal N
Type buffer areas 17 are tangent.
Embodiment 6
As shown in fig. 6, the present embodiment and embodiment 1 are essentially identical, difference is：NXing Tiao areas 7 are with PXing Tiao areas 6 with burying oxygen
2 upper surface of layer are in contact.
Embodiment 7
As shown in fig. 7, the present embodiment and embodiment 1 are essentially identical, difference is：Contain N-type buffer areas 17 in device,
NXing Tiao areas 7 are in contact with PXing Tiao areas 6 with the upper surface of oxygen buried layer 2.
Embodiment 8
As shown in figure 9, the present embodiment and embodiment 1 are essentially identical, difference is：Folded to avoid surface superjunction from introducing two
Added electric field peak value, the NXing Tiao areas 7 are close to the circular arc that is shaped as of the one end in PXing Ti areas 8, and the PXing Tiao areas 6 are situated between close to thick
One end of matter layer 5 is shaped as circular arc.
Embodiment 9
As shown in Figure 10, the present embodiment and embodiment 1 are essentially identical, and difference is：To avoid surface superjunction from introducing two
Superposition of electric field peak value, the NXing Tiao areas 7 are rectangle, and the distance in the left end of NXing Tiao areas 7 and PXing Ti areas 8 is more than the left end of PXing Tiao areas 6
With the distance in PXing Ti areas 8, the PXing Tiao areas 6 are rectangle, and the distance of the right-hand member of PXing Tiao areas 6 and thick dielectric layer 5 is more than NXing Tiao areas 7
The distance of right-hand member and thick dielectric layer 5.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art without departing from disclosed spirit with being completed under technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of SOI lateral high-voltage devices with super-junction structure, it is characterised in that：Its structure cell includes substrate (1), substrate
(1) the substrate contact electrode (16) of lower surface, the oxygen buried layer (2) of substrate (1) upper surface, the thick soi layer of oxygen buried layer (2) upper surface
(4) the internal thick dielectric layer (5) of PXing Ti areas (8), on the left of thick soi layer (4), thick soi layer (4), run through along the longitudinal direction and embedding
Enter and be located on the N-type heavily doped drain region (11) of thick dielectric layer (5) right-hand member, longitudinal direction between thick dielectric layer (5) and oxygen buried layer (2)
Ultra-thin top layer silicon (3), the NXing Tiao areas (7) between PXing Ti areas (8) and thick dielectric layer (5) and PXing Tiao areas (6), positioned at p-type body
The internal separate p-type heavy doping body contact zone (9) in area (8) and N-type heavy-doped source polar region (10), to be arranged on N-type heavily doped
The gate oxide (12) of miscellaneous source area (10) and PXing Ti areas (8) upper surface, the source electrode being in contact with the upper surface of PXing Ti areas (8)
Contact electrode (13), the polysilicon gate (14) above gate oxide (12), it is arranged on N-type heavily doped drain region (11) upper surface
Drain contact electrode (15), the upper surface of the oxygen buried layer (2) is connected with the lower surface of thick soi layer (4) and ultra-thin top layer silicon (3)
Connect, the lower surface of the thick dielectric layer (5) is in contact with the upper surface of ultra-thin top layer silicon (3), the NXing Tiao areas (7) and p-type bar
Area (6) constitutes super-junction structure and is alternately embedded in the thick soi layer (4) in N-type drift region close to source-end region in Z-direction
In, the upper surface of p-type heavy doping body contact zone (9) and N-type heavy-doped source polar region (10) connects with the upper surface of PXing Ti areas (8)
Touch, the left end of right end portion covering N-type heavy-doped source polar region (10) of the Source contact electrode (13), the gate oxide
(12) left end portion covering N-type heavy-doped source polar region (10) right-hand member, gate oxide (12) not with Source contact electrode (13)
It is in contact.
2. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The device
The drain terminal of part contains N-type buffer areas (17).
3. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The N-type
Bar area (7) and PXing Tiao areas (6) are unequal in the width of Z-direction.
4. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The N-type
The length of bar area (7) and PXing Tiao areas (6) in the Y direction is less than or equal to the thickness of thick soi layer (4).
5. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The drift
The thick soi layer (4) of area's ultra-thin top layer silicon (3) and drift region is moved respectively by linear varying doping or Uniform Doped or discrete doping
A kind of doping way is formed；Or formed respectively by N sections of linear varying doping modes, N=1,2,3,4 ....
6. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The N-type
Bar area (7) is close to the circular arc that is shaped as of the one end in PXing Ti areas (8), and the PXing Tiao areas (6) are close to one end of thick dielectric layer (5)
Be shaped as circular arc.
7. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The N-type
Bar area (7) is rectangle, and the distance of NXing Tiao areas (7) left end and PXing Ti areas (8) is more than PXing Tiao areas (6) left end and PXing Ti areas (8)
Distance, the PXing Tiao areas (6) are rectangle, and it is right that the distance of PXing Tiao areas (6) right-hand member and thick dielectric layer (5) is more than NXing Tiao areas (7)
End and the distance of thick dielectric layer (5).
8. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The thickness
The right-hand member of dielectric layer (5) and N-type heavily doped drain region (11) or N-type buffer areas (17) are tangent.
9. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The N-type
Alternate sequencing is exchanged in z-direction for bar area (7) and PXing Tiao areas (6).
10. a kind of SOI lateral high-voltage devices with super-junction structure according to claim 1, it is characterised in that：The device
Part also includes M layers of field plate, M=1,2,3,4 ... ....
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020030114A1 (en) * | 2018-08-10 | 2020-02-13 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1422442A (en) * | 2000-03-30 | 2003-06-04 | 皇家菲利浦电子有限公司 | A high voltage thin film transistor with improved on-state characteristics and method for making same |
| CN1449057A (en) * | 2002-03-27 | 2003-10-15 | 株式会社东芝 | Field effect transistor and devices using same |
| CN101916727A (en) * | 2010-07-06 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Preparation method of SOI (Silicon on Insulator) high-voltage power device |
| US8482066B2 (en) * | 2011-09-02 | 2013-07-09 | Macronix International Co., Ltd. | Semiconductor device |
| US20140203365A1 (en) * | 2013-01-22 | 2014-07-24 | Nxp B.V. | Semiconductor device |
-
2017
- 2017-03-30 CN CN201710203410.XA patent/CN106981518A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1422442A (en) * | 2000-03-30 | 2003-06-04 | 皇家菲利浦电子有限公司 | A high voltage thin film transistor with improved on-state characteristics and method for making same |
| CN1449057A (en) * | 2002-03-27 | 2003-10-15 | 株式会社东芝 | Field effect transistor and devices using same |
| CN101916727A (en) * | 2010-07-06 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Preparation method of SOI (Silicon on Insulator) high-voltage power device |
| US8482066B2 (en) * | 2011-09-02 | 2013-07-09 | Macronix International Co., Ltd. | Semiconductor device |
| US20140203365A1 (en) * | 2013-01-22 | 2014-07-24 | Nxp B.V. | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020030114A1 (en) * | 2018-08-10 | 2020-02-13 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method therefor |
| US11552164B2 (en) | 2018-08-10 | 2023-01-10 | Csmc Technologies Fab2 Co., Ltd. | Semiconductor device and manufacturing method therefor |
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