CN106971988A - Wafer-level packaging part and its manufacture method - Google Patents

Wafer-level packaging part and its manufacture method Download PDF

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Publication number
CN106971988A
CN106971988A CN201610901128.4A CN201610901128A CN106971988A CN 106971988 A CN106971988 A CN 106971988A CN 201610901128 A CN201610901128 A CN 201610901128A CN 106971988 A CN106971988 A CN 106971988A
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China
Prior art keywords
dielectric layer
wafer
photoimageable dielectric
semiconductor element
layer
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CN201610901128.4A
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CN106971988B (en
Inventor
崔亨硕
成基俊
金钟薰
刘荣槿
裴弼淳
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

Wafer-level packaging part and its manufacture method.According to various embodiments, packaging part, semiconductor and wafer-level packaging part, and the method that manufacture packaging part, semiconductor and wafer-level packaging part can be provided can be provided.A kind of method for manufacturing wafer-level packaging part may comprise steps of：Alignment mark is formed at the surface of protection wafer；Semiconductor element is arranged on the protection wafer using the alignment mark；Form the first photoimageable dielectric layer of the covering semiconductor element；By the top surface planarization of first photoimageable dielectric layer；By the Partial exposure of planarized the first photoimageable dielectric layer and it is developed, to form the opening portion for the part exposure for making the semiconductor element；And form redistribution line on first photoimageable dielectric layer.The second photoimageable dielectric layer can be formed to cover the redistribution line.The wafer-level packaging part of correlation can also be provided.

Description

Wafer-level packaging part and its manufacture method
Technical field
Embodiment of the present disclosure can relate generally to semiconductor package part (package), and relate more specifically to Wafer-level packaging part and its manufacture method.
Background technology
Semiconductor device employed in electronic system can include various electronic circuit components.The electronic circuit component It can be integrated in semiconductor substrate and/or on semiconductor substrate, to constitute semiconductor chip or semiconductor element (die).Semiconductor chip or semiconductor element can be encapsulated providing semiconductor package part.Semiconductor package part can be by There is provided to protect semiconductor chip or semiconductor element in the semiconductor package part to influence from external force.Semiconductor package part It is widely used in each in electronic system as such as computer, mobile system or data storage medium.Closely Come, with the exploitation of electronic system lighter and smaller as such as smart phone, to the demand of thin semiconductor package part It is continuously increased.
Because the demand to thin semiconductor package part is continuously increased, therefore semiconductor chip is constituted in semiconductor package part Semiconductor substrate thickness it is reduced.Therefore, substantial amounts of energy has been concentrated to prevent semiconductor package part or partly lead Structure base board warpage during encapsulation process.Further, since semiconductor package part is scaled and company of semiconductor package part The number increase of fitting (for example, connection pad), therefore proposed many technologies to realize the pad with finer pitch High-performance semiconductor packaging part.
The content of the invention
According to various embodiments, packaging part, semiconductor and wafer-level packaging part can be provided.According to various embodiment party Formula, the method that manufacture packaging part, semiconductor and wafer-level packaging part can be provided.A kind of method for manufacturing wafer-level packaging part can With including forming alignment mark.Methods described can include installing semiconductor element on the first surface.Methods described can be with Including the first photoimageable dielectric film is attached into protection wafer.Methods described can include the first photoimageable dielectric layer and protection is brilliant The opposite top surface planarization of circle.Methods described can be included the Partial exposure of planarized the first photoimageable dielectric layer.Institute The method of stating can include developing to exposed the first photoimageable dielectric layer.Methods described can be included in the first photoimageable dielectric Redistribution line (redistribution line) is formed on layer.The redistribution line can be formed through opening portion and be electrically connected It is connected to semiconductor element.The second photoimageable dielectric layer can be formed to cover the redistribution line.
Brief description of the drawings
Fig. 1, Fig. 2 and Fig. 3 are the tables of the example exemplified with the failure shifted in manufacture wafer-level packaging part according to tube core The sectional view shown.
Fig. 4 and Fig. 5 exemplified with manufacture wafer-level packaging according to non-between tube core and epoxy resin mould produced compounds Planarize the expression of the example of the failure of (non-planarity).
Fig. 6 be exemplified with manufacture wafer-level packaging according to the example of the pattern distortion of the pattern density of redistribution line The sectional view of expression.
Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18 and Figure 19 exemplified with According to the expression of the example of the method for the manufacture wafer-level packaging part of embodiment.
Figure 20 is the sectional view of the expression of the example exemplified with the wafer-level packaging part according to embodiment.
Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29 and Figure 30 are exemplified with according to embodiment party The sectional view of the expression of the example of the method for the manufacture wafer-level packaging part of formula.
Figure 31 is the sectional view of the expression of the example exemplified with the wafer-level packaging part according to embodiment.
Figure 32 is the example exemplified with the electronic system using the storage card including the packaging part according to embodiment Expression block diagram.
Figure 33 is the block diagram of the expression of the example exemplified with the electronic system including the packaging part according to embodiment.
Embodiment
Term used herein can correspond to the word for considering its function in embodiments and selecting, and term Implication can be according to belonging to embodiment field in those of ordinary skill and be interpreted difference.If be in detail defined in, Then term can be explained according to the restriction.Unless otherwise defined, otherwise term used herein (including technical term and Scientific terminology) there is the implication identical being generally understood that with the those of ordinary skill in the technical field belonging to embodiment to contain Justice.
It will be appreciated that, although each element can be described with term first, second, third, etc. used herein, But these elements should not be limited by these terms.These terms are used only for distinguishing an element and another element Open.Therefore, in the case where not departing from teaching, the first element in some embodiments can be claimed in other embodiments For the second element.
It will be further understood that when element be referred to as " " another element " on ", " " another element " top ", " " Another element " lower section " or " " another element " below " when, the element can directly " " another element " on ", directly " " another element " top ", directly " " another element " lower section " either directly " " another element " below " or also may be used There is intermediary element.Therefore, it is used herein such as " ... on ", " in ... top ", " in ... lower section " or " ... under Term as face " is merely to describe the purpose of particular implementation, without being intended to limit the disclosure.
According to the semiconductor package part of implementation below can include such as semiconductor element or semiconductor chip this The electronic installation of sample, and semiconductor element or semiconductor chip can by using tube core sawing process will such as wafer this The semiconductor substrate of sample is separated into multiple pieces to obtain.Semiconductor chip can be with memory chip, logic chip or special Integrated circuit (ASIC) chip correspondence.Memory chip can include integrated dynamic random access memory on a semiconductor substrate Device (DRAM) circuit, static RAM (SRAM) circuit, flash memory circuit, MAGNETIC RANDOM ACCESS MEMORY (MRAM) circuit, resistive random access memory (ReRAM) circuit, ferroelectric RAM (FeRAM) circuit or phase Become random access memory (PcRAM) circuit.Each in semiconductor package part can include package substrate and installed in envelope The semiconductor chip on substrate is filled, and package substrate can be used to semiconductor chip being electrically connected to external device (ED).Therefore, Different from semiconductor substrate, package substrate can include being arranged in the base main body being made up of dielectric material and/or the substrate Circuit trace (trace) in main body.Semiconductor substrate can be printed circuit board (PCB) (PCB).Semiconductor package part can by with Such as but be not limited to communication system as mobile phone, the electronic system that associates with biotechnology or health care, Or in Wearable electronic system.
Throughout the specification, identical reference refers to identical element.Therefore, even if being carried without reference to a width figure And or description one reference, also can refer to or describe the reference with reference to another width figure.In addition, even in a width figure Not shown in a reference, also can refer to or describe the reference in another width figure.
The wafer-level packaging part that the disclosure can provide the method for manufacture wafer-level packaging part and thus manufacture.It can make Wafer-level packaging part is manufactured with the protective substrate with the shape of wafer as such as Silicon Wafer.According to implementation below Wafer-level packaging part can be made with and be fanned out to semiconductor package part form.It is fanned out to each in semiconductor package part There can be following structure：Even if semiconductor chip, which is less than, is fanned out to semiconductor package part, semiconductor chip is also by being arranged on Redistribution line on molded components is electrically connected to joint outer part as such as soldered ball.
Being fanned out to semiconductor package part (that is, fan-out wafer level packaging part) can be accomplished by the following way：Performing is used for Such as molded components of epoxy resin mould produced compounds (EMC) material are formed on using temporary die as the wafer of carrier Wafer molding process, and by forming redistribution line on molded components.However, in this case, fan-out wafer level envelope Piece installing can be presented such as poor encapsulation landform (topography), be easy to warpage, due to failure, core caused by tube core displacement Some problems as piece to the non-flattening of mould etc..These problems can include the cross tie part with finer pitch realizing Turn into obstacle during high-performance package part.That is, connector as such as pad of wafer-level packaging part may be being reduced Pitch and size and to there are some when reducing the pitch and size of interconnection line of wafer-level packaging part difficult.
Tube core shifting phenomena may be due to connecing between temporary die and semiconductor chip (or semiconductor element) temporarily Close and occur.Temporary die can be joined to semiconductor chip by temporary adhesive.However, because temporary die is finally necessary It is removed, therefore temporary adhesive can have relatively weak bonding strength.Therefore, it is interim viscous during wafer molding process Mixture may be deformed due to the pressure of EMC materials, to cause the displacement of semiconductor chip.Wafer molding process it Afterwards, EMC materials can be cooled to cause the contraction of EMC materials.In this case, semiconductor chip can be towards wafer Central part is moved.Therefore, the position of the connection pad of semiconductor chip can change, to be formed for limiting bonding pad opening Cause during insulating barrier connect pad and for make connection pad expose bonding pad opening between misalignment.Structure, although soldered ball Connection pad is attached to, but soldered ball can be with being connected pad misalignment.
Non-flattening problem of the chip to mould occurs for boundary that can be between semiconductor chip and molded components. After temporary adhesive is provided on temporary die and the wafer including semiconductor chip is positioned on temporary adhesive, High pressure can be applied to semiconductor chip and temporary adhesive during the molding process for forming molded components.It is applied to The high pressure of semiconductor chip and temporary adhesive can cause the deformation of the temporary adhesive with relatively low modulus, and have The semiconductor chip for having relatively high modulus is hardly deformed.As a result, side that can be between semiconductor chip and molded components The surface level error of temporary adhesive is formed at boundary.Therefore, when in subsequent handling on semiconductor chip and molded components When forming redistribution line, the surface level error of temporary adhesive can cause the pattern distortion of redistribution line.
When redistribution line be formed with sandwich construction and cover redistribution line insulating barrier use rotary coating work When sequence is to form, according to the pattern density of redistribution line, it is impossible in the execution photo-mask process uniformly over the surface of insulating barrier.Should Photo-mask process heterogeneous can cause pattern distortion.
If the body of the molded components (for example, EMC materials) with relatively high thermal coefficient of expansion (CTE) in packaging part Product is more than the volume of the silicon materials with relatively low thermal coefficient of expansion (CTE), then wafer can be for forming molded components Wafer molding process during or the wafer molding process after easily warpage.It is formed and redistribution line in molded components While being formed, heating stepses and cooling step can be repeated to cause due between molded components and silicon materials The concentration of stress caused by CTE difference.Therefore, wafer may easy warpage.The warpage of wafer can cause the failure of processing apparatus Or process disturbances.
Fig. 1, Fig. 2 and Fig. 3 are the tables of the example exemplified with the failure shifted in manufacture wafer-level packaging part according to tube core The sectional view shown.
Reference picture 1, tube core 20 can use temporary adhesive 30 to be attached to the surface of carrier 10.Tube core 20 can be attached to Carrier 10, to cause the connection pad 21 of tube core 20 to face carrier 10.Reference picture 2, is formed to cover tube core 20 in EMC layers 40 While, at least one in tube core 20 can be with transverse shift.As a result, compared with its initial position, in the tube core 20 The position of at least one can change.If the transverse shift of tube core 20, the position of the connection pad 21 of tube core 20 can also change Become.After EMC layers 40 are formed, carrier 10 can be removed from tube core 20 and EMC layers 40.Can be by reducing temporary adhesive 30 Bonding strength remove carrier 10.The bonding strength of temporary adhesive 30 can be by irradiating ultraviolet to temporary adhesive 30 (UV) line or by reducing to the heating of temporary adhesive 30.Reference picture 3, insulating barrier 50 can be formed on EMC layers 40 To cover the connection pad 21 of tube core 20 and tube core 20 on surface, and can be formed through the opening portion 51 of insulating barrier 50 so that Connection pad 21 exposes.It is then possible to form redistribution line 60 on insulating barrier 50 and in opening portion 51.If tube core 20 is as above Described to form EMC layer 40 period transverse shifts, then opening portion 51 can be formed and connect the misalignment of pad 21.As a result, As illustrated in fig. 3, redistribution line 60 can with to be connected pad 21 electrically disconnected, so as to cause connecting fault.
Fig. 4 and Fig. 5 exemplified with manufacture wafer-level packaging according to non-between tube core and epoxy resin mould produced compounds The expression of the example of the failure of planarization.Fig. 4 is along the vertical of the interception of the length direction of any one in redistribution line 60 Sectional view, and Fig. 5 is the plan of redistribution line 60.
Reference picture 4, the non-flattening of insulating barrier 50 can be illustrated in the border between EMC layers 40 and the side wall of tube core 20 On face.Because while EMC layers 40 are formed, the temporary adhesive (the 30 of Fig. 2) contacted with tube core 20 is pressed downwardly Must be more than the temporary adhesive (the 30 of Fig. 2) contacted with EMC layers 40.It therefore, it can provide water between tube core 20 and EMC layers 40 Adjustment.That is, level error D1 may reside between the surface 23 of tube core 20 and the surface 41 of EMC layers 40.Cover tube core The insulating barrier 50 of 20 and EMC layers 40 can be formed with injustice due to the level error D1 between tube core 20 and EMC layers 40 Smooth surface, and the redistribution layer formed on insulating barrier 50 can also have the uneven surface that level error D2 is presented. Redistribution line 60 can be formed by being patterned to the redistribution layer with level error D2.Therefore, level error D2 can be with shadow Ringing be used for being patterned to redistribution layer to be formed in the photo-mask process of redistribution line 60, and redistribution line 60 each can To be formed with uneven width.If, can for example, redistribution layer carrys out composition using photo-mask process and etching work procedure It can be difficult to adjust and optimal during photo-mask process due to the uneven thickness for the photoresist layer being coated on redistribution layer Change the depth of focus.Therefore, redistribution line 60 can be formed to include overlapping and having the first of width X1 with tube core 20 The part 60A and Part II 60B for overlapping and having the width X2 different with width X1 from EMC layers 40 (see Fig. 5).Separately Outside, redistribution line 60 can be formed to include the Part III 60C between Part I 60A and Part II 60B.This In the case of, reference picture 5, if width X1 is more than width X2, the Part III 60C of redistribution line 60 can be from Part I 60A is gradually reduced initially towards Part II 60B.The uneven width of redistribution line 60 can cause the electricity of redistribution line 60 special The deterioration of property and reliability.
Fig. 6 be exemplified with manufacture wafer-level packaging according to the example of the pattern distortion of the pattern density of redistribution line 60 Expression sectional view.
Reference picture 6, redistribution line 60 can be formed on the first insulating barrier 50 of covering tube core 20, and the second insulating barrier 70 can form on the first insulating barrier 50 to cover redistribution line 60.The surface of second insulating barrier 70, which can have, to be provided with Level error D3 between the region 61 of redistribution line 60 and the region 63 for being not provided with redistribution line 60.Level error D3 can be with area The table of the top surface of the second insulating barrier 70 in the horizontal L1 in surface and region 63 of the top surface of the second insulating barrier 70 in domain 61 Difference correspondence between the horizontal L2 in face.If the second insulating barrier 70 has the top surface that level error D3 is presented, form exhausted second Some in the opening portion 81 and 81E of Resist patterns 80 in edge layer 70 can have pattern distortion.If using region 61 The position of the conditions of exposure, then Resist patterns 80 of photo-mask process for forming Resist patterns 80 is determined as target area Opening portion 81 in region 61 can be normally formed as standard-sized sheet, and the opening being located in region 63 of Resist patterns 80 Portion 81E is abnormally produced as no standard-sized sheet.This pattern distortion is probably the level of the top surface due to the second insulating barrier 70 Caused by poor D3.
According to the disclosure, protective substrate (or protection wafer) is used as supporting wafer to support semiconductor element (or semiconductor chip), semiconductor element can use the adhesive with permanent adhesive intensity to be attached to protective substrate.Cause Semiconductor element, after semiconductor element is attached to protective substrate, can be fixed firmly to protective substrate to prevent by this Semiconductor element is shifted during subsequent handling.Semiconductor element can use lamination process and covered with photoimageable dielectric film, be somebody's turn to do Photoimageable dielectric film can be flattened to provide the flat top surface of photoimageable dielectric film.Then, can be in photoimageable dielectric film Redistribution line is formed on flat top surface.Therefore, before redistribution line is formed, following dielectric layer can be prevented to have not Flat landform.Silicon substrate as protective substrate may be used as a part for package main body.It therefore, it can alleviate due to encapsulation Misalignment issues caused by CTE difference between main body and protective substrate, to suppress the warpage of wafer-level packaging part.Therefore, originally It is open that the high-performance semiconductor packaging part including the interconnection line with finer pitch can be provided.
Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18 and Figure 19 exemplified with According to the expression of the example of the method for the manufacture wafer-level packaging part of embodiment.Fig. 7 is the plan for protecting wafer 1100W, And each of Fig. 8 into Figure 19 includes the sectional view of a protection wafer 1100W part.
Reference picture 7, can provide protection wafer 1100W and manufactured with the manufacturing technology using wafer-level packaging part and be fanned out to half Conductor packaging part.Protection wafer 1100W can be the semiconductor crystal wafer or semiconductor substrate of such as Silicon Wafer.In some implementations In mode, the wafer that protection wafer 1100W can be made up of the material different from silicon materials.In some other embodiments In, protection wafer 1100W can be by the main body of CTE and the semiconductor element (the 1200 of Fig. 8) for being attached to protection wafer 1100W The material composition that CTE is substantially identical.In such a case, it is possible to suppress due between semiconductor element and protective substrate Some failures (for example, warpage) caused by CTE difference.If for example, each in semiconductor element (the 1200 of Fig. 8) has Silicon main body, then protect wafer 1100W to be made up of silicon materials.
Protection wafer 1100W can be the thickness that thickness is semiconductor element (the 1200 of Fig. 8) about ten again to about 30 Silicon Wafer again.If for example, semiconductor element (1200 of Fig. 8) has about 30 microns to about 50 microns of thickness, protected Wafer 1100W can have about 750 microns to about 770 microns of thickness.Because protection wafer 1100W is than semiconductor element (Fig. 8 It is much 1200) thick, therefore the volume ratio of protection wafer 1100W and packaging part can be more than semiconductor element (the 1200 of Fig. 8) With the volume ratio of packaging part.This can suppress to lead due to CTE difference of the semiconductor element (the 1200 of Fig. 8) between other elements The influence of cause.It therefore, it can suppress the warpage of packaging part.
Wafer 1100W is protected to have each other relative first surface 1101 and second surface 1103, and the first table The distance between face 1101 and second surface 1103 can be corresponding with protecting wafer 1100W thickness.Alignment mark 1110 can be with Formed at protection wafer 1100W first surface 1101.When reconstitute in subsequent handling semiconductor element (Fig. 8's 1200) when, alignment mark 1110 is used as assigning the reference marker of the position of semiconductor element (the 1200 of Fig. 8). Alignment mark 1110 can be formed in the borderline region 1106 of each in protection wafer 1100W unit area 1100U. Protection wafer 1100W can include multiple unit area 1100U.Each unit area 1100U can be assigned to single package Part.Unit area 1100U can be aligned to matrix form.Each unit area 1100U can include being provided with partly leading Side of the chip mounting area 1105 and encirclement chip mounting area 1105 of body tube core 1200 for use as road plan (scribe lane) Battery limit (BL) domain 1106.Protection wafer 1100W can include the multiple unit area 1100U arranged in two dimensions.Alignment mark 1110 can be arranged in the borderline region 1106 between chip mounting area 1105 adjacent to each other.Alternatively, to fiducial mark Note 1110 can be arranged in chip mounting area 1105 with adjacent with borderline region 1106.Alignment mark 1110 can be by shape As with the low or high surface of the first surface 1101 than protecting wafer 1100W.For example, alignment mark 1110 can pass through To protect wafer 1100W first surface 1101 a part carry out selective etch and be formed with groove shapes or Concave.It therefore, it can realize accurate alignment using alignment mark 1110 in subsequent handling.That is, protection Level error between wafer 1100W first surface 1101 and the basal surface of alignment mark 1110 can be produced with high-resolution Image, and can use with high-resolution alignment mark image accurately to set or identification protecting wafer 1100W ad-hoc location.Alignment mark 1110 can be located in each unit area 1100U to provide reference position.Therefore, half Conductor tube core (the 1200 of Fig. 8) can in subsequent handling using alignment mark 1110 come with protection wafer 1100W it is accurately right It is accurate.
Reference picture 8, semiconductor element 1200 can be arranged on protection wafer 1100W first surface 1101 to use Alignment mark 1110 is aligned with chip mounting area 1105 respectively, and semiconductor element 1200 can be separately mounted on chip On installation region 1105.Each semiconductor element 1200 has the 3rd table of the first surface 1101 in face of protection wafer 1100W Face 1206, and adhesive layer 1300 can be set on the 3rd surface 1206 of semiconductor element 1200.Such as connection pad Internal connector 1201 can be arranged on fourth surface 1207 opposite with protection wafer 1100W of semiconductor element 1200 On.Therefore, semiconductor element 1200 can be installed on protection wafer 1100W, to cause connection pad 1201 to be arranged on On the surface opposite with protection wafer 1100W of semiconductor element 1200.Semiconductor element 1200 can be separately positioned on logical Cross on the chip mounting area 1105 separated from one another of borderline region 1106.Therefore, semiconductor element 1200 can be arranged abreast It is listed on protection wafer 1100W.
Adhesive layer 1300 can provide the permanent engagement between protection wafer 1100W and semiconductor element 1200, will be partly Conductor tube core 1200 is fixed to protection wafer 1100W.With for that will face in the general technology for manufacturing wafer-level packaging part The temporary adhesion layer of Shi Zaiti (or processing supporting member) temporary attachment to semiconductor element is different, and adhesive layer 1300 can be provided Protect the irreversible engagement between wafer 1100W and semiconductor element 1200.If UV ray is irradiated in temporary adhesion layer, Then temporary adhesion layer can lose its bonding strength.Therefore, it is possible to use UV ray is by temporary carrier (or processing supporting member) Separated with semiconductor element.In embodiments, adhesive layer 1300 can be installed in protection wafer in semiconductor element 1200 Solidify afterwards upper 1100W.In this case, even if UV ray is irradiated on cured adhesive layer 1300, cured is viscous Its bonding strength will not also be lost by closing layer 1300.Therefore, it is installed in even in semiconductor element 1200 on protection wafer 1100W And after engaging, also it can additionally perform curing process using heating or UV ray.Adhesive layer 1300 can be with Comprising curable adhesive composition, and semiconductor element 1200 can not by the chemical reaction of curable adhesive composition Protection wafer 1100W is fixed to inversely.Adhesive layer 1300 can include the epoxy resin ingredient as curable adhesive composition, And adhesive layer 1300 can be hardened by epoxy resin reaction during curing process, with provide protection wafer 1100W with Permanent and irreversible engagement between semiconductor element 1200.Because adhesive layer 1300 connects semiconductor element 1200 securely Merge and be fixed to protection wafer 1100W, therefore adhesive layer 1300 can suppress semiconductor element 1200 during subsequent handling Displacement.In the disclosure, protect wafer 1100W not separated with semiconductor element 1200, and protect the one of wafer 1100W Part may be constructed a part for each packaging part.Therefore, it is possible to use semiconductor element 1200 can be permanently attached to Protection wafer 1100W irreversible jointing material is used as adhesive layer 1300.
In some embodiments, adhesive layer 1300 can include thermal interfacial material composition or heat conduction composition, to provide Radiate or distribute the hot path produced by the operation of semiconductor element 1200.If including such as metal in adhesive layer 1300 Heat conduction composition as particle or thermal interfacial material composition, then the heat produced in semiconductor element 1200 can be by more easily It is dispersed into protection wafer 1100W.Protection wafer 1100W thermal conductivity can be higher than to be formed to surround half in subsequent handling The thermal conductivity of the photosensitive material layer of conductor tube core 1200.Therefore, if adhesive layer 1300 is comprising thermal interfacial material composition or leads Hot composition, then can more effectively distribute the heat produced in semiconductor element 1200.
Reference picture 9, the first photoimageable dielectric film 1410F can be arranged on semiconductor element 1200.Reference picture 10, first Photoimageable dielectric film 1410F can be attached to protection wafer 1100W to form the first photoimageable dielectric layer 1410A.Therefore, transistor Core 1200 can be buried in the first photoimageable dielectric layer 1410A.First photoimageable dielectric film (1410F in Fig. 9) can include Photopolymer film as such as light-sensitive polyimide film or photosensitive polybenzoxazoles film.In some embodiments, wrap Light-sensitive surface containing epoxy resin ingredient is used as the first photoimageable dielectric film 1410F.Due to the first photoimageable dielectric film 1410F or Person first photoimageable dielectric layer 1410A include sensitising agent, therefore the first photoimageable dielectric layer 1410A is exposed to light (such as UV ray) It is a part of can have with the first photoimageable dielectric layer 1410A another part without exposure to light (such as UV ray) it is molten The different solubility of solution degree.
Uneven surface 1410U can be had by being attached to protection wafer 1100W the first photoimageable dielectric layer 1410A.Due to The first photoimageable dielectric film 1410F with flat surfaces is in turn laminated on protection wafer 1100W and semiconductor element 1200 to carry For the first photoimageable dielectric layer 1410A, therefore the first photoimageable dielectric layer 1410A uneven surface 1410U can be due to alignment Caused by the configuration of surface of mark 1110 and semiconductor element 1200.That is, the first photoimageable dielectric layer 1410A with it is each The overlapping Part I 1410H of semiconductor element 1200 can have is arranged on semiconductor than the first photoimageable dielectric layer 1410A The high top surface of the top surface of Part II 1410L between tube core 1200.
Reference picture 11, can be to the first photoimageable dielectric layer 1410A application planarization steps.For example, with flat surfaces 1490P Planarization component 1490 can be located at the first photoimageable dielectric layer 1410A on, and planarize component 1490 can be in heating In the case of be pressed downwardly with by the first photoimageable dielectric layer 1410A uneven surface 1410U change into by planarizing component Flat surfaces 1410P smooth 1490 flat surfaces 1490P.As a result, the first sense with flat surfaces 1410P can be provided Light dielectric layer 1410.It can be the mold frame with flat surfaces 1490P to planarize component 1490.Planarizing component 1490 can To be pressure roller.Even if the first photoimageable dielectric layer 1410A has uneven surface due to the presence of semiconductor element 1200 1410U, the first photoimageable dielectric layer 1410A can also be changed to the first sense with flat surfaces 1410P by planarization step Light dielectric layer 1410.Therefore, it is possible to be formed on the flat surfaces 1410P of the first photoimageable dielectric layer 1410 with finer pitch Interconnection line.
Reference picture 12, can form the first opening portion 1411, so that semiconductor element in the first photoimageable dielectric layer 1410 1200 part (for example, internal connector 1201) exposure.First opening portion 1411 can be formed photosensitive through first Dielectric layer 1410.First opening portion 1411 can be by optionally making a part for the first photoimageable dielectric layer 1410 exposed to all As UV ray light and developed by the first photoimageable dielectric to being exposed layer 1410 and formed.In this case, Due to the first photoimageable dielectric layer 1410 have flat surfaces 1410P, therefore can not due to defocus expose etc. caused by It is uniform and be formed accurately the first opening portion 1411 in the case of any pattern distortion.
Reference picture 13, can form Resist patterns on the first photoimageable dielectric layer 1410 with the first opening portion 1411 1700.Resist patterns 1700 is used as mask, for example, being coated with mask for form redistribution line.Resist patterns 1700 can be by being coated on the first photoimageable dielectric layer 1410 and using exposure process and developing procedure by anticorrosive additive material Anticorrosive additive material is patterned to be formed.Resist patterns 1700 can be formed to make the first opening portion 1411 expose and Make the flat surfaces 1410P adjacent with the first opening portion 1411 of the first photoimageable dielectric layer 1410 part exposure.Due to One photoimageable dielectric layer 1410 has flat surfaces 1410P, therefore Resist patterns 1700 can be due to following layer Accurate size is formed with caused by uneven surface in the case of some working-procedure problems.Resist patterns 1700 can To be formed to limit the region for being provided with redistribution line.
Reference picture 14, can the first photoimageable dielectric layer 1410 by Resist patterns (1700 in Figure 13) exposure Redistribution line 1500 is formed in the first opening portion 1411 exposed on flat surfaces 1410P and by Resist patterns 1700. Then Resist patterns 1700 can be removed.Resist patterns 1700 may be used as limiting the composition of the shape of redistribution line 1500 Mask.Redistribution line 1500 can be by being deposited on the first sense exposed by Resist patterns 1700 by the plating preparative layer comprising copper Formed on light dielectric layer 1410, and Resist patterns 1700 can be removed.Alternatively, redistribution line 1500 can be by inciting somebody to action It is upper and by Resist patterns that plating preparative layer comprising copper is deposited on both the first photoimageable dielectric layer 1410 and Resist patterns 1700 1700 peel off and are formed.
Each redistribution line 1500 can be formed the flat surfaces 1410P for including being located at the first photoimageable dielectric layer 1410 On for use as in the trace patterns 1550 of interconnection line and one in the first opening portion 1411 with by trace patterns 1550 The through hole 1530 of one being electrically connected in internal connector 1201.Through hole 1530 can be formed perpendicularly through covering half The first photoimageable dielectric layer 1410 on the 4th surface 1207 of conductor tube core 1200, and contacted with internal connector 1201.Through hole 1530 can be formed to fill one in the first opening portion 1411.Trace patterns 1550 can extend partly to lead with being arranged on A part for the first photoimageable dielectric layer 1410 between body tube core 1200 is overlapped.
Because the first photoimageable dielectric layer 1410 has flat surfaces 1410P, therefore Resist patterns (1700 in Figure 13) It can be formed that there is fine pitch in the case of without pattern distortion.Therefore, its shape is by Resist patterns (Figure 13 In 1700) limit redistribution line 1500 can also be formed in the case of without pattern distortion have fine section Away from.Therefore, it is possible to increase the number of the redistribution line 1500 formed in finite region.
Reference picture 15, the second photoimageable dielectric layer 1450 can form the flat surfaces in the first photoimageable dielectric layer 1410 1410P is upper to cover redistribution line 1500.The identical skill with being used when forming the first photoimageable dielectric layer 1410 can be used Art come formed the second photoimageable dielectric layer 1450.That is, the second photoimageable dielectric layer 1450 can be by by the second photoimageable dielectric Film (not illustrating) is arranged in the first photoimageable dielectric layer 1410 and redistribution line 1500 and photosensitive by second using lamination process Dielectric film is attached to the first photoimageable dielectric layer 1410 and formed.In this case, the second photoimageable dielectric film can be because of dividing again The presence of distribution 1500 and with uneven top surface.It therefore, it can utilize with making the first photoimageable dielectric layer 1410A flat The identical planarization step used during change makes to be attached to the second photoimageable dielectric film planarization of the first photoimageable dielectric layer 1410.Knot Really, as illustrated in Figure 15, the second photoimageable dielectric layer 1450 can be formed with flat surfaces 1450P.Due to second photosensitive Dielectric layer 1450 has flat surfaces 1450P, therefore can be more easily formed on the second photoimageable dielectric layer 1450 fine Pattern.In some embodiments, the second photoimageable dielectric layer 1450 can be by substantially identical with the first photoimageable dielectric layer 1410 Material formed.
If necessarily be formed the redistribution line with sandwich construction, it can be repeatedly carried out forming redistribution line 1500 The step of step and the second photoimageable dielectric of formation layer 1450.It is each photosensitive even if redistribution line is formed with sandwich construction Dielectric layer can also be formed with flat top surface.Therefore, all redistribution lines with sandwich construction can be by shape As with fine pitch.
Reference picture 16, can be to the second photoimageable dielectric 1450 composition of layer, to be formed through the second photoimageable dielectric layer 1450 Second opening portion 1451 of a part.Second opening portion 1451 can be by optionally making the one of the second photoimageable dielectric layer 1450 Part is exposed to the light of such as UV ray and the second photoimageable dielectric layer 1450 exposed is developed and formed.This In the case of, due to the second photoimageable dielectric layer 1450 have flat surfaces 1450P, therefore can not due to defocus expose etc. and It is uniform and be formed accurately the second opening portion 1451 in the case of caused pattern distortion.
Each second opening portion 1451 can be formed to make the part exposure of any one in redistribution line 1500. For example, each second opening portion 1451 can be formed to make the trace patterns 1550 of any one in redistribution line 1500 Part exposure.Some in second opening portion 1451 can be formed not overlapping with semiconductor element 1200.Reference picture 17, Joint outer part 1600 can be attached respectively to the trace patterns 1550 exposed by the second opening portion 1451.Therefore, outside connects Fitting 1600 may be electrically connected to trace patterns 1550.Joint outer part 1600 can have the shape of soldered ball.Alternatively, it is outside Connector 1600 can have the shape of projection.Some in joint outer part 1600 can be positioned as not with semiconductor element 1200 overlap.Trace patterns 1550 are extended on the borderline region 1106 between chip mounting area 1105, to realize fan Go out semiconductor package part.
Reference picture 18, can perform reduction steps to reduce protection wafer 1100W thickness.That is, guarantor can be made Shield wafer 1100W second surface 1103 is recessed to provide recessed second surface 1103B.Can be by protection wafer The 1100W application grinding process of second surface 1103 performs reduction steps.Alternatively, can be by protection wafer 1100W Second surface 1103 applied chemistry mechanical polishing (CMP) process or eatch-back (etch-back) process perform reduction steps.
Initial protection wafer 1100W can be the Silicon Wafer with about 750 microns to about 770 microns of thickness.Performing After reduction steps, protection wafer 1100W can have about 150 microns to about 400 microns of thickness.Although semiconductor element 1200 have about 30 microns to about 50 microns of thickness, but passing through thinned protection wafer 1100W still can compare transistor Core 1200 is thick.In view of the minimum thickness required for protection semiconductor element 1200, can have through thinned protection wafer 1100W There is at least 150 microns of thickness.Because the thickness through thinned protection wafer 1100W is the pact of the thickness of semiconductor element 1200 3 times to about 15 times, thus the volume ratio through thinned protection wafer 1100W and packaging part can be more than semiconductor element 1200 and The volume ratio of packaging part.This can suppress due to the CTE difference between semiconductor element 1200 and photoimageable dielectric layer 1410 and 1450 And the influence caused.It therefore, it can suppress the warpage of packaging part.
Reference picture 19, can use separation circuit along 1106 pair second of borderline region between chip mounting area 1105 Photoimageable dielectric the 1450, first photoimageable dielectric of layer layer 1410 and the protection wafer 1100W through being thinned are cut, therefore are provided each other The wafer-level packaging part 100 and 101 of separation.For example, saw blade 1800 can be arranged on the borderline region 1106 as road plan, And saw blade 1800 can be used along borderline region 1106 to photoimageable dielectric layer 1450 and 1410 and the protection wafer through being thinned 1100W is cut to produce the wafer-level packaging part 100 and 101 separated each other.Even in photoimageable dielectric layer 1450 and 1410 With being cut through thinned protection wafer 1100W with after producing wafer-level packaging part 100 and 101, the He of wafer-level packaging part 100 Each in 101 still can include a part of the protection wafer 1100W through being thinned, i.e. unit protection wafer 1100U. Therefore, unit protection wafer 1100U still can cover the 3rd surface 1206 of semiconductor element 1200 to protect transistor Core 1200.
Figure 20 is the sectional view of the expression of the example exemplified with the wafer-level packaging part 100 according to embodiment.
Reference picture 20, wafer-level packaging part 100 can be corresponding with being fanned out to semiconductor package part.Wafer-level packaging part 100 can With the semiconductor element 1200 for the first surface 1101 that unit protection wafer 1100U is attached to including the use of adhesive layer 1300.It is brilliant Circle level packaging part 100 can also include covering semiconductor element 1200 and have side wall 1410S and planar top surface 1410P First photoimageable dielectric layer 1410.Wafer-level packaging part 100 can include the second sense being stacked on the first photoimageable dielectric layer 1410 Light dielectric layer 1450.Second photoimageable dielectric layer 1450 can have planar top surface 1450P and with the first photoimageable dielectric layer The side wall 1450S of 1410 side wall 1410S alignments.Side wall 1410S and side wall 1450S can protect wafer 1100U's with unit Side wall 1100S is aligned.Alignment mark 1110 can be arranged at unit protection wafer 1100U first surface 1101, and It can be configured to adjacent with semiconductor element 1200.Unit protection wafer 1100U thickness T1 can be more than semiconductor element 1200 thickness T2.
Wafer-level packaging part 100 can also include being arranged on the first photoimageable dielectric layer 1410 and the second photoimageable dielectric layer 1450 Between redistribution line 1500.Redistribution line 1500 is extended in the first photoimageable dielectric layer 1410, and can be electrically connected To the inside connector 1201 of semiconductor element 1200.Semiconductor element 1200 can have the 3rd surface 1206 relative to each other With the 4th surface 1207, and internal connector 1201 can be arranged on the 4th surface 1207 of semiconductor element 1200. The outside that wafer-level packaging part 100 can also include being arranged on the planar top surface 1450P of the second photoimageable dielectric layer 1450 connects Fitting 1600.Joint outer part 160 is extended in the second photoimageable dielectric layer 1450, and may be electrically connected to redistribution line 1500 trace patterns 1550.Joint outer part 1600 can have the shape of soldered ball.
Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29 and Figure 30 are exemplified with according to embodiment party The sectional view of the expression of the example of the method for the manufacture wafer-level packaging part of formula.
Reference picture 21, can provide protection wafer 4100W and be fanned out to the manufacturing technology using wafer-level packaging part to manufacture Semiconductor package part.It can be semiconductor crystal wafer or semiconductor substrate to protect wafer 4100W, for example, Silicon Wafer.In some realities Apply in mode, the wafer that protection wafer 4100W can be made up of the material different from Silicon Wafer.In some other embodiments In, protection wafer 4100W can by CTE substantially with the main body of the semiconductor element 4200 that is attached to protection wafer 4100W Material composition equal CTE.In such a case, it is possible to suppress due to the CTE difference between semiconductor element and protective substrate Some caused failures (for example, warpage).If for example, each in semiconductor element 4200 has silicon main body, protected Wafer 4100W can be made up of silicon materials.
Each other relative first surface 4101 and a second surface 4103 can be had by protecting wafer 4100W, and can be Protect and alignment mark 4110 is formed at wafer 4100W first surface 4101.When reconstituting transistor in subsequent handling During core 4200, alignment mark 4110 is used as assigning the reference marker of the position of semiconductor element 4200.Protection is brilliant Circle 4100W can include the borderline region between multiple chip mounting areas 4105 and the multiple chip mounting area 4105 4106.Semiconductor element 4200 can be separately mounted on chip mounting area 4105, and borderline region 4106 can be used Make road plan.Therefore, borderline region 4106 can surround chip mounting area 4105.Alignment mark 4110 can be arranged on border With adjacent with chip mounting area 4105 in region 4106.Alignment mark 4110 can be formed with than protection wafer The low or high surface of 4100W first surface 4101.For example, alignment mark 4110 can be by protection wafer 4100W's A part for first surface 4101 carries out selective etch and is formed with groove shapes or concave.Therefore, may be used So that accurate alignment is realized using alignment mark 4110 in subsequent handling.That is, protection wafer 4100W the first table Level error between the basal surface of face 4101 and alignment mark 4110 can be produced with high-resolution image, and can be made With with high-resolution alignment mark image come accurately set or identification protecting wafer 4100W ad-hoc location.
Conductive layer can be formed on the first surface 4101 including alignment mark 4110, be used to protect semiconductor to provide First screen layer 4150 of the tube core 4200 from electromagnetic interference (hereinafter, being referred to as " EMI ").Can be by using chemical gaseous phase Deposition (CVD) process is coated with metal level as process deposition such as layers of copper to form first screen layer 4150.If protected It is Silicon Wafer to protect wafer 4100W, then can utilize the equipment used in semiconductor fabrication is used to manufacture wafer scale envelope to perform Whole processes of piece installing.
Semiconductor element 4200 can be arranged on protection wafer 4100W first surface 4101 to use alignment mark 4110 are aligned with chip mounting area 4105 respectively, and semiconductor element 4200 can be separately mounted on chip mounting area On 4105.Each semiconductor element 4200 has the 3rd surface 4206 of the first surface 4101 in face of protection wafer 4100W, and And adhesive layer 4300 can be set on the 3rd surface 4206 of semiconductor element 4200.For example connect the inside connector of pad 4201 can be arranged on the 4th surface 4207 opposite with protection wafer 4100W of semiconductor element 4200.Therefore, partly lead Body tube core 4200 can use adhesive layer 4300 to be installed on protection wafer 4100W.It is brilliant that adhesive layer 4300 can provide protection Permanent engagement between circle 4100W and semiconductor element 4200, protection wafer 4100W is fixed to by semiconductor element 4200. With for temporary carrier (or processing supporting member) temporary attachment to be arrived in the general technology for manufacturing wafer-level packaging part The temporary adhesion layer of semiconductor element is different, adhesive layer 4300 can provide protection wafer 4100W and semiconductor element 4200 it Between irreversible engagement.If UV ray is irradiated in temporary adhesion layer, temporary adhesion layer can lose its bonding strength.Cause This, can use UV ray to separate temporary carrier (or processing supporting member) with semiconductor element.In embodiments, glue Close the solidify afterwards that layer 4300 can be installed in semiconductor element 4200 on protection wafer 4100W.In this case, even if UV ray is irradiated on cured adhesive layer 4300, and cured adhesive layer 4300 will not also lose its bonding strength.Bonding Layer 4300 can include the epoxy resin ingredient as curable adhesive composition.Because adhesive layer 4300 is by semiconductor element 4200 are securely engaged and are fixed to protection wafer 4100W, therefore adhesive layer 4300 can suppress partly to lead during subsequent handling The displacement of body tube core 4200.In the disclosure, protect wafer 4100W not separated with semiconductor element 4200, and protect A wafer 4100W part may be constructed a part for each packaging part.Therefore, it is possible to use can be by semiconductor element 4200 It is permanently attached to protect wafer 4100W irreversible jointing material as adhesive layer 4300.
In some embodiments, adhesive layer 4300 can include thermal interfacial material composition or heat conduction composition, to provide Radiate or distribute the hot path produced by the operation of semiconductor element 4200.If including such as metal in adhesive layer 4300 Heat conduction composition as particle or thermal interfacial material composition, then the heat produced in semiconductor element 4200 can be by more easily It is dispersed into first screen layer 4150 and protection wafer 4100W.Protecting wafer 4100W thermal conductivity can be higher than in subsequent handling In be formed surround semiconductor element 4200 photosensitive material layer (the 4410 of Figure 26 and 4450) thermal conductivity.It therefore, it can More effectively distribute the heat produced in semiconductor element 4200.
For example connection pad inside connector 4201 can be arranged on semiconductor element 4200 with protection wafer On the 4th opposite 4100W surface 4207.Therefore, semiconductor element 4200 can be installed on protection wafer 4100W, so that Obtain surface (that is, fourth surface opposite with protection wafer 4100W that internal connector 4201 is arranged on semiconductor element 4200 4207) on.Semiconductor element 4200 can be separately positioned on by the chip installation area separated from one another of borderline region 4106 On domain 4105.Therefore, semiconductor element 4200 can be by arranged side by side in first screen layer 4150.
Reference picture 22, can form the first photoimageable dielectric layer 4410 to cover semiconductor element in first screen layer 4150 4200.As described in reference picture 9, Figure 10 and Figure 11, the first photoimageable dielectric film can be attached to the by using lamination process One screen layer 4150 and semiconductor element 4200 and make to be attached to the first of first screen layer 4150 and semiconductor element 4200 Photoimageable dielectric film planarizes to form the first photoimageable dielectric layer 4410.As a result, the first photoimageable dielectric layer 4410 can have flat Top surface 4410P.First photoimageable dielectric layer 4410 can include such as light-sensitive polyimide film or photosensitive polybenzoxazoles film Such photopolymer film.In some embodiments, the first photoimageable dielectric layer 4410 can be by including epoxy resin ingredient Light-sensitive surface formed.Due to the first photoimageable dielectric layer include sensitising agent, therefore the first photoimageable dielectric layer 1410 be exposed to light The a part of of (such as UV ray) can have with the first photoimageable dielectric layer 4410 without exposure to light (such as UV ray) The solubility of the different solubility of another part.
Even if first surface 4101 is arranged on first surface 4101 due to alignment mark 4110 and semiconductor element 4200 Above and with uneven surface, the first photoimageable dielectric layer 4410 can also have planar top surface 4410P.Due to first photosensitive Jie Electric layer 4410 have planar top surface 4410P, therefore, it is possible in the case of no pattern distortion the first photoimageable dielectric layer Fine pattern is formed on 4410 planar top surface 4410P.I.e. it is capable to in the case of no pattern distortion The interconnection line with finer pitch is formed on the planar top surface 4410P of one photoimageable dielectric layer 4410.
Reference picture 23, can form the first opening portion 4411, so that semiconductor element in the first photoimageable dielectric layer 4410 4200 part (for example, internal connector 4201) exposure.First opening portion 4411 can be formed photosensitive through first Dielectric layer 4410.While the first opening portion 4411 are formed, groove can also be formed in the first photoimageable dielectric layer 4410 4413, so that the part exposure of first screen layer 4150.Groove 4413 can be formed to make first screen layer 4150 with The overlapping part exposure of borderline region 4106 as road plan.Because groove 4413 is formed along borderline region 4106, therefore Groove 4413 can surround semiconductor element 4200.First photoimageable dielectric layer 4410 can be separated into multiple by groove 4413 Pattern, and the first photoimageable dielectric layer 4410 side wall 4410S can be exposed by groove 4413.
First opening portion 4411 and groove 4413 can be by optionally making a part for the first photoimageable dielectric layer 4410 Exposed to such as UV ray light and the first photoimageable dielectric layer 4410 exposed developed and be formed to run through the One photoimageable dielectric layer 4410.In this case, because the first photoimageable dielectric layer 4410 is formed by photoimageable dielectric film, therefore can be with Photo-mask process is directly applied to form the first opening portion 4411 and groove 4413 on first photoimageable dielectric layer 4410.Therefore, immediately In the case of any additional Other substrate materials of no use, the first opening portion 4411 and groove 4413 can also be formed.
Reference picture 24, can be formed on the first photoimageable dielectric layer 4410 with the first opening portion 4411 and groove 4413 Resist patterns 4700.Resist patterns 4700 is used as mask, for example, being coated with mask for form redistribution line. Anticorrosive additive material can be by being coated on the first photoimageable dielectric layer 4410 and using exposure process by Resist patterns 4700 Anticorrosive additive material is patterned with developing procedure and formed.Resist patterns 4700 can be formed to make the first opening portion 4411 and groove 4413 expose and make the first photoimageable dielectric layer 4410 planar top surface 4410P with the first opening portion 4411 Adjacent part exposure.Resist patterns 4700 can be formed to limit the region for being provided with redistribution line.
Reference picture 25, can pass through the flat of Resist patterns (4700 of Figure 24) exposure in the first photoimageable dielectric layer 4410 On smooth top surface 4410P and in the first opening portion 4411 exposed by Resist patterns 4700 and formed again in groove 4413 Distribute line 4500.It is then possible to remove Resist patterns 4700.Resist patterns 4700 may be used as limiting redistribution line 4500 Shape patterned mask.Redistribution line 4500 can be by by being deposited on by resist comprising copper with being coated with layer-selective Formed on the first photoimageable dielectric layer 4410 that pattern 4700 exposes, and Resist patterns 4700 can be removed.Alternatively, then Distribute line 4500 can by by the conductive layer deposition comprising copper in the first photoimageable dielectric layer 4410 and Resist patterns 4,700 2 Person is upper and peels off Resist patterns 4700 and is formed.
After Resist patterns 4700 is peeled off to be patterned to conductive layer, in the flat of the first photoimageable dielectric layer 4410 Remaining conductive pattern can correspond to redistribution line 4500 on smooth top surface 4410P and in the first opening portion 4411, and And remaining conductive pattern can correspond to secondary shielding layer 4510 in groove 4413.Secondary shielding layer 4510 can be formed To be contacted with the first screen layer 4150 exposed by groove 4413.Therefore, secondary shielding layer 4510 may be electrically connected to first Screen layer 4150.Therefore, first screen layer 4150 and secondary shielding layer 4510 can surround the basal surface of semiconductor element 4200 (that is, the 3rd surface 4206) and side wall, are used to protect semiconductor element 4200 from EMI EMI screening cages to constitute.At some In embodiment, secondary shielding layer 4510 and redistribution line 4500 can be formed in the following manner：With the first opening Conductive layer is deposited in the whole surface of the first photoimageable dielectric layer 4410 of portion 4411 and groove 4413, forms against corrosion on the electrically conductive Agent pattern (is not illustrated), and conductive layer is etched as etching mask by using Resist patterns.
Each redistribution line 4500 can be formed the planar top surface for including being located at the first photoimageable dielectric layer 4410 4410P it is upper for use as in the trace patterns 4550 of interconnection line and one in the first opening portion 4411 with by trace diagram Case 4550 is electrically connected to the through hole 4530 of one in internal connector 4201.Through hole 4530 can be formed perpendicularly through The first photoimageable dielectric layer 4410 on the 4th surface 4207 of semiconductor element 4200 is covered, and is connect with internal connector 4201 Touch.Through hole 4530 can be formed to fill one in the first opening portion 4411.Trace patterns 4550 can extend with setting The part for putting the first photoimageable dielectric layer 4410 between semiconductor element 4200 is overlapped.
Because the first photoimageable dielectric layer 4410 has planar top surface 4410P, therefore Resist patterns is (in Figure 24 4700) it can be formed that there is fine pitch in the case of without pattern distortion.Therefore, its shape passes through resist figure The redistribution line 4500 that case (4700 in Figure 24) is limited can also be formed have essence in the case of no pattern distortion Thin pitch.Therefore, it is possible to increase the number of the redistribution line 4500 formed in finite region.
Reference picture 26, can form the second photoimageable dielectric on the planar top surface 4410P of the first photoimageable dielectric layer 4410 Layer 4450, to cover redistribution line 4500 and secondary shielding layer 4510.Second photoimageable dielectric layer 4450 can be by the way that second be felt Light dielectric film (not illustrating) is arranged in the first photoimageable dielectric layer 4410 and redistribution line 4500 and using lamination process by the Two photoimageable dielectric films are attached to the first photoimageable dielectric layer 4410 and formed.Be attached to the first photoimageable dielectric layer 4410 second is photosensitive Dielectric film can be flattened to provide the second photoimageable dielectric layer 4450 with planar top surface 4450P.Due to second photosensitive Dielectric layer 4450 has planar top surface 4450P, therefore can be more easily formed on the second photoimageable dielectric layer 4450 fine Pattern.In some embodiments, the second photoimageable dielectric layer 4450 can by substantially with the first photoimageable dielectric layer 4410 phase Same material is formed.
Reference picture 27, can be patterned to be formed through the second photoimageable dielectric layer 4450 to the second photoimageable dielectric layer 4450 A part the second opening portion 4451.Each in second opening portion 4451 can be formed to make redistribution line 4500 The part exposure of any one of trace patterns 4550.Some in second opening portion 4451 can be formed not with partly leading Body tube core 4200 is overlapped.That is, some in the second opening portion 4451 can be formed on borderline region 4106.
Reference picture 28, joint outer part 4600 can be attached respectively to the trace patterns exposed by the second opening portion 4451 4550.Therefore, joint outer part 4600 may be electrically connected to trace patterns 4550.Joint outer part 4600 can have soldered ball Shape.Alternatively, joint outer part 4600 can have the shape of projection.Some in joint outer part 4600 can be positioned Not overlapped with semiconductor element 4200.The borderline region that trace patterns 4550 are extended between chip mounting area 4105 On 4106 semiconductor package part is fanned out to realize.
Reference picture 29, can perform reduction steps to reduce protection wafer 4100W thickness.That is, guarantor can be made Shield wafer 4100W second surface 4103 is recessed to provide recessed second surface 4103B.Can be by protection wafer The 4100W application grinding process of second surface 4103 performs reduction steps.Alternatively, can be by protection wafer 4100W Second surface 4103 applied chemistry mechanical polishing (CMP) process or eatch-back process perform reduction steps.
Reference picture 30, can use separation circuit along 4106 pair second of borderline region between chip mounting area 4105 Photoimageable dielectric the 4450, first photoimageable dielectric of layer layer 4410 and the protection wafer 4100W through being thinned are cut, therefore are provided each other The wafer-level packaging part 400 and 401 of separation.For example, saw blade 4800 can be arranged on the borderline region 4106 as road plan, And saw blade 4800 can be used along borderline region 4106 to photoimageable dielectric layer 4450 and 4410 and the protection wafer through being thinned 4100W is cut to produce the wafer-level packaging part 400 and 401 separated each other.It is every in wafer-level packaging part 400 and 401 One still can include a part of the protection wafer 4100W through being thinned, i.e. unit protection wafer 4100U.Therefore, unit Protection wafer 4100U still can cover the 3rd surface 4206 of semiconductor element 4200 to protect semiconductor element 4200.
Figure 31 is the sectional view of the expression of the example exemplified with the wafer-level packaging part 400 according to embodiment.
Reference picture 31, wafer-level packaging part 400 can be corresponding with being fanned out to semiconductor package part.Wafer-level packaging part 400 can With including with each other relative first surface 4101 and second surface 4103B unit protection wafer 4100U.Wafer-level packaging Part 400 can also include the first screen layer 4150 of covering unit protection wafer 4100U first surface 4101.Wafer-level packaging Part 400 can be attached to the semiconductor element 4200 of first screen layer 4150 including the use of adhesive layer 4300.Wafer-level packaging part 400 can include covering semiconductor element 4200 and the first photoimageable dielectric with side wall 4410S and planar top surface 4410P Layer 4410.Wafer-level packaging part 400 can additionally include the side wall 4410S of the first photoimageable dielectric of covering layer 4410 and flat top Surface 4410P the second photoimageable dielectric layer 4450.Second photoimageable dielectric layer 4450 can have side wall 4450S and planar top surface 4450P.Secondary shielding layer 4510 can be arranged on the side wall of the second photoimageable dielectric layer 4450 and the first photoimageable dielectric layer 4410 Between 4410S.That is, secondary shielding layer 4510 can be configured to cover the side wall of the first photoimageable dielectric layer 4410 4410S.Secondary shielding layer 4510 can protect the first screen layer 4150 of wafer 4100U first surface 4101 with covering unit Electrical connection.
Wafer-level packaging part 400 can also include the top surface 4410P and second for being arranged on the first photoimageable dielectric layer 4410 Redistribution line 4500 between the basal surface of photoimageable dielectric layer 4450.Redistribution line 4500 extends to the first photoimageable dielectric layer In 4410, and it may be electrically connected to the inside connector 4201 of semiconductor element 4200.Redistribution line 4500 and secondary shielding Layer 4510 can be provided by being patterned to single conductive layer.Secondary shielding layer 4510 can extend with first screen layer 4150 part is overlapped.
Semiconductor element 4200 can have the 3rd surface 4206 and the 4th surface 4207 relative to each other, and inside connects Fitting 4201 can be arranged on the 4th surface 4207 of semiconductor element 4200.Each in redistribution line 4500 can be with Including through the first photoimageable dielectric layer 4410 a part through hole 4530 and be arranged on the first photoimageable dielectric layer 4410 top Trace patterns 4550 on the 4410P of surface.Wafer-level packaging part 400 can also include the outside for being electrically connected to redistribution line 4500 Connector 4600.
Figure 32 is existed exemplified with including the storage card 7800 with least one semiconductor package part according to embodiment The block diagram of the expression of the example of interior electronic system.Storage card 7800 includes memory as such as nonvolatile semiconductor memory member 7810 and storage control 7820.Memory 7810 and storage control 7820 can be with data storage or the numbers of reading storage According to.Memory 7810 and/or storage control 7820 are one or more in the packaging part according to embodiment including being arranged on Individual semiconductor chip.
Memory 7810 can include the nonvolatile semiconductor memory member for applying the technology of embodiment.Storage control 7820 can be with control memory 7810, to read stored data in response to the read/write requests from main frame 7830 Or stored data.
Figure 33 is the table of the example exemplified with the electronic system 8710 including at least one packaging part according to embodiment The block diagram shown.Electronic system 8710 can include controller 8711, input/output device 8712 and memory 8713.Controller 8711st, input/output device 8712 and memory 8713 can move the bus 8715 of paths traversed by providing data And be engaged with each other.
In one embodiment, controller 8711 can include one or more microprocessors, Digital Signal Processing Device, microcontroller and/or it is able to carry out logical device with these component identical functions.Controller 8711 or memory 8713 One or more semiconductor package parts according to embodiment of the present disclosure can be included.Input/output device 8712 can be with It is included at least one selected among keypad, keyboard, display device, touch-screen etc..Memory 8713 is to be used to store number According to device.Memory 8713 can store the data to be performed by controller 8711 and/or order etc..
Memory 8713 can include volatile memory device as such as DRAM and/or such as flash memory is so Nonvolatile semiconductor memory member.For example, flash memory can be mounted to as such as mobile terminal or desktop computer Information processing system.Flash memory may be constructed solid state hard disc (SSD).In this case, electronic system 8710 can be by Mass data is steadily stored in flash memory system.
Electronic system 8710 can also include interface 8714, the interface 8714 be configured as to communication network send data with And receive data from communication network.Interface 8714 can be wire type or wireless type.For example, interface 8714 can include day Line or wireline transceiver or wireless transceiver.
Electronic system 8710 may be implemented as mobile system, personal computer, industrial computer or perform various work( The flogic system of energy.For example, mobile system can be personal digital assistant (PDA), portable computer, tablet PC, shifting Mobile phone, smart phone, radio telephone, laptop computer, storage card, digital music system and information transmission/reception system Any one in system.
If electronic system 8710 is the equipment for being able to carry out radio communication, electronic system 8710 can be used in such as CDMA (CDMA), GSM (global system for mobile communications), NADC (north American digital cellular), (the enhanced time-division is more by E-TDMA Location), WCDMA (WCDMA), CDMA2000, LTE (Long Term Evolution) and Wibro (wireless broadband internet) communication system In system.
For illustrative purposes, it has been disclosed that embodiment of the present disclosure.Those skilled in the art will understand, energy It is enough do not depart from the disclosure and appended scope and spirit of the claims in the case of carry out various modifications, add and replace Change.
The cross reference of related application
This application claims the korean patent application No.10-2015-0177492 submitted on December 11st, 2015 and in The priority for the korean patent application No.10-2016-0034059 that on March 22nd, 2016 submits, these korean patent applications lead to Way of reference is crossed intactly to be incorporated into herein.

Claims (21)

1. a kind of wafer-level packaging part, the wafer-level packaging part includes：
Alignment mark, the alignment mark is arranged at the first surface of protection wafer；
Semiconductor element, it is brilliant that the semiconductor element is arranged on the protection in the way of being separated with the alignment mark On the round first surface；
First photoimageable dielectric layer, the first photoimageable dielectric layer covers the semiconductor element and with planar top surface；
Second photoimageable dielectric layer, the planar top surface of the second photoimageable dielectric layer covering the first photoimageable dielectric layer；
Redistribution line, the redistribution line is arranged between the first photoimageable dielectric layer and second photoimageable dielectric layer, And it is electrically connected to the semiconductor element through through the first opening portion of first photoimageable dielectric layer；And
Joint outer part, the joint outer part is arranged on second photoimageable dielectric layer, and through through described the Second opening portion of two photoimageable dielectrics layer is electrically connected to the redistribution line.
2. wafer-level packaging part according to claim 1, wherein, the protection wafer includes Silicon Wafer.
3. wafer-level packaging part according to claim 1, wherein, at least one in the redistribution line extend to it is described The perimeter of semiconductor element.
4. wafer-level packaging part according to claim 1, wherein, the thickness of the protection wafer is more than the transistor The thickness of core.
5. wafer-level packaging part according to claim 1, wherein, the second photoimageable dielectric layer include planar top surface with And the side wall being aligned with the side wall of first photoimageable dielectric layer.
6. wafer-level packaging part according to claim 1,
Wherein, the side wall of the first photoimageable dielectric layer and the side wall of second photoimageable dielectric layer and the side of the protection wafer Wall is aligned.
7. wafer-level packaging part according to claim 1, wherein, the joint outer part has the shape of soldered ball.
8. wafer-level packaging part according to claim 1, the wafer-level packaging part also includes：
Adhesive layer, the adhesive layer is located between the semiconductor element and the protection wafer.
9. wafer-level packaging part according to claim 1, wherein, the second photoimageable dielectric layer has the external connection Part is arranged on the planar top surface on the second photoimageable dielectric layer.
10. a kind of wafer-level packaging part, the wafer-level packaging part includes：
First screen layer, the first surface of the first screen layer covering protection wafer；
Semiconductor element, the semiconductor element is installed in the first screen layer；
First dielectric layer, first dielectric layer covers the semiconductor element and with top surface and side wall；
Second dielectric layer, second dielectric layer covers the top surface and the side wall of first dielectric layer；
Secondary shielding layer, the secondary shielding layer is arranged on the side wall and second dielectric layer of first dielectric layer Between, to cover the side wall of first dielectric layer；
Redistribution line, the redistribution line be arranged on the top surface of first dielectric layer and second dielectric layer it Between, and it is electrically connected to the semiconductor element through the first opening portion through first dielectric layer；And
Joint outer part, the joint outer part is arranged on second dielectric layer, and is situated between through through described second Second opening portion of electric layer is electrically connected to the redistribution line.
11. wafer-level packaging part according to claim 10, the wafer-level packaging part also includes alignment mark, the alignment Mark is arranged at the first surface of the protection wafer.
12. wafer-level packaging part according to claim 10, wherein, the top surface of first dielectric layer is flat Surface.
13. wafer-level packaging part according to claim 12, wherein, the planar top surface of first dielectric layer is configured To enable Resist patterns to be formed with fine pitch and there is no pattern distortion.
14. wafer-level packaging part according to claim 10, wherein, the top surface of second dielectric layer is flat Surface.
15. wafer-level packaging part according to claim 10, wherein, first dielectric layer and second dielectric layer are Photoimageable dielectric layer.
16. wafer-level packaging part according to claim 10, wherein, the secondary shielding layer is extended to and first screen The part for covering layer is overlapped.
17. wafer-level packaging part according to claim 10, wherein, the secondary shielding layer is with covering the protection wafer The first surface the first screen layer electrical connection.
18. wafer-level packaging part according to claim 10, the wafer-level packaging part also includes；
Adhesive layer, the adhesive layer is located between the semiconductor element and the first screen layer.
19. a kind of method for manufacturing wafer-level packaging part, this method comprises the following steps：
Alignment mark is formed at the first surface of protection wafer；
Semiconductor element is abreast arranged on the first surface of the protection wafer using the alignment mark；
First photoimageable dielectric film is attached to the protection wafer and the semiconductor element, the transistor is buried to be formed The first photoimageable dielectric layer of core；
The top surface opposite with the protection wafer of first photoimageable dielectric layer is planarized；
The part of planarized the first photoimageable dielectric layer is directly exposed；
Exposed the first photoimageable dielectric layer is developed, makes the part of each in the semiconductor element to be formed Exposed opening portion；
Redistribution line is formed on developed the first photoimageable dielectric layer, wherein, the redistribution line is electric through the opening portion It is connected to the semiconductor element；
Form the second photoimageable dielectric layer of the covering redistribution line；
Joint outer part is formed on second photoimageable dielectric layer, wherein, the joint outer part is photosensitive by described second Dielectric layer is electrically connected to the redistribution line；And
Reduce the thickness of the protection wafer.
20. method according to claim 19, wherein, by the top surface planarization of first photoimageable dielectric layer Step comprises the following steps：
The planarization component with flat surfaces is set on first photoimageable dielectric layer, to cause the planarization component The flat surfaces are in face of first photoimageable dielectric layer；And
The planarization component is pressed down in case of heating, so that the top surface of first photoimageable dielectric layer is put down It is smooth.
21. a kind of method for manufacturing wafer-level packaging part, this method comprises the following steps：
First screen layer is formed on the first surface of protection wafer；
Semiconductor element is abreast installed in the first screen layer；
The first photoimageable dielectric film is attached to the first screen layer and the semiconductor element using lamination process, to be formed First photoimageable dielectric layer；
First photoimageable dielectric layer is patterned, to form the part exposure of each made in the semiconductor element Opening portion and make the first screen layer a part exposure groove；
Form the secondary shielding layer and redistribution line of the side wall of the covering groove, the redistribution line is arranged on described the On the top surface of one photoimageable dielectric layer and it is electrically connected to the semiconductor element through the opening portion；
Form the second photoimageable dielectric layer for covering the redistribution line and the secondary shielding layer；And
Joint outer part is formed on second photoimageable dielectric layer,
Wherein, the joint outer part extends in the second photoimageable dielectric layer to be electrically connected to the redistribution line.
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