TWI692842B - Semiconductors, packages, wafer level packages, and methods of manufacturing the same - Google Patents

Semiconductors, packages, wafer level packages, and methods of manufacturing the same Download PDF

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TWI692842B
TWI692842B TW105132551A TW105132551A TWI692842B TW I692842 B TWI692842 B TW I692842B TW 105132551 A TW105132551 A TW 105132551A TW 105132551 A TW105132551 A TW 105132551A TW I692842 B TWI692842 B TW I692842B
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wafer
dielectric layer
layer
photosensitive dielectric
semiconductor die
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TW105132551A
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TW201724386A (en
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崔亨碩
成基俊
金鍾薰
劉榮槿
裵弼淳
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南韓商愛思開海力士有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.

Description

半導體、封裝件、晶圓級封裝件以及其製造方法 Semiconductor, package, wafer-level package and method of manufacturing the same

本公開的實施方式可以總體上涉及半導體封裝件(package)，並且更具體地涉及晶圓級封裝件及其製造方法。 Embodiments of the present disclosure may relate generally to semiconductor packages, and more specifically to wafer-level packages and methods of manufacturing the same.

相關申請的交叉引用Cross-reference of related applications

本申請要求於2015年12月11日提交的韓國專利申請No.10-2015-0177492以及於2016年3月22日提交的韓國專利申請No.10-2016-0034059的優先權，這些韓國專利申請通過引用方式被完整地併入到本文中。 This application claims the priority of Korean Patent Application No. 10-2015-0177492 filed on December 11, 2015 and Korean Patent Application No. 10-2016-0034059 filed on March 22, 2016. These Korean patent applications It is incorporated by reference in its entirety.

電子系統中所採用的半導體裝置可以包括各種電子電路元件。所述電子電路元件可以被整合在半導體基板中和/或半導體基板上，以構成半導體晶片或者半導體晶粒(die)。半導體晶片或者半導體晶粒可以被包封以提供半導體封裝件。半導體封裝件可以被提供以保護該半導體封裝件中的半導體晶片或者半導體晶粒免受外力影響。半導體封裝件被廣泛地用在諸如電腦、移動系統或者資料存儲媒體這樣的電子系統中的每一個中。近來，隨著諸如智慧型手機這樣的更輕且更小的電子系統的開發，對薄的半導體封裝件的需求不斷增加。 The semiconductor device employed in the electronic system may include various electronic circuit elements. The electronic circuit element may be integrated in and/or on the semiconductor substrate to constitute a semiconductor wafer or a semiconductor die. The semiconductor wafer or semiconductor die may be encapsulated to provide a semiconductor package. The semiconductor package may be provided to protect the semiconductor wafer or semiconductor die in the semiconductor package from external forces. Semiconductor packages are widely used in each of electronic systems such as computers, mobile systems, or data storage media. Recently, with the development of lighter and smaller electronic systems such as smart phones, the demand for thin semiconductor packages has been increasing.

由於對薄的半導體封裝件的需求不斷增加，因此半導體封裝件中構成半導體晶片的半導體基板的厚度已經減小。因此，已經集中大量的精力以防止半導體封裝件或者半導體基板在封裝處理期間翹曲。此外，由於半導體封裝件按比例縮小並且半導體封裝件的連接件(例如，連接焊墊)的數目增加，因此已經提出很多技術來實現具有精細節距的焊墊的高性能半導體封裝件。 Due to the increasing demand for thin semiconductor packages, the thickness of the semiconductor substrate constituting the semiconductor wafer in the semiconductor package has been reduced. Therefore, a lot of effort has been concentrated to prevent the semiconductor package or the semiconductor substrate from warping during the packaging process. In addition, as semiconductor packages are scaled down and the number of connectors (eg, connection pads) of the semiconductor packages is increased, many techniques have been proposed to realize high-performance semiconductor packages with fine-pitch pads.

根據各種實施方式，可以提供封裝件、半導體和晶圓級封裝件。根據各種實施方式，可以提供製造封裝件、半導體和晶圓級封裝件的方法。一種製造晶圓級封裝件的方法可以包括形成對準標記。所述方法可以包括將半導體晶粒安裝在第一表面上。所述方法可以包括將第一感光介電膜附接到保護晶圓。所述方法可以包括將第一感光介電層的與保護晶圓相反的頂表面平坦化。所述方法可以包括將經平坦化的第一感光介電層的部分曝光。所述方法可以包括對經曝光的第一感光介電層進行顯影。所述方法可以包括在第一感光介電層上形成再分配線(redistribution line)。所述再分配線可以被形成為穿過開口部電連接到半導體晶粒。可以形成第二感光介電層以覆蓋所述再分配線。 According to various embodiments, packages, semiconductors, and wafer-level packages may be provided. According to various embodiments, methods of manufacturing packages, semiconductors, and wafer-level packages may be provided. A method of manufacturing a wafer-level package may include forming alignment marks. The method may include mounting the semiconductor die on the first surface. The method may include attaching the first photosensitive dielectric film to the protection wafer. The method may include planarizing the top surface of the first photosensitive dielectric layer opposite to the protection wafer. The method may include exposing a portion of the planarized first photosensitive dielectric layer. The method may include developing the exposed first photosensitive dielectric layer. The method may include forming a redistribution line on the first photosensitive dielectric layer. The redistribution line may be formed to be electrically connected to the semiconductor die through the opening portion. A second photosensitive dielectric layer may be formed to cover the redistribution line.

10‧‧‧載體 10‧‧‧Carrier

20‧‧‧晶粒 20‧‧‧ grain

21‧‧‧連接焊墊 21‧‧‧ connection pad

23‧‧‧表面 23‧‧‧surface

30‧‧‧臨時黏合劑 30‧‧‧Temporary adhesive

40‧‧‧EMC層 40‧‧‧EMC layer

41‧‧‧表面 41‧‧‧Surface

50‧‧‧絕緣層 50‧‧‧Insulation

51‧‧‧開口部 51‧‧‧Opening

60‧‧‧再分配線 60‧‧‧ Redistribution line

60A‧‧‧第一部分 60A‧‧‧Part 1

60B‧‧‧第二部分 60B‧‧‧Part 2

60C‧‧‧第三部分 60C‧‧‧Part Three

63‧‧‧區域 63‧‧‧Region

70‧‧‧第二絕緣層 70‧‧‧Second insulation layer

81‧‧‧開口部 81‧‧‧ opening

81E‧‧‧開口部 81E‧‧‧Opening

400‧‧‧晶圓級封裝件 400‧‧‧wafer-level package

401‧‧‧晶圓級封裝件 401‧‧‧ Wafer-level package

1101‧‧‧第一表面 1101‧‧‧First surface

1100U‧‧‧單位區域 1100U‧‧‧Unit area

1100W‧‧‧保護晶圓 1100W‧‧‧Protection wafer

1103‧‧‧第二表面 1103‧‧‧Second surface

1103B‧‧‧第二表面 1103B‧‧‧Second surface

1105‧‧‧晶片安裝區域 1105‧‧‧Chip installation area

1106‧‧‧邊界區域 1106‧‧‧Border area

1101‧‧‧第一表面 1101‧‧‧First surface

1110‧‧‧對準標記 1110‧‧‧Alignment mark

1200‧‧‧半導體晶粒 1200‧‧‧Semiconductor die

1201‧‧‧內部連接件 1201‧‧‧Internal connector

1206‧‧‧第三表面 1206‧‧‧The third surface

1207‧‧‧第四表面 1207‧‧‧Fourth surface

1300‧‧‧黏合層 1300‧‧‧ adhesive layer

1410‧‧‧第一感光介電層 1410‧‧‧First photosensitive dielectric layer

1410A‧‧‧第一感光介電層 1410A‧‧‧First photosensitive dielectric layer

1410F‧‧‧第一感光介電膜 1410F‧‧‧The first photosensitive dielectric film

1410H‧‧‧第一部分 1410H‧‧‧Part 1

1410L‧‧‧第二部分 1410L‧‧‧Part II

1410P‧‧‧平坦表面 1410P‧‧‧flat surface

1410U‧‧‧不平坦表面 1410U‧‧‧Uneven surface

1411‧‧‧第一開口部 1411‧‧‧First opening

1450‧‧‧第二感光介電層 1450‧‧‧Second photosensitive dielectric layer

1450P‧‧‧平坦表面 1450P‧‧‧flat surface

1451‧‧‧第二開口部 1451‧‧‧Second opening

1490‧‧‧平坦化構件 1490‧‧‧Flat member

1490P‧‧‧平坦表面 1490P‧‧‧flat surface

1500‧‧‧再分配線 1500‧‧‧ Redistribution line

1530‧‧‧通孔 1530‧‧‧Through hole

1550‧‧‧跡線圖案 1550‧‧‧ trace pattern

1600‧‧‧外部連接件 1600‧‧‧External connector

1700‧‧‧光阻圖案 1700‧‧‧Photoresist pattern

1800‧‧‧鋸片 1800‧‧‧Saw Blade

4100W‧‧‧保護晶圓 4100W‧‧‧Protection wafer

4101‧‧‧第一表面 4101‧‧‧First surface

4103‧‧‧第二表面 4103‧‧‧Second surface

4103B‧‧‧第二表面 4103B‧‧‧Second surface

4105‧‧‧晶片安裝區域 4105‧‧‧Chip installation area

4106‧‧‧邊界區域 4106‧‧‧Border area

4110‧‧‧對準標記 4110‧‧‧Alignment mark

4150‧‧‧第一遮罩層 4150‧‧‧The first mask layer

4200‧‧‧半導體晶粒 4200‧‧‧Semiconductor die

4201‧‧‧內部連接件 4201‧‧‧Internal connector

4206‧‧‧第三表面 4206‧‧‧The third surface

4207‧‧‧第四表面 4207‧‧‧Fourth surface

4300‧‧‧黏合層 4300‧‧‧ adhesive layer

4410‧‧‧第一感光介電層 4410‧‧‧The first photosensitive dielectric layer

4410P‧‧‧平坦頂表面 4410P‧‧‧flat top surface

4410S‧‧‧側壁 4410S‧‧‧Sidewall

4411‧‧‧第一開口部 4411‧‧‧First opening

4413‧‧‧溝槽 4413‧‧‧Trench

4450‧‧‧第二感光介電層 4450‧‧‧Second photosensitive dielectric layer

4450P‧‧‧平坦頂表面 4450P‧‧‧flat top surface

4451‧‧‧第二開口部 4451‧‧‧Second opening

4500‧‧‧再分配線 4500‧‧‧ Redistribution line

4510‧‧‧第二遮罩層 4510‧‧‧The second mask layer

4530‧‧‧通孔 4530‧‧‧Through hole

4550‧‧‧跡線圖案 4550‧‧‧ trace pattern

4600‧‧‧外部連接件 4600‧‧‧External connector

4700‧‧‧光阻圖案 4700‧‧‧Photoresist pattern

4800‧‧‧鋸片 4800‧‧‧Saw blade

7800‧‧‧記憶卡 7800‧‧‧Memory card

7810‧‧‧記憶體 7810‧‧‧Memory

7820‧‧‧記憶體控制器 7820‧‧‧Memory Controller

7830‧‧‧主機 7830‧‧‧Host

8710‧‧‧電子系統 8710‧‧‧Electronic system

8711‧‧‧控制器 8711‧‧‧Controller

8712‧‧‧輸入/輸出裝置 8712‧‧‧I/O device

8713‧‧‧記憶體 8713‧‧‧Memory

8714‧‧‧介面 8714‧‧‧Interface

8715‧‧‧匯流排 8715‧‧‧Bus

圖1至圖3是例示了在製造晶圓級封裝件中根據晶粒移位的故障的示例的表示的截面圖。 1 to 3 are cross-sectional views illustrating representations of examples of failures according to die displacement in manufacturing wafer-level packages.

圖4和圖5例示了在製造晶圓級封裝中根據晶粒與環氧樹脂模製化合物之間的非平面化(non-planarity)的故障的示例的表示。 4 and 5 illustrate representations of examples of failures based on non-planarity between die and epoxy molding compound in manufacturing wafer-level packages.

圖6是例示了在製造晶圓級封裝中根據再分配線的圖案密度的圖案失真的示例的表示的截面圖。 6 is a cross-sectional view illustrating an example of a pattern distortion according to the pattern density of redistribution lines in manufacturing a wafer-level package.

圖7至圖19例示了根據實施方式的製造晶圓級封裝件的方法的示例的表示。 7 to 19 illustrate a representation of an example of a method of manufacturing a wafer-level package according to an embodiment.

圖20是例示了根據實施方式的晶圓級封裝件的示例的表示的截面圖。 20 is a cross-sectional view illustrating a representation of an example of a wafer-level package according to an embodiment.

圖21至圖30是例示了根據實施方式的製造晶圓級封裝件的方法的示例的表示的截面圖。 21 to 30 are cross-sectional views illustrating an example of a method of manufacturing a wafer-level package according to an embodiment.

圖31是例示了根據實施方式的晶圓級封裝件的示例的表示的截面圖。 31 is a cross-sectional view illustrating a representation of an example of a wafer-level package according to an embodiment.

圖32是例示了採用包括根據實施方式的封裝件在內的記憶卡的電子系統的示例的表示的區塊圖。 32 is a block diagram illustrating a representation of an example of an electronic system employing a memory card including the package according to the embodiment.

圖33是例示了包括根據實施方式的封裝件在內的電子系統的示例的表示的區塊圖。 33 is a block diagram illustrating a representation of an example of an electronic system including the package according to the embodiment.

本文中使用的術語可以對應於在實施方式中考慮其功能而選擇的詞，並且術語的含義可以根據實施方式所屬的領域中的普通技術人員而被解釋為不同。如果詳細地限定，則術語可以根據所述限定來解釋。除非另外限定，否則本文中使用的術語(包括技術術語和科學術語)具有與實施方式所屬的技術領域中的普通技術人員通常理解的含義相同的含義。 The term used herein may correspond to a word selected in consideration of its function in the embodiment, and the meaning of the term may be interpreted differently according to those of ordinary skill in the art to which the embodiment belongs. If defined in detail, the term can be interpreted according to the definition. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the embodiments belong.

將要理解的是，雖然可以在本文中使用術語第一、第二、第 三等來描述各個元件，但是這些元件不應該受這些術語限制。這些術語僅被用來將一個元件與另一個元件區分開。因此，在不脫離教導的情況下，一些實施方式中的第一元件能夠在其它實施方式中被稱為第二元件。 It will be understood that although the terms first, second, first Third-class to describe each element, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element in some embodiments can be referred to as the second element in other embodiments without departing from the teaching.

還將理解的是，當一個元件被稱作“在”另一元件“上”、“在”另一元件“上方”、“在”另一元件“下方”或者“在”另一元件“下面”時，該元件能夠直接“在”另一元件“上”、直接“在”另一元件“上方”、直接“在”另一元件“下方”或者直接“在”另一元件“下面”，或者也可以存在中間元件。因此，本文中使用的諸如“在…上”、“在…上方”、“在…下方”或者“在…下面”這樣的術語僅是為了描述特定實施方式的目的，而不是旨在限制本公開。 It will also be understood that when an element is referred to as being "on" another element, "above" another element "above", "below" another element "below" or "below" another element ", the element can be directly "on" another element, "above" another element, "below" another element, or "below" another element, Alternatively, there may be intermediate elements. Therefore, terms such as "on", "above", "below", or "below" used herein are for the purpose of describing particular embodiments only, and are not intended to limit the present disclosure .

根據以下實施方式的半導體封裝件可以包括諸如半導體晶粒或者半導體晶片這樣的電子裝置，並且半導體晶粒或者半導體晶片可以通過使用晶粒鋸切製程將諸如包括電路的晶圓這樣的半導體基板分離成多個塊來獲得。半導體晶片可以與記憶體晶片、邏輯晶片或者特定應用積體電路(ASIC)晶片對應。記憶體晶片可以包括整合在半導體基板上的動態隨機存取記憶體(DRAM)電路、靜態隨機存取記憶體(SRAM)電路、快閃記憶體電路、磁隨機存取記憶體(MRAM)電路、電阻式隨機存取記憶體(ReRAM)電路、鐵電隨機存取記憶體(FeRAM)電路或相變隨機存取記憶體(PcRAM)電路。半導體封裝件中的每一個可以包括封裝基板和安裝在封裝基板上的半導體晶片，並且封裝基板可以被用於將半導體晶片電連接到外部裝置。因此，與半導體基板不同，封裝基板可以包括設置在由介電材料組成的基板主體上和/或該基板主體中的電路跡線(trace)。半導體 基板可以是印刷電路板(PCB)。半導體封裝件可以被用在諸如例如但不限於行動電話這樣的通信系統、與生物技術或健康保健關聯的電子系統、或者穿戴式電子系統中。 The semiconductor package according to the following embodiment may include an electronic device such as a semiconductor die or a semiconductor wafer, and the semiconductor die or the semiconductor wafer may separate a semiconductor substrate such as a wafer including a circuit by using a die sawing process Multiple blocks to obtain. The semiconductor chip may correspond to a memory chip, a logic chip, or an application specific integrated circuit (ASIC) chip. The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a flash memory circuit, a magnetic random access memory (MRAM) circuit integrated on a semiconductor substrate, Resistive random access memory (ReRAM) circuit, ferroelectric random access memory (FeRAM) circuit or phase change random access memory (PcRAM) circuit. Each of the semiconductor packages may include a package substrate and a semiconductor wafer mounted on the package substrate, and the package substrate may be used to electrically connect the semiconductor wafer to an external device. Therefore, unlike a semiconductor substrate, a package substrate may include a circuit trace provided on and/or in a substrate body composed of a dielectric material. semiconductor The substrate may be a printed circuit board (PCB). The semiconductor package may be used in a communication system such as, but not limited to, a mobile phone, an electronic system associated with biotechnology or health care, or a wearable electronic system.

在整個說明書中，相同的附圖標記指代相同的元件。因此，即使沒有參照一幅圖提及或描述一個附圖標記，也會參照另一幅圖來提及或描述該附圖標記。此外，即使在一幅圖中未示出一個附圖標記，也會在另一幅圖中提及或描述該附圖標記。 Throughout the specification, the same reference numerals refer to the same elements. Therefore, even if a reference number is not mentioned or described with reference to one figure, the reference number will be mentioned or described with reference to another figure. In addition, even if a reference number is not shown in one figure, the reference number will be mentioned or described in another figure.

本公開可以提供製造晶圓級封裝件的方法以及由此製造的晶圓級封裝件。可以使用具有諸如矽晶圓這樣的晶圓的形狀的保護基板來製造晶圓級封裝件。根據以下實施方式的晶圓級封裝件可以被製造為具有扇出半導體封裝件形式。扇出半導體封裝件中的每一個可以具有如下的結構：即使半導體晶片小於扇出半導體封裝件，半導體晶片也通過設置在模製構件上的再分配線電連接到諸如焊球這樣的外部連接件。 The present disclosure may provide a method of manufacturing a wafer-level package and a wafer-level package manufactured thereby. A wafer-level package may be manufactured using a protective substrate having the shape of a wafer such as a silicon wafer. The wafer-level package according to the following embodiments may be manufactured in the form of a fan-out semiconductor package. Each of the fan-out semiconductor packages may have a structure that even if the semiconductor wafer is smaller than the fan-out semiconductor package, the semiconductor wafer is electrically connected to an external connector such as a solder ball through a redistribution line provided on the molding member .

扇出半導體封裝件(即，扇出晶圓級封裝件)可以通過以下方式來實現：執行用於在使用臨時晶圓作為載體的晶圓上形成諸如環氧樹脂模製化合物(EMC)材料的模製構件的晶圓模製製程，並且通過在模製構件上形成再分配線。然而，在這種情況下，扇出晶圓級封裝件可以呈現諸如差的封裝地形(topography)、易於翹曲、由於晶粒移位而導致的故障、晶片到模具的非平面化等這樣的一些問題。這些問題會在實現包括具有精細節距的互連件的高性能封裝件時成為障礙。也就是說，可能在減小晶圓級封裝件的諸如焊墊這樣的連接件的節距和尺寸以及在減小晶圓級封裝件的互連線的節距和尺寸時存在一些困難。 Fan-out semiconductor packages (ie, fan-out wafer-level packages) can be realized by performing a method for forming a material such as an epoxy molding compound (EMC) on a wafer using a temporary wafer as a carrier The wafer molding process of the molding member, and by forming a redistribution line on the molding member. However, in this case, fan-out wafer-level packages may exhibit such things as poor package topography, susceptibility to warpage, failure due to die shift, non-planar wafer-to-mold, etc. some problems. These problems can become obstacles when implementing high-performance packages that include interconnects with fine pitch. That is, there may be some difficulties in reducing the pitch and size of the connection members such as pads of the wafer-level package and the interconnect line of the wafer-level package.

晶粒移位現象可能由於臨時晶圓與半導體晶片(或者半導體晶粒)之間的臨時接合而發生。臨時晶圓可以通過臨時黏合劑接合到半導體晶片。然而，由於臨時晶圓最終必須被去除，因此臨時黏合劑可以具有相對弱的黏合強度。因此，在晶圓模製製程期間，臨時黏合劑可能由於EMC材料的壓力而變形，以導致半導體晶片的位置移位。在晶圓模製製程之後，EMC材料可以被冷卻以導致EMC材料的收縮。在這種情況下，半導體晶片可以朝向晶圓的中心部移動。因此，半導體晶片的連接焊墊的位置可以改變，以在形成用於限定焊墊開口的絕緣層時導致連接焊墊與用於使連接焊墊暴露的焊墊開口之間的未對準。結構，雖然焊球附接到連接焊墊，但是焊球會與連接焊墊未對準。 The die shift phenomenon may occur due to temporary bonding between the temporary wafer and the semiconductor wafer (or semiconductor die). The temporary wafer may be bonded to the semiconductor wafer by a temporary adhesive. However, because the temporary wafer must eventually be removed, the temporary adhesive may have a relatively weak adhesive strength. Therefore, during the wafer molding process, the temporary adhesive may be deformed due to the pressure of the EMC material to cause the position of the semiconductor wafer to shift. After the wafer molding process, the EMC material can be cooled to cause the EMC material to shrink. In this case, the semiconductor wafer can move toward the center of the wafer. Therefore, the position of the connection pad of the semiconductor wafer may be changed to cause a misalignment between the connection pad and the pad opening for exposing the connection pad when the insulating layer for defining the pad opening is formed. Structure, although the solder balls are attached to the connection pads, the solder balls may not be aligned with the connection pads.

可以在半導體晶片與模製構件之間的邊界處發生晶片到模具的非平面化問題。在臨時黏合劑被提供到臨時晶圓上並且包括半導體晶片的晶圓被定位在臨時黏合劑上之後，可以在用於形成模製構件的模製製程期間對半導體晶片和臨時黏合劑施加高壓力。施加到半導體晶片和臨時黏合劑的高壓力可以導致具有相對低的模量的臨時黏合劑的變形，而具有相對高的模量的半導體晶片幾乎不變形。結果，可以在半導體晶片與模製構件之間的邊界處形成臨時黏合劑的表面高度差。因此，當在後續製程中在半導體晶片和模製構件上面形成再分配線時，臨時黏合劑的表面高度差會導致再分配線的圖案失真。 The wafer-to-mold non-planarization problem may occur at the boundary between the semiconductor wafer and the molding member. After the temporary adhesive is provided on the temporary wafer and the wafer including the semiconductor wafer is positioned on the temporary adhesive, high pressure may be applied to the semiconductor wafer and the temporary adhesive during the molding process for forming the molding member . The high pressure applied to the semiconductor wafer and the temporary adhesive may cause deformation of the temporary adhesive having a relatively low modulus, while the semiconductor wafer having a relatively high modulus hardly deforms. As a result, the surface height difference of the temporary adhesive can be formed at the boundary between the semiconductor wafer and the molding member. Therefore, when a redistribution line is formed on the semiconductor wafer and the molding member in the subsequent process, the surface height difference of the temporary adhesive may cause the pattern of the redistribution line to be distorted.

當再分配線被形成為具有多層結構並且覆蓋再分配線的絕緣層使用旋轉塗覆製程來形成時，根據再分配線的圖案密度，不可能在絕緣層的表面上均勻地執行光微影製程。該非均勻的光微影製程會導致圖案 失真。 When the redistribution line is formed to have a multilayer structure and the insulating layer covering the redistribution line is formed using a spin coating process, according to the pattern density of the redistribution line, it is impossible to perform the photolithography process uniformly on the surface of the insulating layer . This non-uniform photolithography process will cause patterns distortion.

如果封裝件中的具有相對高的熱膨脹係數(CTE)的模製構件(例如，EMC材料)的體積大於具有相對低的熱膨脹係數(CTE)的矽材料的體積，則晶圓可以在用於形成模製構件的晶圓模製製程期間或者該晶圓模製製程之後容易翹曲。在模製構件被形成並且再分配線被形成的同時，可以重複執行加熱步驟和冷卻步驟以導致由於模製構件與矽材料之間的CTE差而導致的應力的集中。因此，晶圓可能容易翹曲。晶圓的翹曲會導致製程設備的故障或製程故障。 If the volume of the molded member (eg, EMC material) with a relatively high coefficient of thermal expansion (CTE) in the package is larger than the volume of the silicon material with a relatively low coefficient of thermal expansion (CTE), the wafer can be used to form a mold The component is easily warped during the wafer molding process or after the wafer molding process. While the molded member is formed and the redistribution line is formed, the heating step and the cooling step may be repeatedly performed to cause concentration of stress due to the CTE difference between the molded member and the silicon material. Therefore, the wafer may be easily warped. Wafer warpage can cause process equipment failure or process failure.

圖1、圖2和圖3是例示了在製造晶圓級封裝件中根據晶粒移位的故障的示例的表示的截面圖。 FIGS. 1, 2 and 3 are cross-sectional views illustrating representations of examples of failures according to die displacement in manufacturing wafer-level packages.

參照圖1，晶粒20可以使用臨時黏合劑30附接到載體10的表面。晶粒20可以附接到載體10，以使得晶粒20的連接焊墊21面對載體10。參照圖2，在EMC層40被形成為覆蓋晶粒20的同時，晶粒20中的至少一個可以橫向移位。結果，與其初始位置相比較，所述晶粒20中的至少一個的位置可以改變。如果晶粒20橫向移位，則晶粒20的連接焊墊21的位置也可以改變。在形成EMC層40之後，可以從晶粒20和EMC層40去除載體10。可以通過減小臨時黏合劑30的黏合強度來去除載體10。臨時黏合劑30的黏合強度可以通過向臨時黏合劑30照射紫外(UV)線或者通過對臨時黏合劑30加熱來減小。參照圖3，絕緣層50可以被形成在EMC層40的表面上以覆蓋晶粒20和晶粒20的連接焊墊21，並且可以形成貫穿絕緣層50的開口部51以使連接焊墊21暴露。然後，可以在絕緣層50上和開口部51中形成再分配線60。如果晶粒20如上所述在形成EMC層40期 間橫向移位，則開口部51可以被形成為與連接焊墊21未對準。結果，如圖3所例示，再分配線60可以與連接焊墊21電斷開，從而導致連接故障。 Referring to FIG. 1, the die 20 may be attached to the surface of the carrier 10 using a temporary adhesive 30. The die 20 may be attached to the carrier 10 so that the connection pad 21 of the die 20 faces the carrier 10. Referring to FIG. 2, while the EMC layer 40 is formed to cover the die 20, at least one of the die 20 may be laterally displaced. As a result, the position of at least one of the crystal grains 20 can be changed compared to its initial position. If the die 20 is laterally displaced, the position of the die 20 to which the pad 21 is connected may also be changed. After the EMC layer 40 is formed, the carrier 10 can be removed from the die 20 and the EMC layer 40. The carrier 10 can be removed by reducing the adhesive strength of the temporary adhesive 30. The adhesive strength of the temporary adhesive 30 can be reduced by irradiating the temporary adhesive 30 with ultraviolet (UV) rays or by heating the temporary adhesive 30. Referring to FIG. 3, an insulating layer 50 may be formed on the surface of the EMC layer 40 to cover the die 20 and the connection pad 21 of the die 20, and an opening 51 penetrating the insulating layer 50 may be formed to expose the connection pad 21 . Then, a redistribution line 60 can be formed on the insulating layer 50 and in the opening 51. If the die 20 is in the stage of forming the EMC layer 40 as described above If it is laterally displaced, the opening 51 may be formed to be misaligned with the connection pad 21. As a result, as illustrated in FIG. 3, the redistribution line 60 may be electrically disconnected from the connection pad 21, thereby causing a connection failure.

圖4和圖5例示了在製造晶圓級封裝中根據晶粒EMC層之間的非平面化的故障的示例的表示。圖4是沿著再分配線60中的任意一條的長度方向截取的垂直截面圖，並且圖5是再分配線60的平面圖。 4 and 5 illustrate representations of examples of failures based on non-planarization between die EMC layers in manufacturing wafer-level packages. 4 is a vertical cross-sectional view taken along the length direction of any one of the redistribution lines 60, and FIG. 5 is a plan view of the redistribution line 60.

參照圖4，絕緣層50的非平面化可以被例示在EMC層40與晶粒20的側壁之間的邊界面上。這是因為在形成EMC層40的同時，與晶粒20接觸的臨時黏合劑(圖2的30)被向下按壓得比與EMC層40接觸的臨時黏合劑(圖2的30)多。因此，可以在晶粒20與EMC層40之間提供高度差。也就是說，高度差D1可以存在於晶粒20的表面23與EMC層40的表面41之間。覆蓋晶粒20和EMC層40的絕緣層50可以由於晶粒20與EMC層40之間的高度差D1而被形成為具有不平坦的表面，並且形成在絕緣層50上的再分配層也可以具有呈現高度差D2的不平坦的表面。再分配線60可以通過對具有高度差D2的再分配層進行圖案化來形成。因此，高度差D2可以影響用於對再分配層進行圖案化以形成再分配線60的光微影製程，並且再分配線60中的每一條可以被形成為具有不均勻的寬度。例如，如果再分配層使用光微影製程和蝕刻製程來圖案化，則可能由於塗覆在再分配層上的光阻層的不均勻的厚度而在光微影製程期間難以調整並最佳化焦點的深度。因此，再分配線60可以被形成為包括與晶粒20交疊並且具有寬度X1的第一部分60A以及與EMC層40交疊並且具有與寬度X1不同的寬度X2的第二部分60B(見圖5)。另外，再分配線60可以被形成為包括第一部分60A與第二部分60B之間的第三部分60C。在這種情況下， 參照圖5，如果寬度X1大於寬度X2，則再分配線60的第三部分60C可以從第一部分60A開始朝向第二部分60B逐漸減小。再分配線60的不均勻的寬度會導致再分配線60的電特性和可靠性的劣化。 Referring to FIG. 4, the non-planarization of the insulating layer 50 may be exemplified on the boundary surface between the EMC layer 40 and the sidewall of the die 20. This is because while forming the EMC layer 40, the temporary adhesive (30 in FIG. 2) in contact with the die 20 is pressed down more than the temporary adhesive (30 in FIG. 2) in contact with the EMC layer 40. Therefore, a height difference can be provided between the die 20 and the EMC layer 40. That is, the height difference D1 may exist between the surface 23 of the crystal grain 20 and the surface 41 of the EMC layer 40. The insulating layer 50 covering the die 20 and the EMC layer 40 may be formed to have an uneven surface due to the height difference D1 between the die 20 and the EMC layer 40, and the redistribution layer formed on the insulating layer 50 may also be Has an uneven surface that exhibits a height difference D2. The redistribution line 60 may be formed by patterning a redistribution layer having a height difference D2. Therefore, the height difference D2 may affect the photolithography process for patterning the redistribution layer to form the redistribution line 60, and each of the redistribution lines 60 may be formed to have an uneven width. For example, if the redistribution layer is patterned using a photolithography process and an etching process, it may be difficult to adjust and optimize during the photolithography process due to the uneven thickness of the photoresist layer coated on the redistribution layer The depth of focus. Therefore, the redistribution line 60 may be formed to include a first portion 60A overlapping the die 20 and having a width X1 and a second portion 60B overlapping the EMC layer 40 and having a width X2 different from the width X1 (see FIG. 5 ). In addition, the redistribution line 60 may be formed to include a third portion 60C between the first portion 60A and the second portion 60B. under these circumstances, Referring to FIG. 5, if the width X1 is greater than the width X2, the third portion 60C of the redistribution line 60 may gradually decrease from the first portion 60A toward the second portion 60B. The non-uniform width of the redistribution line 60 causes deterioration of the electrical characteristics and reliability of the redistribution line 60.

圖6是例示了在製造晶圓級封裝中根據再分配線60的圖案密度的圖案失真的示例的表示的截面圖。 6 is a cross-sectional view illustrating a representation of an example of pattern distortion according to the pattern density of the redistribution line 60 in manufacturing a wafer-level package.

參照圖6，再分配線60可以形成在覆蓋晶粒20的第一絕緣層50上，並且第二絕緣層70可以形成在第一絕緣層50上以覆蓋再分配線60。第二絕緣層70的表面可以具有在設置有再分配線60的區域61與沒有設置再分配線60的區域63之間的高度差D3。高度差D3可以與區域61中的第二絕緣層70的頂表面的表面高度L1和區域63中的第二絕緣層70的頂表面的表面高度L2之間的差對應。如果第二絕緣層70具有呈現高度差D3的頂表面，則形成在第二絕緣層70上的光阻圖案80的開口部81和81E中的一些可以具有圖案失真。如果使用區域61作為目的地區域來確定用於形成光阻圖案80的光微影製程的曝光條件，則光阻圖案80的位於區域61中的開口部81可以被正常地形成為全開，而光阻圖案80的位於區域63中的開口部81E被異常地形成為沒有全開。這種圖案失真可能是由於第二絕緣層70的頂表面的高度差D3而導致的。 Referring to FIG. 6, the redistribution line 60 may be formed on the first insulating layer 50 covering the die 20, and the second insulating layer 70 may be formed on the first insulating layer 50 to cover the redistribution line 60. The surface of the second insulating layer 70 may have a height difference D3 between the area 61 where the redistribution line 60 is provided and the area 63 where the redistribution line 60 is not provided. The height difference D3 may correspond to the difference between the surface height L1 of the top surface of the second insulating layer 70 in the region 61 and the surface height L2 of the top surface of the second insulating layer 70 in the region 63. If the second insulating layer 70 has a top surface exhibiting a height difference D3, some of the openings 81 and 81E of the photoresist pattern 80 formed on the second insulating layer 70 may have pattern distortion. If the area 61 is used as the destination area to determine the exposure conditions for the photolithography process for forming the photoresist pattern 80, the opening 81 of the photoresist pattern 80 in the area 61 may be normally formed to be fully open, while the photoresist The opening 81E of the pattern 80 located in the area 63 is abnormally formed so as not to be fully opened. This pattern distortion may be caused by the height difference D3 of the top surface of the second insulating layer 70.

根據本公開，保護基板(或者保護晶圓)可以被用作支承晶圓以支承半導體晶粒(或者半導體晶片)，半導體晶粒可以使用具有永久黏合強度的黏合劑附接到保護基板。因此，在半導體晶粒附接到保護基板之後，可以將半導體晶粒牢固地固定到保護基板以防止半導體晶粒在後續製程期間移位。半導體晶粒可以使用層壓製程而覆蓋有感光介電膜，該感光 介電膜可以被平坦化以提供感光介電膜的平坦的頂表面。隨後，可以在感光介電膜的平坦的頂表面上形成再分配線。因此，在形成再分配線之前，能夠防止下面的介電層具有不平坦的地形。用作保護基板的矽基板可以用作封裝主體的一部分。因此，可以緩解由於封裝主體與保護基板之間的CTE差而導致的未對準問題，以抑制晶圓級封裝件的翹曲。因此，本公開可以提供包括具有精細節距的互連線在內的高性能半導體封裝件。 According to the present disclosure, a protective substrate (or a protective wafer) may be used as a support wafer to support semiconductor dies (or semiconductor wafers), and the semiconductor dies may be attached to the protective substrate using an adhesive having permanent bonding strength. Therefore, after the semiconductor die is attached to the protective substrate, the semiconductor die can be firmly fixed to the protective substrate to prevent the semiconductor die from shifting during the subsequent manufacturing process. The semiconductor die can be covered with a photosensitive dielectric film using a lamination process. The dielectric film may be planarized to provide a flat top surface of the photosensitive dielectric film. Subsequently, redistribution lines may be formed on the flat top surface of the photosensitive dielectric film. Therefore, before the redistribution line is formed, the underlying dielectric layer can be prevented from having uneven topography. The silicon substrate used as the protective substrate can be used as a part of the package body. Therefore, the misalignment problem due to the CTE difference between the package body and the protective substrate can be alleviated to suppress the warpage of the wafer-level package. Therefore, the present disclosure can provide a high-performance semiconductor package including interconnects with fine pitch.

圖7至圖19例示了根據實施方式的製造晶圓級封裝件的方法的示例的表示。圖7是保護晶圓1100W的平面圖，並且圖8至圖19中的每一個包括保護晶圓1100W的一部分的截面圖。 7 to 19 illustrate a representation of an example of a method of manufacturing a wafer-level package according to an embodiment. 7 is a plan view of the protection wafer 1100W, and each of FIGS. 8 to 19 includes a cross-sectional view of a portion of the protection wafer 1100W.

參照圖7，可以提供保護晶圓1100W以使用晶圓級封裝件的製造技術來製造扇出半導體封裝件。保護晶圓1100W可以是例如矽晶圓的半導體晶圓或者半導體基板。在一些實施方式中，保護晶圓1100W可以是由與矽材料不同的材料組成的晶圓。在一些其它實施方式中，保護晶圓1100W可以由CTE與附接到保護晶圓1100W的半導體晶粒(圖8的1200)的主體的CTE基本上相等的材料組成。在這種情況下，可以抑制由於半導體晶粒與保護基板之間的CTE差而導致的一些故障(例如，翹曲)。例如，如果半導體晶粒(圖8的1200)中的每一個具有矽主體，則保護晶圓1100W可以由矽材料組成。 Referring to FIG. 7, a protection wafer 1100W may be provided to manufacture a fan-out semiconductor package using wafer-level package manufacturing technology. The protection wafer 1100W may be a semiconductor wafer such as a silicon wafer or a semiconductor substrate. In some embodiments, the protection wafer 1100W may be a wafer composed of a material different from silicon material. In some other embodiments, the protective wafer 1100W may be composed of a material having a CTE that is substantially equal to a CTE attached to the body of the semiconductor die (1200 of FIG. 8) of the protective wafer 1100W. In this case, some failures (eg, warpage) due to the difference in CTE between the semiconductor die and the protective substrate can be suppressed. For example, if each of the semiconductor dies (1200 of FIG. 8) has a silicon body, the protection wafer 1100W may be composed of silicon material.

保護晶圓1100W可以是厚度為半導體晶粒(圖8的1200)的厚度的約十倍至約三十倍的矽晶圓。例如，如果半導體晶粒(圖8的1200)具有約30微米至約50微米的厚度，則保護晶圓1100W可以具有約750微米至約770微米的厚度。由於保護晶圓1100W比半導體晶粒(圖8的1200) 厚得多，因此保護晶圓1100W與封裝件的體積比可以大於半導體晶粒(圖8的1200)與封裝件的體積比。這可以抑制由於半導體晶粒(圖8的1200)與其它元件之間的CTE差而導致的影響。因此，可以抑制封裝件的翹曲。 The protection wafer 1100W may be a silicon wafer having a thickness of about ten times to about thirty times the thickness of the semiconductor die (1200 of FIG. 8 ). For example, if the semiconductor die (1200 of FIG. 8) has a thickness of about 30 microns to about 50 microns, the protective wafer 1100W may have a thickness of about 750 microns to about 770 microns. Because the protection wafer is 1100W higher than the semiconductor die (1200 in Figure 8) It is much thicker, so the volume ratio of the protection wafer 1100W to the package can be greater than the volume ratio of the semiconductor die (1200 of FIG. 8) to the package. This can suppress the influence due to the CTE difference between the semiconductor die (1200 of FIG. 8) and other elements. Therefore, the warpage of the package can be suppressed.

保護晶圓1100W可以具有彼此相對的第一表面1101和第二表面1103，並且第一表面1101與第二表面1103之間的距離可以與保護晶圓1100W的厚度對應。對準標記1110可以形成在保護晶圓1100W的第一表面1101處。當在後續製程中重新構成半導體晶粒(圖8的1200)時，對準標記1110可以被用作用於指派半導體晶粒(圖8的1200)的位置的參考標記。對準標記1110可以形成在保護晶圓1100W的單位區域1100U中的每一個的邊界區域1106中。保護晶圓1100W可以包括多個單位區域1100U。每個單位區域1100U可以被指派給單個封裝件。單位區域1100U可以被排列成具有矩陣形式。每個單位區域1100U可以包括安裝有半導體晶粒1200的晶片安裝區域1105和包圍晶片安裝區域1105以用作劃道(scribe lane)的邊界區域1106。保護晶圓1100W可以包括以二維方式排列的多個單位區域1100U。對準標記1110可以被設置在彼此相鄰的晶片安裝區域1105之間的邊界區域1106中。另選地，對準標記1110可以被設置在晶片安裝區域1105中以與邊界區域1106相鄰。對準標記1110可以被形成為具有比保護晶圓1100W的第一表面1101低或者高的表面。例如，對準標記1110可以通過對保護晶圓1100W的第一表面1101的一部分進行選擇性蝕刻而被形成為具有凹槽形狀或者凹面形狀。因此，可以在後續製程中使用對準標記1110來實現精確的對準。也就是說，保護晶圓1100W的第一表面1101與對準標記1110的底表面之間的高度差可以產生具有高解析度的圖像，並且可以使用具有高解 析度的對準標記圖像來精確地設置或者識別保護晶圓1100W的特定位置。對準標記1110可以位於每個單位區域1100U中以提供參考位置。因此，半導體晶粒(圖8的1200)可以在後續製程中使用對準標記1110來與保護晶圓1100W精確地對準。 The protection wafer 1100W may have a first surface 1101 and a second surface 1103 opposite to each other, and the distance between the first surface 1101 and the second surface 1103 may correspond to the thickness of the protection wafer 1100W. The alignment mark 1110 may be formed at the first surface 1101 of the protection wafer 1100W. When the semiconductor die (1200 of FIG. 8) is reconstructed in a subsequent process, the alignment mark 1110 may be used as a reference mark for assigning the position of the semiconductor die (1200 of FIG. 8). The alignment mark 1110 may be formed in the boundary area 1106 of each of the unit areas 1100U protecting the wafer 1100W. The protection wafer 1100W may include a plurality of unit areas 1100U. Each unit area 1100U may be assigned to a single package. The unit area 1100U may be arranged to have a matrix form. Each unit area 1100U may include a wafer mounting area 1105 on which the semiconductor die 1200 is mounted and a boundary area 1106 surrounding the wafer mounting area 1105 to serve as a scribe lane. The protection wafer 1100W may include a plurality of unit regions 1100U arranged in a two-dimensional manner. The alignment mark 1110 may be provided in the boundary area 1106 between the wafer mounting areas 1105 adjacent to each other. Alternatively, the alignment mark 1110 may be provided in the wafer mounting area 1105 to be adjacent to the boundary area 1106. The alignment mark 1110 may be formed to have a lower or higher surface than the first surface 1101 of the protection wafer 1100W. For example, the alignment mark 1110 may be formed to have a groove shape or a concave shape by selectively etching a part of the first surface 1101 of the protection wafer 1100W. Therefore, alignment marks 1110 can be used in subsequent processes to achieve accurate alignment. That is, the difference in height between the first surface 1101 of the protection wafer 1100W and the bottom surface of the alignment mark 1110 can produce an image with high resolution, and a high resolution can be used Resolution of the alignment mark image to accurately set or identify the specific position of the protection wafer 1100W. The alignment mark 1110 may be located in each unit area 1100U to provide a reference position. Therefore, the semiconductor die (1200 of FIG. 8) can be accurately aligned with the protection wafer 1100W using the alignment mark 1110 in the subsequent process.

參照圖8，半導體晶粒1200可以被設置在保護晶圓1100W的第一表面1101上以使用對準標記1110分別與晶片安裝區域1105對準，並且半導體晶粒1200可以被分別安裝在晶片安裝區域1105上。每個半導體晶粒1200具有面對保護晶圓1100W的第一表面1101的第三表面1206，並且可以在半導體晶粒1200的第三表面1206上設置黏合層1300。例如連接焊墊的內部連接件1201可以被設置在半導體晶粒1200的與保護晶圓1100W相反的第四表面1207上。因此，半導體晶粒1200可以被安裝在保護晶圓1100W上，以使得連接焊墊1201被設置在半導體晶粒1200的與保護晶圓1100W相反的表面上。半導體晶粒1200可以被分別設置在通過邊界區域1106彼此分隔開的晶片安裝區域1105上。因此，半導體晶粒1200可以並排地排列在保護晶圓1100W上。 Referring to FIG. 8, the semiconductor die 1200 may be disposed on the first surface 1101 of the protection wafer 1100W to be respectively aligned with the wafer mounting area 1105 using the alignment marks 1110, and the semiconductor die 1200 may be respectively mounted on the wafer mounting area 1105. Each semiconductor die 1200 has a third surface 1206 facing the first surface 1101 of the protection wafer 1100W, and an adhesive layer 1300 may be provided on the third surface 1206 of the semiconductor die 1200. For example, an internal connector 1201 connecting pads may be provided on the fourth surface 1207 of the semiconductor die 1200 opposite to the protection wafer 1100W. Therefore, the semiconductor die 1200 may be mounted on the protection wafer 1100W so that the connection pad 1201 is provided on the surface of the semiconductor die 1200 opposite to the protection wafer 1100W. The semiconductor dies 1200 may be respectively disposed on the wafer mounting regions 1105 separated from each other by the boundary region 1106. Therefore, the semiconductor dies 1200 may be arranged side by side on the protection wafer 1100W.

黏合層1300可以提供保護晶圓1100W與半導體晶粒1200之間的永久接合，以將半導體晶粒1200固定到保護晶圓1100W。與用於在用於製造晶圓級封裝件的一般技術中將臨時載體(或者處理支承件)臨時附接到半導體晶粒的臨時黏合層不同，黏合層1300可以提供保護晶圓1100W與半導體晶粒1200之間的不可逆的接合。如果UV射線照射到臨時黏合層上，則臨時黏合層會失去其黏合強度。因此，可以使用UV射線來將臨時載體(或者處理支承件)與半導體晶粒分離。在實施方式中，黏合層 1300可以在半導體晶粒1200被安裝在保護晶圓1100W上之後固化。在這種情況下，即使UV射線照射到經固化的黏合層1300上，經固化的黏合層1300也不會失去其黏合強度。因此，即使在半導體晶粒1200被安裝在保護晶圓1100W上並且與其接合之後，也能夠利用加熱或者UV射線來附加地執行固化處理。黏合層1300可以包含硬化性黏合劑成分，並且半導體晶粒1200可以通過硬化性黏合劑成分的化學反應不可逆地固定到保護晶圓1100W。黏合層1300可以包含用作硬化性黏合劑成分的環氧樹脂成分，並且黏合層1300可以在固化處理期間通過環氧樹脂反應來硬化，以提供保護晶圓1100W與半導體晶粒1200之間的永久且不可逆的接合。由於黏合層1300將半導體晶粒1200牢固地接合並固定到保護晶圓1100W，因此黏合層1300可以在後續製程期間抑制半導體晶粒1200的位置移位。在本公開中，保護晶圓1100W不與半導體晶粒1200分離，並且保護晶圓1100W的一部分可以構成每個封裝件的一部分。因此，可以使用能夠將半導體晶粒1200永久地固定到保護晶圓1100W的不可逆黏合材料作為黏合層1300。 The adhesive layer 1300 may provide a permanent bond between the protection wafer 1100W and the semiconductor die 1200 to fix the semiconductor die 1200 to the protection wafer 1100W. Unlike the temporary adhesive layer used to temporarily attach a temporary carrier (or processing support) to a semiconductor die in a general technique for manufacturing wafer-level packages, the adhesive layer 1300 can provide protection to the wafer 1100W and semiconductor crystal Irreversible bonding between the particles 1200. If UV rays are irradiated on the temporary adhesive layer, the temporary adhesive layer will lose its adhesive strength. Therefore, UV rays can be used to separate the temporary carrier (or processing support) from the semiconductor die. In an embodiment, the adhesive layer 1300 may be cured after the semiconductor die 1200 is mounted on the protection wafer 1100W. In this case, even if UV rays are irradiated onto the cured adhesive layer 1300, the cured adhesive layer 1300 will not lose its adhesive strength. Therefore, even after the semiconductor die 1200 is mounted on and bonded to the protective wafer 1100W, the curing process can be additionally performed using heat or UV rays. The adhesive layer 1300 may contain a hardening adhesive component, and the semiconductor die 1200 may be irreversibly fixed to the protection wafer 1100W through a chemical reaction of the hardening adhesive component. The adhesive layer 1300 may contain an epoxy resin component used as a hardening adhesive component, and the adhesive layer 1300 may be hardened by an epoxy resin reaction during the curing process to provide permanent protection between the wafer 1100W and the semiconductor die 1200 And irreversible joint. Since the adhesive layer 1300 firmly bonds and fixes the semiconductor die 1200 to the protection wafer 1100W, the adhesive layer 1300 can suppress the positional displacement of the semiconductor die 1200 during the subsequent manufacturing process. In the present disclosure, the protection wafer 1100W is not separated from the semiconductor die 1200, and a part of the protection wafer 1100W may constitute a part of each package. Therefore, as the adhesive layer 1300, an irreversible adhesive material capable of permanently fixing the semiconductor die 1200 to the protection wafer 1100W may be used.

在一些實施方式中，黏合層1300可以包含熱介面材料成分或者導熱成分，以提供輻射或者散發由半導體晶粒1200的操作產生的熱的路徑。如果黏合層1300中包含諸如金屬顆粒這樣的導熱成分或者熱介面材料成分，則半導體晶粒1200中產生的熱可以被更容易地散發到保護晶圓1100W中。保護晶圓1100W的熱導率可以高於在後續製程中被形成為包圍半導體晶粒1200的感光材料層的熱導率。因此，如果黏合層1300包含熱介面材料成分或者導熱成分，則可以更有效地散發半導體晶粒1200中產生的熱。 In some embodiments, the adhesive layer 1300 may include a thermal interface material component or a thermally conductive component to provide a path for radiating or dissipating heat generated by the operation of the semiconductor die 1200. If the adhesive layer 1300 contains thermally conductive components such as metal particles or thermal interface material components, the heat generated in the semiconductor die 1200 can be more easily dissipated into the protection wafer 1100W. The thermal conductivity of the protection wafer 1100W may be higher than the thermal conductivity of the photosensitive material layer formed to surround the semiconductor die 1200 in the subsequent process. Therefore, if the adhesive layer 1300 contains a thermal interface material component or a thermally conductive component, the heat generated in the semiconductor die 1200 can be more efficiently dissipated.

參照圖9，第一感光介電膜1410F可以被設置在半導體晶粒1200上。參照圖10，第一感光介電膜1410F可以附接到保護晶圓1100W以形成第一感光介電層1410A。因此，半導體晶粒1200可以被掩埋在第一感光介電層1410A中。第一感光介電膜(圖9中的1410F)可以包括諸如感光聚醯亞胺膜或者感光聚苯並惡唑膜這樣的感光聚合物膜。在一些實施方式中，包含環氧樹脂成分的感光膜可以被用作第一感光介電膜1410F。由於第一感光介電膜1410F或者第一感光介電層1410A包含光敏劑，因此第一感光介電層1410A的暴露於光(諸如UV射線)的一部分可以具有與第一感光介電層1410A的沒有暴露於光(諸如UV射線)的另一部分的溶解度不同的溶解度。 Referring to FIG. 9, the first photosensitive dielectric film 1410F may be provided on the semiconductor die 1200. Referring to FIG. 10, the first photosensitive dielectric film 1410F may be attached to the protection wafer 1100W to form the first photosensitive dielectric layer 1410A. Therefore, the semiconductor die 1200 may be buried in the first photosensitive dielectric layer 1410A. The first photosensitive dielectric film (1410F in FIG. 9) may include a photosensitive polymer film such as a photosensitive polyimide film or a photosensitive polybenzoxazole film. In some embodiments, a photosensitive film containing an epoxy resin component may be used as the first photosensitive dielectric film 1410F. Since the first photosensitive dielectric film 1410F or the first photosensitive dielectric layer 1410A contains a photosensitizer, a portion of the first photosensitive dielectric layer 1410A exposed to light (such as UV rays) may have a difference from the first photosensitive dielectric layer 1410A The solubility of another part that is not exposed to light (such as UV rays) differs in solubility.

附接到保護晶圓1100W的第一感光介電層1410A可以具有不平坦表面1410U。由於具有平坦表面的第一感光介電膜1410F被層壓到保護晶圓1100W和半導體晶粒1200上以提供第一感光介電層1410A，因此第一感光介電層1410A的不平坦表面1410U可以是由於對準標記1110和半導體晶粒1200的表面形態而導致的。也就是說，第一感光介電層1410A與每個半導體晶粒1200交疊的第一部分1410H可以具有比第一感光介電層1410A的設置在半導體晶粒1200之間的第二部分1410L的頂表面高的頂表面。 The first photosensitive dielectric layer 1410A attached to the protection wafer 1100W may have an uneven surface 1410U. Since the first photosensitive dielectric film 1410F having a flat surface is laminated onto the protection wafer 1100W and the semiconductor die 1200 to provide the first photosensitive dielectric layer 1410A, the uneven surface 1410U of the first photosensitive dielectric layer 1410A may This is due to the surface morphology of the alignment mark 1110 and the semiconductor die 1200. That is, the first portion 1410H of the first photosensitive dielectric layer 1410A overlapping each semiconductor die 1200 may have a top of the second portion 1410L of the first photosensitive dielectric layer 1410A disposed between the semiconductor die 1200 High surface top surface.

參照圖11，可以對第一感光介電層1410A應用平整步驟。例如，具有平坦表面1490P的平坦化構件1490可以位於第一感光介電層1410A上，並且平坦化構件1490可以在加熱的情況下被向下按壓以將第一感光介電層1410A的不平坦表面1410U改變為通過平坦化構件1490的平坦 表面1490P平整的平坦表面1410P。結果，可以提供具有平坦表面1410P的第一感光介電層1410。平坦化構件1490可以是具有平坦表面1490P的模具框架。平坦化構件1490可以是壓輥(press roller)。即使第一感光介電層1410A由於半導體晶粒1200的存在而具有不平坦表面1410U，第一感光介電層1410A也可以通過平整步驟被改變為具有平坦表面1410P的第一感光介電層1410。因此，能夠在第一感光介電層1410的平坦表面1410P上形成具有精細節距的互連線。 Referring to FIG. 11, a smoothing step may be applied to the first photosensitive dielectric layer 1410A. For example, a planarizing member 1490 having a flat surface 1490P may be located on the first photosensitive dielectric layer 1410A, and the planarizing member 1490 may be pressed down under heating to press the uneven surface of the first photosensitive dielectric layer 1410A 1410U changed to flat by the flattening member 1490 The surface 1490P is a flat surface 1410P flat. As a result, the first photosensitive dielectric layer 1410 having the flat surface 1410P can be provided. The planarizing member 1490 may be a mold frame having a flat surface 1490P. The planarizing member 1490 may be a press roller. Even though the first photosensitive dielectric layer 1410A has an uneven surface 1410U due to the presence of the semiconductor die 1200, the first photosensitive dielectric layer 1410A can be changed to the first photosensitive dielectric layer 1410 having a flat surface 1410P through the planarization step. Therefore, it is possible to form interconnect lines having a fine pitch on the flat surface 1410P of the first photosensitive dielectric layer 1410.

參照圖12，可以在第一感光介電層1410中形成第一開口部1411，以使半導體晶粒1200的一部分(例如，內部連接件1201)暴露。第一開口部1411可以被形成為貫穿第一感光介電層1410。第一開口部1411可以通過選擇性地使第一感光介電層1410的一部分暴露於諸如UV射線的光並且通過對所暴露的第一感光介電層1410進行顯影而形成。在這種情況下，由於第一感光介電層1410具有平坦表面1410P，因此可以在沒有由於散焦曝光等而導致的任何圖案失真的情況下均勻且精確地形成第一開口部1411。 Referring to FIG. 12, a first opening 1411 may be formed in the first photosensitive dielectric layer 1410 to expose a portion of the semiconductor die 1200 (for example, the internal connector 1201 ). The first opening 1411 may be formed to penetrate the first photosensitive dielectric layer 1410. The first opening portion 1411 may be formed by selectively exposing a portion of the first photosensitive dielectric layer 1410 to light such as UV rays and by developing the exposed first photosensitive dielectric layer 1410. In this case, since the first photosensitive dielectric layer 1410 has a flat surface 1410P, the first opening portion 1411 can be uniformly and accurately formed without any pattern distortion due to defocus exposure or the like.

參照圖13，可以在具有第一開口部1411的第一感光介電層1410上形成光阻圖案1700。光阻圖案1700可以被用作遮罩，例如，用於形成再分配線的電鍍遮罩。光阻圖案1700可以通過將光阻材料塗覆在第一感光介電層1410上並且使用曝光製程和顯影製程對光阻材料進行圖案化來形成。光阻圖案1700可以被形成為使第一開口部1411暴露並且使第一感光介電層1410的與第一開口部1411相鄰的平坦表面1410P的一部分暴露。由於第一感光介電層1410具有平坦表面1410P，因此光阻圖案1700可以在沒有 由於下面的層的不平坦表面而導致的一些製程問題的情況下被形成為具有精確的尺寸。光阻圖案1700可以被形成為限定設置有再分配線的區域。 Referring to FIG. 13, a photoresist pattern 1700 may be formed on the first photosensitive dielectric layer 1410 having the first opening 1411. The photoresist pattern 1700 may be used as a mask, for example, an electroplating mask for forming a redistribution line. The photoresist pattern 1700 may be formed by coating a photoresist material on the first photosensitive dielectric layer 1410 and patterning the photoresist material using an exposure process and a development process. The photoresist pattern 1700 may be formed to expose the first opening 1411 and expose a portion of the flat surface 1410P of the first photosensitive dielectric layer 1410 adjacent to the first opening 1411. Since the first photosensitive dielectric layer 1410 has a flat surface 1410P, the photoresist pattern 1700 can have no Some process problems due to the uneven surface of the underlying layer are formed to have precise dimensions. The photoresist pattern 1700 may be formed to define an area where redistribution lines are provided.

參照圖14，可以在第一感光介電層1410的通過光阻圖案(圖13中的1700)暴露的平坦表面1410P上以及通過光阻圖案1700暴露的第一開口部1411中形成再分配線1500。然後可以去除光阻圖案1700。光阻圖案1700可以用作限定再分配線1500的形狀的圖案化遮罩。再分配線1500可以通過將包含銅的電鍍層沉積在通過光阻圖案1700暴露的第一感光介電層1410上而形成，並且可以去除光阻圖案1700。另選地，再分配線1500可以通過將包含銅的電鍍層沉積在第一感光介電層1410和光阻圖案1700二者上並且將光阻圖案1700剝離而形成。 Referring to FIG. 14, a redistribution line 1500 may be formed on the flat surface 1410P of the first photosensitive dielectric layer 1410 exposed through the photoresist pattern (1700 in FIG. 13) and the first opening portion 1411 exposed through the photoresist pattern 1700 . The photoresist pattern 1700 can then be removed. The photoresist pattern 1700 can be used as a patterned mask that defines the shape of the redistribution line 1500. The redistribution line 1500 may be formed by depositing a plating layer containing copper on the first photosensitive dielectric layer 1410 exposed through the photoresist pattern 1700, and the photoresist pattern 1700 may be removed. Alternatively, the redistribution line 1500 may be formed by depositing a plating layer containing copper on both the first photosensitive dielectric layer 1410 and the photoresist pattern 1700 and peeling off the photoresist pattern 1700.

每個再分配線1500可以被形成為包括位於第一感光介電層1410的平坦表面1410P上以用作互連線的跡線圖案1550以及位於第一開口部1411中的一個中以將跡線圖案1550電連接到內部連接件1201中的一個的通孔1530。通孔1530可以被形成為垂直地貫穿覆蓋半導體晶粒1200的第四表面1207的第一感光介電層1410，並且與內部連接件1201接觸。通孔1530可以被形成為填充第一開口部1411中的一個。跡線圖案1550可以延伸以與設置在半導體晶粒1200之間的第一感光介電層1410的一部分交疊。 Each redistribution line 1500 may be formed to include a trace pattern 1550 on the flat surface 1410P of the first photosensitive dielectric layer 1410 to serve as an interconnect line and one of the first opening portions 1411 to divide the trace The pattern 1550 is electrically connected to the through hole 1530 of one of the internal connectors 1201. The through hole 1530 may be formed to vertically penetrate the first photosensitive dielectric layer 1410 covering the fourth surface 1207 of the semiconductor die 1200 and make contact with the internal connector 1201. The through hole 1530 may be formed to fill one of the first opening parts 1411. The trace pattern 1550 may extend to overlap a portion of the first photosensitive dielectric layer 1410 disposed between the semiconductor dies 1200.

由於第一感光介電層1410具有平坦表面1410P，因此光阻圖案(圖13中的1700)可以被形成為在沒有圖案失真的情況下具有精細的節距。因此，其形狀由光阻圖案(圖13中的1700)限定的再分配線1500也可以被形成為在沒有圖案失真的情況下具有精細的節距。因此，能夠增加有限區域中所形成的再分配線1500的數目。 Since the first photosensitive dielectric layer 1410 has a flat surface 1410P, a photoresist pattern (1700 in FIG. 13) can be formed to have a fine pitch without pattern distortion. Therefore, the redistribution line 1500 whose shape is defined by the photoresist pattern (1700 in FIG. 13) may also be formed to have a fine pitch without pattern distortion. Therefore, the number of redistribution lines 1500 formed in the limited area can be increased.

參照圖15，第二感光介電層1450可以形成在第一感光介電層1410的平坦表面1410P上以覆蓋再分配線1500。可以使用與在形成第一感光介電層1410時使用的相同的技術來形成第二感光介電層1450。也就是說，第二感光介電層1450可以通過將第二感光介電膜(未例示)設置在第一感光介電層1410和再分配線1500上並且使用層壓製程將第二感光介電膜附接到第一感光介電層1410而形成。在這種情況下，第二感光介電膜可以因為再分配線1500的存在而具有不平坦的頂表面。因此，可以利用與在使第一感光介電層1410A平坦化時使用的相同的平整步驟來使附接到第一感光介電層1410的第二感光介電膜平坦化。結果，如圖15所例示，第二感光介電層1450可以被形成為具有平坦表面1450P。由於第二感光介電層1450具有平坦表面1450P，因此可以在第二感光介電層1450上更容易地形成精細的圖案。在一些實施方式中，第二感光介電層1450可以由基本上與第一感光介電層1410相同的材料形成。 Referring to FIG. 15, the second photosensitive dielectric layer 1450 may be formed on the flat surface 1410P of the first photosensitive dielectric layer 1410 to cover the redistribution line 1500. The second photosensitive dielectric layer 1450 may be formed using the same technique used when forming the first photosensitive dielectric layer 1410. That is, the second photosensitive dielectric layer 1450 can be formed by disposing a second photosensitive dielectric film (not illustrated) on the first photosensitive dielectric layer 1410 and the redistribution line 1500 and using a lamination process to A film is formed by being attached to the first photosensitive dielectric layer 1410. In this case, the second photosensitive dielectric film may have an uneven top surface due to the presence of the redistribution line 1500. Therefore, it is possible to planarize the second photosensitive dielectric film attached to the first photosensitive dielectric layer 1410 using the same flattening step as that used when planarizing the first photosensitive dielectric layer 1410A. As a result, as illustrated in FIG. 15, the second photosensitive dielectric layer 1450 may be formed to have a flat surface 1450P. Since the second photosensitive dielectric layer 1450 has a flat surface 1450P, a fine pattern can be more easily formed on the second photosensitive dielectric layer 1450. In some embodiments, the second photosensitive dielectric layer 1450 may be formed of substantially the same material as the first photosensitive dielectric layer 1410.

如果必須形成具有多層結構的再分配線，則可以重複地執行形成再分配線1500的步驟和形成第二感光介電層1450的步驟。即使再分配線被形成為具有多層結構，每個感光介電層也可以被形成為具有平坦的頂表面。因此，具有多層結構的所有再分配線可以被形成為具有精細的節距。 If it is necessary to form a redistribution line having a multilayer structure, the steps of forming the redistribution line 1500 and the step of forming the second photosensitive dielectric layer 1450 may be repeatedly performed. Even if the redistribution line is formed to have a multilayer structure, each photosensitive dielectric layer may be formed to have a flat top surface. Therefore, all redistribution lines having a multilayer structure can be formed to have a fine pitch.

參照圖16，可以對第二感光介電層1450圖案化，以形成貫穿第二感光介電層1450的一部分的第二開口部1451。第二開口部1451可以通過選擇性地使第二感光介電層1450的一部分暴露於諸如UV射線的光並且對所暴露的第二感光介電層1450進行顯影而形成。在這種情況下，由於第二感光介電層1450具有平坦表面1450P，因此可以在沒有由於散焦曝光 等而導致的圖案失真的情況下均勻且精確地形成第二開口部1451。 Referring to FIG. 16, the second photosensitive dielectric layer 1450 may be patterned to form a second opening 1451 penetrating a portion of the second photosensitive dielectric layer 1450. The second opening portion 1451 may be formed by selectively exposing a portion of the second photosensitive dielectric layer 1450 to light such as UV rays and developing the exposed second photosensitive dielectric layer 1450. In this case, since the second photosensitive dielectric layer 1450 has a flat surface 1450P, it can be exposed without defocusing The second opening 1451 is formed uniformly and accurately in the case of pattern distortion caused by the like.

每個第二開口部1451可以被形成為使再分配線1500中的任意一條的一部分暴露。例如，每個第二開口部1451可以被形成為使再分配線1500中的任意一條的跡線圖案1550的一部分暴露。第二開口部1451中的一些可以被形成為不與半導體晶粒1200交疊。參照圖17，外部連接件1600可以分別附接到通過第二開口部1451暴露的跡線圖案1550。因此，外部連接件1600可以電連接到跡線圖案1550。外部連接件1600可以具有焊球的形狀。另選地，外部連接件1600可以具有凸塊的形狀。外部連接件1600中的一些可以被定位為不與半導體晶粒1200交疊。跡線圖案1550可以延伸到晶片安裝區域1105之間的邊界區域1106上，以實現扇出半導體封裝件。 Each second opening portion 1451 may be formed to expose a part of any one of the redistribution lines 1500. For example, each second opening portion 1451 may be formed to expose a part of the trace pattern 1550 of any one of the redistribution lines 1500. Some of the second openings 1451 may be formed not to overlap the semiconductor die 1200. Referring to FIG. 17, the external connectors 1600 may be respectively attached to the trace patterns 1550 exposed through the second opening part 1451. Therefore, the external connector 1600 may be electrically connected to the trace pattern 1550. The external connection 1600 may have the shape of a solder ball. Alternatively, the external connector 1600 may have a bump shape. Some of the external connectors 1600 may be positioned so as not to overlap the semiconductor die 1200. The trace pattern 1550 may extend onto the boundary area 1106 between the wafer mounting areas 1105 to realize the fan-out semiconductor package.

參照圖18，可以執行減薄步驟以減小保護晶圓1100W的厚度。也就是說，可以使保護晶圓1100W的第二表面1103凹進以提供凹進的第二表面1103B。可以通過對保護晶圓1100W的第二表面1103應用研磨製程來執行減薄步驟。另選地，可以通過對保護晶圓1100W的第二表面1103應用化學機械拋光(CMP)製程或者回蝕(etch-back)製程來執行減薄步驟。 Referring to FIG. 18, a thinning step may be performed to reduce the thickness of the protective wafer 1100W. That is, the second surface 1103 of the protection wafer 1100W may be recessed to provide the recessed second surface 1103B. The thinning step may be performed by applying a grinding process to the second surface 1103 of the protection wafer 1100W. Alternatively, the thinning step may be performed by applying a chemical mechanical polishing (CMP) process or an etch-back process to the second surface 1103 of the protection wafer 1100W.

初始保護晶圓1100W可以是具有約750微米至約770微米的厚度的矽晶圓。在執行減薄步驟之後，保護晶圓1100W可以具有約150微米至約400微米的厚度。儘管半導體晶粒1200具有約30微米至約50微米的厚度，然而經減薄的保護晶圓1100W仍然可以比半導體晶粒1200厚。考慮到保護半導體晶粒1200所需要的最小厚度，經減薄的保護晶圓1100W可以具有至少150微米的厚度。由於經減薄的保護晶圓1100W的厚度是半導體晶粒1200的厚度的約3倍至約15倍，因此經減薄的保護晶圓1100W 與封裝件的體積比可以大於半導體晶粒1200與封裝件的體積比。這可以抑制由於半導體晶粒1200與感光介電層1410和1450之間的CTE差而造成的影響。因此，可以抑制封裝件的翹曲。 The initial protection wafer 1100W may be a silicon wafer having a thickness of about 750 microns to about 770 microns. After performing the thinning step, the protective wafer 1100W may have a thickness of about 150 microns to about 400 microns. Although the semiconductor die 1200 has a thickness of about 30 microns to about 50 microns, the thinned protective wafer 1100W may still be thicker than the semiconductor die 1200. Considering the minimum thickness required to protect the semiconductor die 1200, the thinned protective wafer 1100W may have a thickness of at least 150 microns. Since the thickness of the thinned protective wafer 1100W is about 3 to about 15 times the thickness of the semiconductor die 1200, the thinned protective wafer 1100W The volume ratio to the package may be greater than the volume ratio of the semiconductor die 1200 to the package. This can suppress the influence due to the CTE difference between the semiconductor die 1200 and the photosensitive dielectric layers 1410 and 1450. Therefore, the warpage of the package can be suppressed.

參照圖19，可以使用分離製程沿著晶片安裝區域1105之間的邊界區域1106對第二感光介電層1450、第一感光介電層1410和經減薄的保護晶圓1100W進行切割，因此提供彼此分離的晶圓級封裝件100和101。例如，鋸片1800可以被設置在用作劃道的邊界區域1106上，並且可以使用鋸片1800沿著邊界區域1106對感光介電層1450和1410與經減薄的保護晶圓1100W進行切割以產生彼此分離的晶圓級封裝件100和101。即使在感光介電層1450和1410與經減薄的保護晶圓1100W被切割以產生晶圓級封裝件100和101之後，晶圓級封裝件100和101中的每一個仍然可以包括經減薄的保護晶圓1100W的一部分，即，單位保護晶圓1100U。因此，單位保護晶圓1100U仍然可以覆蓋半導體晶粒1200的第三表面1206以保護半導體晶粒1200。 Referring to FIG. 19, the second photosensitive dielectric layer 1450, the first photosensitive dielectric layer 1410, and the thinned protective wafer 1100W may be diced along the boundary region 1106 between the wafer mounting regions 1105 using a separation process, and thus provide Wafer-level packages 100 and 101 separated from each other. For example, the saw blade 1800 may be disposed on the boundary area 1106 used as a scribe lane, and the saw blade 1800 may be used to cut the photosensitive dielectric layers 1450 and 1410 and the thinned protective wafer 1100W along the boundary area 1106 to Wafer-level packages 100 and 101 separated from each other are produced. Even after the photosensitive dielectric layers 1450 and 1410 and the thinned protective wafer 1100W are cut to produce wafer-level packages 100 and 101, each of the wafer-level packages 100 and 101 may still include the thinned Part of the protection wafer 1100W, that is, the unit protection wafer 1100U. Therefore, the unit protection wafer 1100U can still cover the third surface 1206 of the semiconductor die 1200 to protect the semiconductor die 1200.

圖20是例示了根據實施方式的晶圓級封裝件100的示例的表示的截面圖。 20 is a cross-sectional view illustrating a representation of an example of a wafer-level package 100 according to an embodiment.

參照圖20，晶圓級封裝件100可以與扇出半導體封裝件對應。晶圓級封裝件100可以包括使用黏合層1300附接到單位保護晶圓1100U的第一表面1101的半導體晶粒1200。晶圓級封裝件100還可以包括覆蓋半導體晶粒1200並且具有側壁1410S和平坦頂表面1410P的第一感光介電層1410。晶圓級封裝件100可以包括堆疊在第一感光介電層1410上的第二感光介電層1450。第二感光介電層1450可以具有平坦頂表面1450P以及與第 一感光介電層1410的側壁1410S對準的側壁1450S。側壁1410S和側壁1450S可以與單位保護晶圓1100U的側壁1100S對準。對準標記1110可以被設置在單位保護晶圓1100U的第一表面1101處，並且可以被設置為與半導體晶粒1200相鄰。單位保護晶圓1100U的厚度T1可以大於半導體晶粒1200的厚度T2。 Referring to FIG. 20, the wafer-level package 100 may correspond to a fan-out semiconductor package. The wafer-level package 100 may include the semiconductor die 1200 attached to the first surface 1101 of the unit protection wafer 1100U using the adhesive layer 1300. The wafer-level package 100 may further include a first photosensitive dielectric layer 1410 covering the semiconductor die 1200 and having sidewalls 1410S and a flat top surface 1410P. The wafer-level package 100 may include a second photosensitive dielectric layer 1450 stacked on the first photosensitive dielectric layer 1410. The second photosensitive dielectric layer 1450 may have a flat top surface 1450P and a The sidewall 1410S of a photosensitive dielectric layer 1410 is aligned with the sidewall 1450S. The sidewall 1410S and the sidewall 1450S may be aligned with the sidewall 1100S of the unit protection wafer 1100U. The alignment mark 1110 may be disposed at the first surface 1101 of the unit protection wafer 1100U, and may be disposed adjacent to the semiconductor die 1200. The thickness T1 of the unit protection wafer 1100U may be greater than the thickness T2 of the semiconductor die 1200.

晶圓級封裝件100也可以包括設置在第一感光介電層1410與第二感光介電層1450之間的再分配線1500。再分配線1500可以延伸到第一感光介電層1410中，並且可以電連接到半導體晶粒1200的內部連接件1201。半導體晶粒1200可以具有彼此相對的第三表面1206和第四表面1207，並且內部連接件1201可以被設置在半導體晶粒1200的第四表面1207上。晶圓級封裝件100還可以包括設置在第二感光介電層1450的平坦頂表面1450P上的外部連接件1600。外部連接件160可以延伸到第二感光介電層1450中，並且可以電連接到再分配線1500的跡線圖案1550。外部連接件1600可以具有焊球的形狀。 The wafer-level package 100 may also include a redistribution line 1500 disposed between the first photosensitive dielectric layer 1410 and the second photosensitive dielectric layer 1450. The redistribution line 1500 may extend into the first photosensitive dielectric layer 1410, and may be electrically connected to the internal connector 1201 of the semiconductor die 1200. The semiconductor die 1200 may have a third surface 1206 and a fourth surface 1207 opposite to each other, and the internal connector 1201 may be provided on the fourth surface 1207 of the semiconductor die 1200. The wafer-level package 100 may further include an external connector 1600 disposed on the flat top surface 1450P of the second photosensitive dielectric layer 1450. The external connector 160 may extend into the second photosensitive dielectric layer 1450, and may be electrically connected to the trace pattern 1550 of the redistribution line 1500. The external connection 1600 may have the shape of a solder ball.

圖21至圖30是例示了根據實施方式的製造晶圓級封裝件的方法的示例的表示的截面圖。 21 to 30 are cross-sectional views illustrating an example of a method of manufacturing a wafer-level package according to an embodiment.

參照圖21，可以提供保護晶圓4100W以使用晶圓級封裝件的製造技術來製造扇出半導體封裝件。保護晶圓4100W可以是半導體晶圓或者半導體基板，例如，矽晶圓。在一些實施方式中，保護晶圓4100W可以是由與矽晶圓不同的材料組成的晶圓。在一些其它實施方式中，保護晶圓4100W可以由CTE基本上與附接到保護晶圓4100W的半導體晶粒4200的主體的CTE相等的材料組成。在這種情況下，可以抑制由於半導體晶粒 與保護基板之間的CTE差而導致的一些故障(例如，翹曲)。例如，如果半導體晶粒4200中的每一個具有矽主體，則保護晶圓4100W可以由矽材料組成。 Referring to FIG. 21, a protection wafer 4100W may be provided to manufacture a fan-out semiconductor package using wafer-level package manufacturing technology. The protection wafer 4100W may be a semiconductor wafer or a semiconductor substrate, for example, a silicon wafer. In some embodiments, the protection wafer 4100W may be a wafer composed of a material different from the silicon wafer. In some other embodiments, the protection wafer 4100W may be composed of a material having a CTE substantially equal to the CTE of the body of the semiconductor die 4200 attached to the protection wafer 4100W. In this case, it is possible to suppress Some failures (eg, warpage) caused by poor CTE with the protection substrate. For example, if each of the semiconductor dies 4200 has a silicon body, the protection wafer 4100W may be composed of silicon material.

保護晶圓4100W可以具有彼此相對的第一表面4101和第二表面4103，並且可以在保護晶圓4100W的第一表面4101處形成對準標記4110。當在後續製程中重新構成半導體晶粒4200時，對準標記4110可以被用作用於指派半導體晶粒4200的位置的參考標記。保護晶圓4100W可以包括多個晶片安裝區域4105以及所述多個晶片安裝區域4105之間的邊界區域4106。半導體晶粒4200可以被分別安裝在晶片安裝區域4105上，並且邊界區域4106可以用作劃道。因此，邊界區域4106可以包圍晶片安裝區域4105。對準標記4110可以被設置在邊界區域4106中以與晶片安裝區域4105相鄰。對準標記4110可以被形成為具有比保護晶圓4100W的第一表面4101低或者高的表面。例如，對準標記4110可以通過對保護晶圓4100W的第一表面4101的一部分進行選擇性蝕刻而被形成為具有凹槽形狀或者凹面形狀。因此，可以在後續製程中使用對準標記4110來實現精確的對準。也就是說，保護晶圓4100W的第一表面4101與對準標記4110的底表面之間的高度差可以產生具有高解析度的圖像，並且可以使用具有高解析度的對準標記圖像來精確地設置或者識別保護晶圓4100W的特定位置。 The protection wafer 4100W may have a first surface 4101 and a second surface 4103 opposite to each other, and an alignment mark 4110 may be formed at the first surface 4101 of the protection wafer 4100W. When the semiconductor die 4200 is reconstructed in a subsequent process, the alignment mark 4110 may be used as a reference mark for assigning the position of the semiconductor die 4200. The protection wafer 4100W may include a plurality of wafer mounting regions 4105 and a boundary region 4106 between the plurality of wafer mounting regions 4105. The semiconductor dies 4200 may be respectively mounted on the wafer mounting area 4105, and the boundary area 4106 may be used as a scribe lane. Therefore, the boundary region 4106 may surround the wafer mounting region 4105. The alignment mark 4110 may be disposed in the boundary area 4106 to be adjacent to the wafer mounting area 4105. The alignment mark 4110 may be formed to have a lower or higher surface than the first surface 4101 of the protection wafer 4100W. For example, the alignment mark 4110 may be formed to have a groove shape or a concave shape by selectively etching a part of the first surface 4101 of the protection wafer 4100W. Therefore, the alignment mark 4110 can be used in subsequent processes to achieve accurate alignment. That is, the difference in height between the first surface 4101 of the protection wafer 4100W and the bottom surface of the alignment mark 4110 can produce an image with high resolution, and an alignment mark image with high resolution can be used to Precisely set or identify the specific position of the protection wafer 4100W.

可以在包括對準標記4110的第一表面4101上形成導電層，以提供用於保護半導體晶粒4200免受電磁干擾(在下文中，稱作“EMI”)的第一遮罩層4150。可以通過使用化學氣相沉積(CVD)製程或者電鍍製程沉積諸如銅層這樣的金屬層來形成第一遮罩層4150。如果保護晶圓 4100W是矽晶圓，則可以利用在半導體製造中使用的設備來執行用於製造晶圓級封裝件的全部製程。 A conductive layer may be formed on the first surface 4101 including the alignment mark 4110 to provide a first mask layer 4150 for protecting the semiconductor die 4200 from electromagnetic interference (hereinafter, referred to as "EMI"). The first mask layer 4150 may be formed by depositing a metal layer such as a copper layer using a chemical vapor deposition (CVD) process or an electroplating process. If you protect the wafer 4100W is a silicon wafer, you can use the equipment used in semiconductor manufacturing to perform the entire process for manufacturing wafer-level packages.

半導體晶粒4200可以被設置在保護晶圓4100W的第一表面4101上以使用對準標記4110分別與晶片安裝區域4105對準，並且半導體晶粒4200可以被分別安裝在晶片安裝區域4105上。每個半導體晶粒4200具有面對保護晶圓4100W的第一表面4101的第三表面4206，並且可以在半導體晶粒4200的第三表面4206上設置黏合層4300。例如連接焊墊的內部連接件4201可以被設置在半導體晶粒4200的與保護晶圓4100W相反的第四表面4207上。因此，半導體晶粒4200可以使用黏合層4300被安裝在保護晶圓4100W上。黏合層4300可以提供保護晶圓4100W與半導體晶粒4200之間的永久接合，以將半導體晶粒4200固定到保護晶圓4100W。與用於在用於製造晶圓級封裝件的一般技術中將臨時載體(或者處理支承件)臨時附接到半導體晶粒的臨時黏合層不同，黏合層4300可以提供保護晶圓4100W與半導體晶粒4200之間的不可逆接合。如果UV射線照射到臨時黏合層上，則臨時黏合層會失去其黏合強度。因此，可以使用UV射線來將臨時載體(或者處理支承件)與半導體晶粒分離。在實施方式中，黏合層4300可以在半導體晶粒4200被安裝在保護晶圓4100W上之後固化。在這種情況下，即使UV射線照射到經固化的黏合層4300上，經固化的黏合層4300也不會失去其黏合強度。黏合層4300可以包含用作硬化性黏合劑成分的環氧樹脂成分。由於黏合層4300將半導體晶粒4200牢固地接合並固定到保護晶圓4100W，因此黏合層4300可以在後續製程期間抑制半導體晶粒4200的位置移位。在本公開中，保護晶圓4100W不與半導體晶粒4200分離，並且保護 晶圓4100W的一部分可以構成每個封裝件的一部分。因此，可以使用能夠將半導體晶粒4200永久地固定到保護晶圓4100W的不可逆黏合材料作為黏合層4300。 The semiconductor die 4200 may be disposed on the first surface 4101 of the protection wafer 4100W to be aligned with the wafer mounting area 4105 respectively using the alignment marks 4110, and the semiconductor die 4200 may be mounted on the wafer mounting area 4105, respectively. Each semiconductor die 4200 has a third surface 4206 facing the first surface 4101 of the protection wafer 4100W, and an adhesive layer 4300 may be provided on the third surface 4206 of the semiconductor die 4200. For example, an internal connector 4201 connecting pads may be provided on the fourth surface 4207 of the semiconductor die 4200 opposite to the protection wafer 4100W. Therefore, the semiconductor die 4200 can be mounted on the protective wafer 4100W using the adhesive layer 4300. The adhesive layer 4300 may provide a permanent bond between the protection wafer 4100W and the semiconductor die 4200 to fix the semiconductor die 4200 to the protection wafer 4100W. Unlike the temporary adhesive layer used to temporarily attach the temporary carrier (or process support) to the semiconductor die in the general technology used to manufacture wafer-level packages, the adhesive layer 4300 can provide protection to the wafer 4100W and the semiconductor crystal Irreversible bonding between the particles 4200. If UV rays are irradiated on the temporary adhesive layer, the temporary adhesive layer will lose its adhesive strength. Therefore, UV rays can be used to separate the temporary carrier (or processing support) from the semiconductor die. In an embodiment, the adhesive layer 4300 may be cured after the semiconductor die 4200 is mounted on the protective wafer 4100W. In this case, even if UV rays are irradiated onto the cured adhesive layer 4300, the cured adhesive layer 4300 will not lose its adhesive strength. The adhesive layer 4300 may contain an epoxy resin component used as a hardening adhesive component. Since the adhesive layer 4300 firmly bonds and fixes the semiconductor die 4200 to the protection wafer 4100W, the adhesive layer 4300 can suppress the positional displacement of the semiconductor die 4200 during the subsequent process. In the present disclosure, the protection wafer 4100W is not separated from the semiconductor die 4200, and the protection A part of the wafer 4100W may constitute a part of each package. Therefore, an irreversible adhesive material capable of permanently fixing the semiconductor die 4200 to the protection wafer 4100W may be used as the adhesive layer 4300.

在一些實施方式中，黏合層4300可以包含熱介面材料成分或者導熱成分，以提供輻射或者散發由半導體晶粒4200的操作產生的熱的路徑。如果黏合層4300中包含諸如金屬顆粒這樣的導熱成分或者熱介面材料成分，則半導體晶粒4200中產生的熱可以被更容易地散發到第一遮罩層4150和保護晶圓4100W中。保護晶圓4100W的熱導率可以高於在後續製程中被形成為包圍半導體晶粒4200的感光材料層(圖26的4410和4450)的熱導率。因此，可以更有效地散發半導體晶粒4200中產生的熱。 In some embodiments, the adhesive layer 4300 may include a thermal interface material component or a thermally conductive component to provide a path for radiating or dissipating heat generated by the operation of the semiconductor die 4200. If the adhesive layer 4300 contains a thermally conductive component such as metal particles or a thermal interface material component, the heat generated in the semiconductor die 4200 can be more easily dissipated into the first mask layer 4150 and the protective wafer 4100W. The thermal conductivity of the protection wafer 4100W may be higher than the thermal conductivity of the photosensitive material layers (4410 and 4450 of FIG. 26) formed to surround the semiconductor die 4200 in the subsequent process. Therefore, the heat generated in the semiconductor die 4200 can be more efficiently dissipated.

例如連接焊墊的內部連接件4201可以被設置在半導體晶粒4200的與保護晶圓4100W相反的第四表面4207上。因此，半導體晶粒4200可以被安裝在保護晶圓4100W上，以使得內部連接件4201被設置在半導體晶粒4200的與保護晶圓4100W相反的表面(即，第四表面4207)上。半導體晶粒4200可以被分別設置在通過邊界區域4106彼此分隔開的晶片安裝區域4105上。因此，半導體晶粒4200可以被並排地排列在第一遮罩層4150上。 For example, an internal connector 4201 connecting pads may be provided on the fourth surface 4207 of the semiconductor die 4200 opposite to the protection wafer 4100W. Therefore, the semiconductor die 4200 may be mounted on the protection wafer 4100W, so that the internal connection 4201 is provided on the surface of the semiconductor die 4200 opposite to the protection wafer 4100W (ie, the fourth surface 4207). The semiconductor dies 4200 may be respectively disposed on the wafer mounting regions 4105 separated from each other by the boundary region 4106. Therefore, the semiconductor dies 4200 may be arranged side by side on the first mask layer 4150.

參照圖22，可以在第一遮罩層4150上形成第一感光介電層4410以覆蓋半導體晶粒4200。如參照圖9、圖10和圖11所述的，可以通過使用層壓製程將第一感光介電膜附接到第一遮罩層4150和半導體晶粒4200並且使附接到第一遮罩層4150和半導體晶粒4200的第一感光介電膜平坦化來形成第一感光介電層4410。結果，第一感光介電層4410可以具有平坦頂 表面4410P。第一感光介電層4410可以包括諸如感光聚醯亞胺膜或者感光聚苯並惡唑膜這樣的感光聚合物膜。在一些實施方式中，第一感光介電層4410可以由包含環氧樹脂成分的感光膜來形成。由於第一感光介電層包含光敏劑，因此第一感光介電層1410的暴露於光(諸如UV射線)的一部分可以具有與第一感光介電層4410的沒有暴露於光(諸如UV射線)的另一部分的溶解度不同的溶解度。 Referring to FIG. 22, a first photosensitive dielectric layer 4410 may be formed on the first mask layer 4150 to cover the semiconductor die 4200. As described with reference to FIGS. 9, 10 and 11, the first photosensitive dielectric film can be attached to the first mask layer 4150 and the semiconductor die 4200 by using a lamination process and attached to the first mask The first photosensitive dielectric film of the layer 4150 and the semiconductor die 4200 is planarized to form a first photosensitive dielectric layer 4410. As a result, the first photosensitive dielectric layer 4410 may have a flat top Surface 4410P. The first photosensitive dielectric layer 4410 may include a photosensitive polymer film such as a photosensitive polyimide film or a photosensitive polybenzoxazole film. In some embodiments, the first photosensitive dielectric layer 4410 may be formed of a photosensitive film containing an epoxy resin component. Since the first photosensitive dielectric layer contains a photosensitizer, a portion of the first photosensitive dielectric layer 1410 that is exposed to light (such as UV rays) may have a difference from the first photosensitive dielectric layer 4410 that is not exposed to light (such as UV rays) The solubility of the other part is different.

即使第一表面4101由於對準標記4110和半導體晶粒4200被設置在第一表面4101上而具有不平坦表面，第一感光介電層4410也可以具有平坦頂表面4410P。由於第一感光介電層4410具有平坦頂表面4410P，因此能夠在沒有圖案失真的情況下在第一感光介電層4410的平坦頂表面4410P上形成精細的圖案。也就是說，能夠在沒有圖案失真的情況下在第一感光介電層4410的平坦頂表面4410P上形成具有精細節距的互連線。 Even if the first surface 4101 has an uneven surface due to the alignment mark 4110 and the semiconductor die 4200 being provided on the first surface 4101, the first photosensitive dielectric layer 4410 may have a flat top surface 4410P. Since the first photosensitive dielectric layer 4410 has a flat top surface 4410P, a fine pattern can be formed on the flat top surface 4410P of the first photosensitive dielectric layer 4410 without pattern distortion. That is, it is possible to form interconnect lines with fine pitch on the flat top surface 4410P of the first photosensitive dielectric layer 4410 without pattern distortion.

參照圖23，可以在第一感光介電層4410中形成第一開口部4411，以使半導體晶粒4200的一部分(例如，內部連接件4201)暴露。第一開口部4411可以被形成為貫穿第一感光介電層4410。在形成第一開口部4411的同時，還可以在第一感光介電層4410中形成溝槽4413，以使第一遮罩層4150的一部分暴露。溝槽4413可以被形成為使第一遮罩層4150的與用作劃道的邊界區域4106交疊的一部分暴露。由於溝槽4413沿著邊界區域4106形成，因此溝槽4413可以包圍半導體晶粒4200。第一感光介電層4410可以通過溝槽4413被分離為多個圖案，並且第一感光介電層4410的側壁4410S可以通過溝槽4413暴露。 Referring to FIG. 23, a first opening 4411 may be formed in the first photosensitive dielectric layer 4410 to expose a portion of the semiconductor die 4200 (eg, the internal connection 4201). The first opening portion 4411 may be formed to penetrate the first photosensitive dielectric layer 4410. Simultaneously with the formation of the first opening 4411, a groove 4413 may be formed in the first photosensitive dielectric layer 4410 to expose a portion of the first mask layer 4150. The trench 4413 may be formed to expose a portion of the first mask layer 4150 that overlaps the boundary area 4106 serving as a scribe lane. Since the trench 4413 is formed along the boundary region 4106, the trench 4413 may surround the semiconductor die 4200. The first photosensitive dielectric layer 4410 may be separated into a plurality of patterns through the trench 4413, and the sidewall 4410S of the first photosensitive dielectric layer 4410 may be exposed through the trench 4413.

第一開口部4411和溝槽4413可以通過選擇性地使第一感光 介電層4410的一部分暴露於諸如UV射線的光並且對所暴露的第一感光介電層4410進行顯影而被形成為貫穿第一感光介電層4410。在這種情況下，由於第一感光介電層4410由感光介電膜形成，因此可以對第一感光介電層4410直接應用光微影製程以形成第一開口部4411和溝槽4413。因此，即時在沒有使用任何附加光阻材料的情況下，也可以形成第一開口部4411和溝槽4413。 The first opening 4411 and the groove 4413 can selectively make the first photosensitive A portion of the dielectric layer 4410 is exposed to light such as UV rays and the exposed first photosensitive dielectric layer 4410 is developed to be formed through the first photosensitive dielectric layer 4410. In this case, since the first photosensitive dielectric layer 4410 is formed of a photosensitive dielectric film, a photolithography process may be directly applied to the first photosensitive dielectric layer 4410 to form the first opening 4411 and the trench 4413. Therefore, even without using any additional photoresist material, the first opening 4411 and the groove 4413 can be formed.

參照圖24，可以在具有第一開口部4411和溝槽4413的第一感光介電層4410上形成光阻圖案4700。光阻圖案4700可以被用作遮罩，例如，用於形成再分配線的電鍍遮罩。光阻圖案4700可以通過將光阻材料塗覆在第一感光介電層4410上並且使用曝光製程和顯影製程對光阻材料進行圖案化而形成。光阻圖案4700可以被形成為使第一開口部4411和溝槽4413暴露以及使第一感光介電層4410的平坦頂表面4410P的與第一開口部4411相鄰的部分暴露。光阻圖案4700可以被形成為限定設置有再分配線的區域。 Referring to FIG. 24, a photoresist pattern 4700 may be formed on the first photosensitive dielectric layer 4410 having the first opening 4411 and the trench 4413. The photoresist pattern 4700 may be used as a mask, for example, an electroplating mask for forming a redistribution line. The photoresist pattern 4700 may be formed by coating a photoresist material on the first photosensitive dielectric layer 4410 and patterning the photoresist material using an exposure process and a development process. The photoresist pattern 4700 may be formed to expose the first opening portion 4411 and the groove 4413 and expose a portion of the flat top surface 4410P of the first photosensitive dielectric layer 4410 adjacent to the first opening portion 4411. The photoresist pattern 4700 may be formed to define an area where redistribution lines are provided.

參照圖25，可以在第一感光介電層4410的通過光阻圖案(圖24的4700)暴露的平坦頂表面4410P上以及在通過光阻圖案4700暴露的第一開口部4411和溝槽4413中形成再分配線4500。然後，可以去除光阻圖案4700。光阻圖案4700可以用作限定再分配線4500的形狀的圖案化遮罩。再分配線4500可以通過將包含銅的電鍍層選擇性地沉積在通過光阻圖案4700暴露的第一感光介電層4410上而形成，並且可以去除光阻圖案4700。可選地，再分配線4500可以通過將包含銅的導電層沉積在第一感光介電層4410和光阻圖案4700二者上並且將光阻圖案4700剝離而形成。 Referring to FIG. 25, on the flat top surface 4410P of the first photosensitive dielectric layer 4410 exposed through the photoresist pattern (4700 of FIG. 24) and in the first opening 4411 and the trench 4413 exposed through the photoresist pattern 4700 Form a redistribution line 4500. Then, the photoresist pattern 4700 may be removed. The photoresist pattern 4700 may be used as a patterned mask that defines the shape of the redistribution line 4500. The redistribution line 4500 may be formed by selectively depositing a plating layer containing copper on the first photosensitive dielectric layer 4410 exposed through the photoresist pattern 4700, and the photoresist pattern 4700 may be removed. Alternatively, the redistribution line 4500 may be formed by depositing a conductive layer containing copper on both the first photosensitive dielectric layer 4410 and the photoresist pattern 4700 and peeling off the photoresist pattern 4700.

在將光阻圖案4700剝離以對導電層進行圖案化之後，在第 一感光介電層4410的平坦頂表面4410P上以及在第一開口部4411中剩餘的導電圖案可以對應於再分配線4500，並且在溝槽4413中剩餘的導電圖案可以對應於第二遮罩層4510。第二遮罩層4510可以被形成為與通過溝槽4413暴露的第一遮罩層4150接觸。因此，第二遮罩層4510可以電連接到第一遮罩層4150。因此，第一遮罩層4150和第二遮罩層4510可以包圍半導體晶粒4200的底表面(即，第三表面4206)和側壁，以構成用於保護半導體晶粒4200免受EMI的EMI遮罩籠。在一些實施方式中，可以通過以下方式來形成第二遮罩層4510和再分配線4500：在具有第一開口部4411和溝槽4413的第一感光介電層4410的整個表面上沉積導電層，在導電層上形成光阻圖案(未例示)，並且通過使用光阻圖案作為蝕刻遮罩對導電層進行蝕刻。 After the photoresist pattern 4700 is peeled off to pattern the conductive layer, after the The conductive patterns remaining on the flat top surface 4410P of a photosensitive dielectric layer 4410 and in the first opening 4411 may correspond to the redistribution line 4500, and the remaining conductive patterns in the trench 4413 may correspond to the second mask layer 4510. The second mask layer 4510 may be formed in contact with the first mask layer 4150 exposed through the trench 4413. Therefore, the second mask layer 4510 may be electrically connected to the first mask layer 4150. Therefore, the first mask layer 4150 and the second mask layer 4510 may surround the bottom surface (ie, the third surface 4206) and the sidewalls of the semiconductor die 4200 to constitute an EMI shield for protecting the semiconductor die 4200 from EMI Shroud. In some embodiments, the second mask layer 4510 and the redistribution line 4500 may be formed by depositing a conductive layer on the entire surface of the first photosensitive dielectric layer 4410 having the first opening 4411 and the groove 4413 , A photoresist pattern (not illustrated) is formed on the conductive layer, and the conductive layer is etched by using the photoresist pattern as an etching mask.

每個再分配線4500可以被形成為包括位於第一感光介電層4410的平坦頂表面4410P上以用作互連線的跡線圖案4550、以及位於第一開口部4411中的一個中以將跡線圖案4550電連接到內部連接件4201中的一個的通孔4530。通孔4530可以被形成為垂直地貫穿覆蓋半導體晶粒4200的第四表面4207的第一感光介電層4410，並且與內部連接件4201接觸。通孔4530可以被形成為填充第一開口部4411中的一個。跡線圖案4550可以延伸以與設置在半導體晶粒4200之間的第一感光介電層4410的一部分交疊。 Each redistribution line 4500 may be formed to include a trace pattern 4550 on the flat top surface 4410P of the first photosensitive dielectric layer 4410 to serve as an interconnect line, and one of the first openings 4411 to be The trace pattern 4550 is electrically connected to the through hole 4530 of one of the internal connectors 4201. The through hole 4530 may be formed to vertically penetrate the first photosensitive dielectric layer 4410 covering the fourth surface 4207 of the semiconductor die 4200 and contact the internal connector 4201. The through hole 4530 may be formed to fill one of the first openings 4411. The trace pattern 4550 may extend to overlap a portion of the first photosensitive dielectric layer 4410 disposed between the semiconductor die 4200.

由於第一感光介電層4410具有平坦頂表面4410P，因此光阻圖案(圖24中的4700)可以被形成為在沒有圖案失真的情況下具有精細的節距。因此，其形狀通過光阻圖案(圖24中的4700)限定的再分配線4500也可以被形成為在沒有圖案失真的情況下具有精細的節距。因此，能夠增 加有限區域中所形成的再分配線4500的數目。 Since the first photosensitive dielectric layer 4410 has a flat top surface 4410P, a photoresist pattern (4700 in FIG. 24) can be formed to have a fine pitch without pattern distortion. Therefore, the redistribution line 4500 whose shape is defined by the photoresist pattern (4700 in FIG. 24) can also be formed to have a fine pitch without pattern distortion. Therefore, it is possible to increase Add the number of redistribution lines 4500 formed in the limited area.

參照圖26，可以在第一感光介電層4410的平坦頂表面4410P上形成第二感光介電層4450，以覆蓋再分配線4500和第二遮罩層4510。第二感光介電層4450可以通過將第二感光介電膜(未例示)設置在第一感光介電層4410和再分配線4500上並且使用層壓製程將第二感光介電膜附接到第一感光介電層4410而形成。附接到第一感光介電層4410的第二感光介電膜可以被平坦化以提供具有平坦頂表面4450P的第二感光介電層4450。由於第二感光介電層4450具有平坦頂表面4450P，因此可以在第二感光介電層4450上更容易地形成精細的圖案。在一些實施方式中，第二感光介電層4450可以由基本上與第一感光介電層4410相同的材料形成。 Referring to FIG. 26, a second photosensitive dielectric layer 4450 may be formed on the flat top surface 4410P of the first photosensitive dielectric layer 4410 to cover the redistribution line 4500 and the second mask layer 4510. The second photosensitive dielectric layer 4450 may be provided by attaching a second photosensitive dielectric film (not illustrated) on the first photosensitive dielectric layer 4410 and the redistribution line 4500 and using a lamination process to attach the second photosensitive dielectric film to The first photosensitive dielectric layer 4410 is formed. The second photosensitive dielectric film attached to the first photosensitive dielectric layer 4410 may be planarized to provide a second photosensitive dielectric layer 4450 having a flat top surface 4450P. Since the second photosensitive dielectric layer 4450 has a flat top surface 4450P, a fine pattern can be formed more easily on the second photosensitive dielectric layer 4450. In some embodiments, the second photosensitive dielectric layer 4450 may be formed of substantially the same material as the first photosensitive dielectric layer 4410.

參照圖27，可以對第二感光介電層4450進行圖案化以形成貫穿第二感光介電層4450的一部分的第二開口部4451。第二開口部4451中的每一個可以被形成為使再分配線4500的跡線圖案4550的任意一個的一部分暴露。第二開口部4451中的一些可以被形成為不與半導體晶粒4200交疊。也就是說，第二開口部4451中的一些可以被形成在邊界區域4106上。 Referring to FIG. 27, the second photosensitive dielectric layer 4450 may be patterned to form a second opening portion 4451 penetrating a portion of the second photosensitive dielectric layer 4450. Each of the second openings 4451 may be formed to expose a part of any one of the trace patterns 4550 of the redistribution line 4500. Some of the second openings 4451 may be formed so as not to overlap the semiconductor die 4200. That is, some of the second opening portion 4451 may be formed on the boundary area 4106.

參照圖28，外部連接件4600可以分別附接到通過第二開口部4451暴露的跡線圖案4550。因此，外部連接件4600可以電連接到跡線圖案4550。外部連接件4600可以具有焊球的形狀。另選地，外部連接件4600可以具有凸塊的形狀。外部連接件4600中的一些可以被定位為不與半導體晶粒4200交疊。跡線圖案4550可以延伸到晶片安裝區域4105之間的邊界區域4106上以實現扇出半導體封裝件。 Referring to FIG. 28, the external connectors 4600 may be respectively attached to the trace patterns 4550 exposed through the second opening portion 4451. Therefore, the external connector 4600 may be electrically connected to the trace pattern 4550. The external connector 4600 may have the shape of a solder ball. Alternatively, the external connector 4600 may have a bump shape. Some of the external connectors 4600 may be positioned so as not to overlap the semiconductor die 4200. The trace pattern 4550 may extend onto the boundary area 4106 between the wafer mounting areas 4105 to realize the fan-out semiconductor package.

參照圖29，可以執行減薄步驟以減小保護晶圓4100W的厚度。也就是說，可以使保護晶圓4100W的第二表面4103凹進以提供凹進的第二表面4103B。可以通過對保護晶圓4100W的第二表面4103應用研磨製程來執行減薄步驟。另選地，可以通過對保護晶圓4100W的第二表面4103應用化學機械拋光(CMP)製程或回蝕製程來執行減薄步驟。 Referring to FIG. 29, a thinning step may be performed to reduce the thickness of the protective wafer 4100W. That is, the second surface 4103 of the protection wafer 4100W may be recessed to provide the recessed second surface 4103B. The thinning step may be performed by applying a grinding process to the second surface 4103 of the protection wafer 4100W. Alternatively, the thinning step may be performed by applying a chemical mechanical polishing (CMP) process or an etch-back process to the second surface 4103 of the protection wafer 4100W.

參照圖30，可以使用分離製程沿著晶片安裝區域4105之間的邊界區域4106對第二感光介電層4450、第一感光介電層4410和經減薄的保護晶圓4100W進行切割，因此提供彼此分離的晶圓級封裝件400和401。例如，鋸片4800可以被設置在用作劃道的邊界區域4106上，並且可以使用鋸片4800沿著邊界區域4106對感光介電層4450和4410與經減薄的保護晶圓4100W進行切割以產生彼此分離的晶圓級封裝件400和401。晶圓級封裝件400和401中的每一個仍然可以包括經減薄的保護晶圓4100W的一部分，即，單位保護晶圓4100U。因此，單位保護晶圓4100U仍然可以覆蓋半導體晶粒4200的第三表面4206以保護半導體晶粒4200。 Referring to FIG. 30, the second photosensitive dielectric layer 4450, the first photosensitive dielectric layer 4410, and the thinned protective wafer 4100W may be diced along the boundary region 4106 between the wafer mounting regions 4105 using a separation process, and thus provide Wafer-level packages 400 and 401 separated from each other. For example, the saw blade 4800 may be disposed on the boundary area 4106 used as a scribe lane, and the saw blade 4800 may be used to cut the photosensitive dielectric layers 4450 and 4410 and the thinned protective wafer 4100W along the boundary area 4106 to Wafer-level packages 400 and 401 separated from each other are produced. Each of the wafer-level packages 400 and 401 may still include a portion of the thinned protective wafer 4100W, that is, the unit protective wafer 4100U. Therefore, the unit protection wafer 4100U can still cover the third surface 4206 of the semiconductor die 4200 to protect the semiconductor die 4200.

圖31是例示了根據實施方式的晶圓級封裝件400的示例的表示的截面圖。 31 is a cross-sectional view illustrating a representation of an example of a wafer-level package 400 according to an embodiment.

參照圖31，晶圓級封裝件400可以與扇出半導體封裝件對應。晶圓級封裝件400可以包括具有彼此相對的第一表面4101和第二表面4103B的單位保護晶圓4100U。晶圓級封裝件400還可以包括覆蓋單位保護晶圓4100U的第一表面4101的第一遮罩層4150。晶圓級封裝件400可以包括使用黏合層4300附接到第一遮罩層4150的半導體晶粒4200。晶圓級封裝件400可以包括覆蓋半導體晶粒4200並且具有側壁4410S和平坦頂表面 4410P的第一感光介電層4410。晶圓級封裝件400可以附加地包括覆蓋第一感光介電層4410的側壁4410S和平坦頂表面4410P的第二感光介電層4450。第二感光介電層4450可以具有側壁4450S和平坦頂表面4450P。第二遮罩層4510可以被設置在第二感光介電層4450與第一感光介電層4410的側壁4410S之間。也就是說，第二遮罩層4510可以被設置為覆蓋第一感光介電層4410的側壁4410S。第二遮罩層4510可以與覆蓋單位保護晶圓4100U的第一表面4101的第一遮罩層4150電連接。 Referring to FIG. 31, the wafer-level package 400 may correspond to a fan-out semiconductor package. The wafer-level package 400 may include a unit protection wafer 4100U having a first surface 4101 and a second surface 4103B opposed to each other. The wafer-level package 400 may further include a first mask layer 4150 covering the first surface 4101 of the unit protection wafer 4100U. The wafer-level package 400 may include a semiconductor die 4200 attached to the first mask layer 4150 using an adhesive layer 4300. The wafer-level package 400 may include a semiconductor die 4200 and has a sidewall 4410S and a flat top surface The first photosensitive dielectric layer 4410 of 4410P. The wafer-level package 400 may additionally include a second photosensitive dielectric layer 4450 covering the sidewall 4410S of the first photosensitive dielectric layer 4410 and the flat top surface 4410P. The second photosensitive dielectric layer 4450 may have a side wall 4450S and a flat top surface 4450P. The second mask layer 4510 may be disposed between the second photosensitive dielectric layer 4450 and the sidewall 4410S of the first photosensitive dielectric layer 4410. That is, the second mask layer 4510 may be disposed to cover the sidewall 4410S of the first photosensitive dielectric layer 4410. The second mask layer 4510 may be electrically connected to the first mask layer 4150 covering the first surface 4101 of the unit protection wafer 4100U.

晶圓級封裝件400還可以包括設置在第一感光介電層4410的頂表面4410P與第二感光介電層4450的底表面之間的再分配線4500。再分配線4500可以延伸到第一感光介電層4410中，並且可以電連接到半導體晶粒4200的內部連接件4201。再分配線4500和第二遮罩層4510可以通過對單個導電層進行圖案化來提供。第二遮罩層4510可以延伸以與第一遮罩層4150的一部分交疊。 The wafer-level package 400 may further include a redistribution line 4500 disposed between the top surface 4410P of the first photosensitive dielectric layer 4410 and the bottom surface of the second photosensitive dielectric layer 4450. The redistribution line 4500 may extend into the first photosensitive dielectric layer 4410, and may be electrically connected to the internal connection 4201 of the semiconductor die 4200. The redistribution line 4500 and the second mask layer 4510 may be provided by patterning a single conductive layer. The second mask layer 4510 may extend to overlap a portion of the first mask layer 4150.

半導體晶粒4200可以具有彼此相對的第三表面4206和第四表面4207，並且內部連接件4201可以被設置在半導體晶粒4200的第四表面4207上。再分配線4500中的每一個可以包括貫穿第一感光介電層4410的一部分的通孔4530以及設置在第一感光介電層4410的頂表面4410P上的跡線圖案4550。晶圓級封裝件400還可以包括電連接到再分配線4500的外部連接件4600。 The semiconductor die 4200 may have a third surface 4206 and a fourth surface 4207 opposite to each other, and the internal connection 4201 may be provided on the fourth surface 4207 of the semiconductor die 4200. Each of the redistribution lines 4500 may include a through hole 4530 penetrating a portion of the first photosensitive dielectric layer 4410 and a trace pattern 4550 provided on the top surface 4410P of the first photosensitive dielectric layer 4410. The wafer-level package 400 may further include an external connector 4600 electrically connected to the redistribution line 4500.

圖32是例示了包括具有根據實施方式的至少一個半導體封裝件的記憶卡7800在內的電子系統的示例的表示的區塊圖。記憶卡7800包括諸如非揮發性記憶體件這樣的記憶體7810以及記憶體控制器7820。記 憶體7810和記憶體控制器7820可以存儲資料或者讀取存儲的資料。記憶體7810和/或記憶體控制器7820包括設置在根據實施方式的封裝件中的一個或更多個半導體晶片。 32 is a block diagram illustrating a representation of an example of an electronic system including a memory card 7800 having at least one semiconductor package according to an embodiment. The memory card 7800 includes a memory 7810 such as a non-volatile memory device and a memory controller 7820. Remember The memory 7810 and the memory controller 7820 can store data or read stored data. The memory 7810 and/or the memory controller 7820 include one or more semiconductor chips provided in the package according to the embodiment.

記憶體7810可以包括應用了實施方式的技術的非揮發性記憶體件。記憶體控制器7820可以控制記憶體7810，以使得回應於來自主機7830的讀/寫請求來讀出所存儲的資料或者將資料進行存儲。 The memory 7810 may include a non-volatile memory device to which the technology of the embodiment is applied. The memory controller 7820 may control the memory 7810 so that the stored data is read out or stored in response to the read/write request from the host 7830.

圖33是例示了包括根據實施方式的至少一個封裝件的電子系統8710的示例的表示的區塊圖。電子系統8710可以包括控制器8711、輸入/輸出裝置8712和記憶體8713。控制器8711、輸入/輸出裝置8712和記憶體8713可以通過提供資料移動所經過的路徑的匯流排8715而彼此接合。 33 is a block diagram illustrating a representation of an example of an electronic system 8710 including at least one package according to an embodiment. The electronic system 8710 may include a controller 8711, an input/output device 8712, and a memory 8713. The controller 8711, the input/output device 8712, and the memory 8713 can be joined to each other by a bus 8715 that provides a path through which data moves.

在一個實施方式中，控制器8711可以包括一個或更多個微處理器、數位訊號處理器、微控制器和/或能夠執行與這些元件相同的功能的邏輯器件。控制器8711或記憶體8713可以包括根據本公開的實施方式的一個或更多個半導體封裝件。輸入/輸出裝置8712可以包括在小鍵盤、鍵盤、顯示裝置、觸控式螢幕等當中選擇的至少一個。記憶體8713是用於存儲資料的裝置。記憶體8713可以存儲要由控制器8711執行的資料和/或命令等。 In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these elements. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to an embodiment of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. Memory 8713 is a device for storing data. The memory 8713 may store data and/or commands to be executed by the controller 8711 and the like.

記憶體8713可以包括諸如DRAM這樣的揮發性記憶體件和/或諸如快閃記憶體這樣的非揮發性記憶體件。例如，快閃記憶體可以被安裝到諸如移動終端或桌上型電腦這樣的資訊處理系統。快閃記憶體可以構成固態硬碟(SSD)。在這種情況下，電子系統8710可以將大量資料穩定地存儲在快閃記憶體系統中。 The memory 8713 may include a volatile memory device such as DRAM and/or a non-volatile memory device such as flash memory. For example, flash memory can be installed in information processing systems such as mobile terminals or desktop computers. Flash memory can constitute a solid state drive (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

電子系統8710還可以包括介面8714，該介面8714被配置為 向通信網路發送資料以及從通信網路接收資料。介面8714可以是有線類型或無線類型。例如，介面8714可以包括天線或者有線收發器或無線收發器。 The electronic system 8710 may further include an interface 8714 that is configured as Send data to and receive data from the communication network. The interface 8714 may be a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired transceiver or a wireless transceiver.

電子系統8710可以被實現為移動系統、個人電腦、工業電腦或者執行各種功能的邏輯系統。例如，移動系統可以是個人數位助理(PDA)、可攜式電腦、平板電腦、行動電話、智慧型手機、無線電話、膝上型電腦、記憶卡、數位音樂系統以及資訊發送/接收系統中的任一個。 The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be a personal digital assistant (PDA), portable computer, tablet computer, mobile phone, smartphone, wireless phone, laptop computer, memory card, digital music system, and information transmission/reception system Any one.

如果電子系統8710是能夠執行無線通訊的設備，則電子系統8710可以被用在諸如CDMA(分碼多重存取)、GSM(全球移動通信系統)、NADC(北美數位行動電話)、E-TDMA(強化分時多重存取)、WCDMA(寬頻分碼多重存取)、CDMA2000、LTE(長期演進技術)和Wibro(無線寬頻網際網路)的通信系統中。 If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 can be used in such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Mobile Phone), E-TDMA ( Enhanced time division multiple access), WCDMA (broadband frequency division multiple access), CDMA2000, LTE (long-term evolution technology) and Wibro (wireless broadband internet) communication systems.

出於例示的目的，已公開了本公開的實施方式。本領域技術人員將要領會的是，能夠在不脫離本公開以及所附的請求項的範圍和精神的情況下進行各種修改、添加和替換。 For the purpose of illustration, embodiments of the present disclosure have been disclosed. Those skilled in the art will appreciate that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the disclosure and the appended claims.

1100W‧‧‧保護晶圓 1100W‧‧‧Protection wafer

1101‧‧‧第一表面 1101‧‧‧First surface

1103‧‧‧第二表面 1103‧‧‧Second surface

1103B‧‧‧第二表面 1103B‧‧‧Second surface

1105‧‧‧晶片安裝區域 1105‧‧‧Chip installation area

1106‧‧‧邊界區域 1106‧‧‧Border area

1110‧‧‧對準標記 1110‧‧‧Alignment mark

1200‧‧‧半導體晶粒 1200‧‧‧Semiconductor die

1201‧‧‧內部連接件 1201‧‧‧Internal connector

1207‧‧‧第四表面 1207‧‧‧Fourth surface

1300‧‧‧黏合層 1300‧‧‧ adhesive layer

1410‧‧‧第一感光介電層 1410‧‧‧First photosensitive dielectric layer

1410P‧‧‧平坦表面 1410P‧‧‧flat surface

1411‧‧‧第一開口部 1411‧‧‧First opening

1450‧‧‧第二感光介電層 1450‧‧‧Second photosensitive dielectric layer

1450P‧‧‧平坦表面 1450P‧‧‧flat surface

1451‧‧‧第二開口部 1451‧‧‧Second opening

1500‧‧‧再分配線 1500‧‧‧ Redistribution line

1530‧‧‧通孔 1530‧‧‧Through hole

1550‧‧‧跡線圖案 1550‧‧‧ trace pattern

1600‧‧‧外部連接件 1600‧‧‧External connector

Claims (10)

一種晶圓級封裝件，該晶圓級封裝件包括：第一遮罩層，所述第一遮罩層覆蓋保護晶圓的第一表面；半導體晶粒，所述半導體晶粒被安裝在所述第一遮罩層上；第一介電層，所述第一介電層覆蓋所述半導體晶粒並且具有頂表面和側壁；第二介電層，所述第二介電層覆蓋所述第一介電層的所述頂表面和所述側壁；第二遮罩層，所述第二遮罩層被設置在所述第一介電層的所述側壁與所述第二介電層之間，以覆蓋所述第一介電層的所述側壁；再分配線，所述再分配線被設置在所述第一介電層的所述頂表面與所述第二介電層之間，並且穿過貫穿所述第一介電層的第一開口部電連接到所述半導體晶粒；以及外部連接件，所述外部連接件被設置在所述第二介電層上，並且穿過貫穿所述第二介電層的第二開口部電連接到所述再分配線。 A wafer-level package includes: a first mask layer covering the first surface of the protection wafer; a semiconductor die, the semiconductor die is mounted on the On the first mask layer; a first dielectric layer, the first dielectric layer covers the semiconductor die and has a top surface and side walls; a second dielectric layer, the second dielectric layer covers the The top surface and the side wall of the first dielectric layer; a second mask layer, the second mask layer is disposed on the side wall of the first dielectric layer and the second dielectric layer To cover the sidewalls of the first dielectric layer; redistribution lines, the redistribution lines are disposed between the top surface of the first dielectric layer and the second dielectric layer And through the first opening through the first dielectric layer is electrically connected to the semiconductor die; and an external connector, the external connector is provided on the second dielectric layer, and A second opening passing through the second dielectric layer is electrically connected to the redistribution line. 根據請求項1所述的晶圓級封裝件，該晶圓級封裝件還包括對準標記，所述對準標記被設置在所述保護晶圓的所述第一表面處。 The wafer-level package according to claim 1, further comprising an alignment mark provided at the first surface of the protection wafer. 根據請求項1所述的晶圓級封裝件，其中，所述第一介電層的所述頂表面是平坦表面。 The wafer-level package of claim 1, wherein the top surface of the first dielectric layer is a flat surface. 根據請求項3所述的晶圓級封裝件，其中，所述第一介電層的所述平坦頂表面被配置為使得光阻圖案能夠形成有精細的節距並且基本上沒有圖案失真。 The wafer-level package according to claim 3, wherein the flat top surface of the first dielectric layer is configured such that a photoresist pattern can be formed with a fine pitch and substantially free of pattern distortion. 根據請求項1所述的晶圓級封裝件，其中，所述第二介電層的所述頂表面是平坦表面。 The wafer-level package of claim 1, wherein the top surface of the second dielectric layer is a flat surface. 根據請求項1所述的晶圓級封裝件，其中，所述第一介電層和所述第二介電層是感光介電層。 The wafer-level package of claim 1, wherein the first dielectric layer and the second dielectric layer are photosensitive dielectric layers. 根據請求項1所述的晶圓級封裝件，其中，所述第二遮罩層延伸至與所述第一遮罩層的部分交疊。 The wafer-level package of claim 1, wherein the second mask layer extends to partially overlap the first mask layer. 根據請求項1所述的晶圓級封裝件，其中，所述第二遮罩層與覆蓋所述保護晶圓的所述第一表面的所述第一遮罩層電連接。 The wafer-level package according to claim 1, wherein the second mask layer is electrically connected to the first mask layer covering the first surface of the protection wafer. 根據請求項1所述的晶圓級封裝件，該晶圓級封裝件還包括：黏合層，所述黏合層位於所述半導體晶粒與所述第一遮罩層之間。 The wafer-level package according to claim 1, further comprising: an adhesive layer, the adhesive layer being located between the semiconductor die and the first mask layer. 一種製造晶圓級封裝件的方法，該方法包括以下步驟：在保護晶圓的第一表面上形成第一遮罩層；在所述第一遮罩層上並排地安裝半導體晶粒；使用層壓製程來將第一感光介電膜附接到所述第一遮罩層和所述半導體晶粒，以形成第一感光介電層；對所述第一感光介電層進行圖案化，以形成使所述半導體晶粒中的每一個的部分暴露的開口部以及使所述第一遮罩層的部分暴露的溝槽；形成覆蓋所述溝槽的側壁的第二遮罩層以及再分配線，所述再分配線被設置在所述第一感光介電層的頂表面上並且穿過所述開口部電連接到所述半導體晶粒；形成覆蓋所述再分配線和所述第二遮罩層的第二感光介電層；以及在所述第二感光介電層上形成外部連接件， 其中，所述外部連接件延伸到所述第二感光介電層中以電連接到所述再分配線。 A method of manufacturing a wafer-level package includes the following steps: forming a first mask layer on a first surface of a protection wafer; mounting semiconductor dies side by side on the first mask layer; using a layer A pressing process to attach the first photosensitive dielectric film to the first mask layer and the semiconductor die to form a first photosensitive dielectric layer; patterning the first photosensitive dielectric layer to Forming an opening that exposes a portion of each of the semiconductor dies and a trench that exposes a portion of the first mask layer; forming a second mask layer covering the sidewall of the trench and subdividing Wiring, the redistribution line is provided on the top surface of the first photosensitive dielectric layer and is electrically connected to the semiconductor die through the opening portion; formed to cover the redistribution line and the second A second photosensitive dielectric layer of the mask layer; and forming an external connector on the second photosensitive dielectric layer, Wherein, the external connector extends into the second photosensitive dielectric layer to be electrically connected to the redistribution line.
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