CN106953302B - Frequency protection circuit - Google Patents
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- CN106953302B CN106953302B CN201710130091.4A CN201710130091A CN106953302B CN 106953302 B CN106953302 B CN 106953302B CN 201710130091 A CN201710130091 A CN 201710130091A CN 106953302 B CN106953302 B CN 106953302B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
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Abstract
The invention belongs to the technical field of inverters, and provides a frequency protection circuit which comprises a primary high-frequency protection circuit, wherein the primary high-frequency protection circuit is connected with a phase-locked plate circuit through a plug terminal row; the high-frequency protection circuit also comprises a secondary high-frequency protection circuit and a low-frequency protection circuit which are connected with the phase-locked board circuit through the plug-in terminal row. The inverter control system is ingenious in concept, and the technical problems that an existing inverter control system in the prior art is poor in safety and high in maintenance and replacement cost are solved.
Description
Technical Field
The invention belongs to the technical field of inverters, and relates to a frequency protection circuit.
Background
The inverter is a device for converting Direct Current (DC) into Alternating Current (AC), consists of an inverter bridge, control logic and a filter circuit, and is widely applied to air conditioners, home theaters, electric grinding wheels, electric tools, computers, televisions and the like. The inverter is generally controlled by a resonant circuit, and operates in a high impedance state near a resonant point, and the resonant current is a safe area for the circuit to operate in the frequency range. When the load changes or the open circuit short circuit or other sudden changes occur, the frequency suddenly changes upwards or downwards, and the resonance current is suddenly increased regardless of the change in any direction, so that the inverter is damaged. The safety of the existing inverter control system is poor, and the maintenance and replacement cost is high.
Disclosure of Invention
The invention provides a frequency protection circuit, which solves the technical problems of poor safety and high maintenance and replacement cost of the existing inverter control system in the prior art.
The technical scheme of the invention is realized as follows:
a frequency protection circuit comprises a circuit input end, a circuit output end and a primary high-frequency protection circuit,
the first-stage high-frequency protection circuit comprises a first frequency divider, wherein the input end of the first frequency divider is connected with the input end of the circuit, the output end of the first frequency divider is connected with one input end of a second NOR gate and the input end of a second bi-stable trigger, the output end of the second bi-stable trigger is connected with the other input end of the second NOR gate, and the output end of the second NOR gate is connected with the output end of the circuit.
As a further technical scheme, the second bistable trigger is connected with a power supply through a first frequency modulation circuit,
the first frequency modulation circuit comprises a second potentiometer, one end of the second potentiometer is connected with the power supply after being connected with the first resistor in series, the other end of the second potentiometer is connected with the second capacitor and the second bistable trigger, and the other end of the second capacitor is connected with the ground.
As a further technical proposal, the device also comprises a secondary high-frequency protection circuit,
the two-stage high-frequency protection circuit comprises a third NOR gate, two input ends of the third NOR gate are respectively connected with the input end of the first frequency divider and the first bistable trigger, the output ends of the third NOR gate are connected with the second frequency divider and the circuit output end, and the second frequency divider is connected with the circuit output end.
As a further technical scheme, the secondary high-frequency protection circuit is connected with a power supply through a second frequency modulation circuit,
the second frequency modulation circuit comprises a fifth resistor and a sixth resistor which are connected in parallel, one end of the fifth resistor and one end of the sixth resistor are connected with the power supply after the fifth resistor and the sixth resistor are connected in parallel, the other end of the second resistor is connected with the first capacitor and the first bistable trigger, and the first capacitor is connected with the ground.
As a further technical solution, a fourth diode is disposed between the second frequency divider and the circuit output terminal.
As a further technical solution, the first frequency divider is connected to a power supply through a third resistor.
As a further technical solution, the first frequency divider is connected to the second frequency divider and the input end of the third nor gate through a first diode and a second diode, respectively.
As a further technical proposal, the device also comprises a low-frequency protection circuit,
the low-frequency protection circuit comprises a double-D trigger, a first NAND gate and an adjusting circuit which are sequentially connected, the adjusting circuit comprises a charging circuit and a discharging circuit which are mutually connected in parallel, the charging circuit comprises a charging diode, the discharging circuit comprises a first potentiometer and a seventh resistor which are mutually connected in series, the adjusting circuit is connected with the ground through an eighth capacitor and is connected with the output end of the circuit through a second NAND gate, and the double-D trigger is connected with the input end of the circuit.
As a further technical solution, a third diode and a sixth diode are respectively arranged between the second nor gate and the second nand gate and the circuit output end.
The invention has the following using principle and beneficial effects:
1. the frequency protection circuit product board is a frequency protection board, and the frequency protection board is arranged on a phase locking board of a mother board through a plug terminal row J1. The frequency protection circuit is internally divided into a high frequency part and a low frequency part for processing just by acquiring the resonance frequency, and the upper limit of the frequency (F) is adjusted by a potentiometermax) And lower frequency limit (F)min) When the frequency exceeds the upper limit or the lower limit, a high level is output to trigger the protection circuit, so that the safety of the equipment is ensured. During the operation, equipment operating signal passes through in the plug terminal row J1 inputs the frequency protection circuit, and later the high frequency carries out analysis feedback through high frequency protection circuit, and the low frequency carries out analysis feedback through low frequency protection circuit, and wherein plug terminal row J1 gathers the input frequency square wave signal of 6 feet, and high frequency protection signal divide into two the tunnel, including one-level high frequency protection circuit and second grade high frequency protection circuit, has dual protection function.
Primary high-frequency protection: an input signal transmitted by the plug terminal row J1 is subjected to frequency division by the first frequency divider U3 and then is transmitted to the 12 pin A input end of the second bistable flip-flop U2B to be used as a rising edge trigger signal, wherein the second potentiometer WR2 is used for 14 pin stable RC time adjustment of the U2 chip, and the width of a comparison pulse during high-frequency protection can be determined by adjusting the resistance value of the second potentiometer WR2 during work; the pin 9 of the second bi-stable state flip-flop U2B is an inverting output terminal, the output signal and the frequency-divided frequency signal are sent to the second nor gate U1B logic circuit for comparison, if the frequency exceeds the set upper limit, the low level appears in the pins 5 and 6 of the second nor gate U1B, at this time, the pin 4 outputs a high level alarm signal, and the protection signal is output to the pin 10 of the plug terminal row J1 after passing through the third diode D3. Wherein, second potentiometre WR2 is the high frequency protection potentiometre, can set for the frequency upper limit value through adjusting this potentiometre, and this setting has effectively guaranteed the width and the adjustability of circuit application scope, and the user demand that satisfies different users that can be better sets up scientifically, rationally.
Secondary high-frequency protection: the second-stage protection function is started when the frequency of the input signal transmitted by the plug terminal row J1 is higher than the frequency value of the first-stage high-frequency protection (namely, the frequency of phase-locking failure is raised to the highest frequency). The input signal is directly input to the 4-pin A input end of the first bistable flip-flop U2A without frequency division, the 2-pin is a stable RC fixed value and is output through the 7-pin inverted output end, the output signal is compared with the signal input to the 6-pin of the plug terminal row J1 through the third NOR gate U1C logic circuit, if the frequency exceeds the set highest frequency value, the 10-pin of the third NOR gate U1C sends out high level, the direct output is selected through the connection bit number of the terminal row J2 and J3 or the alarm signal is output after the frequency division is counted by the second frequency divider U4, and the alarm signal is output to the 10-pin of the plug terminal row J1 through the fourth diode D4. The number of the terminal row J2 and J3 is selected according to the power and frequency of the device. When the frequency is high, the signal is transmitted by the second frequency divider U4 by adopting a counting frequency division method, and when the frequency is low, the signal is directly transmitted without the second frequency divider U4, so that the safety and the stability of the equipment in the using process are effectively ensured by the arrangement. The secondary high-frequency protection is frequency limit protection and is a fixed value.
Low-frequency protection: the voltage is divided by two by the dual D flip-flop U5 and then sent to the first nand gate U6A for inversion processing, the processed high level charges the eighth capacitor C8 through the charging diode D5, when the output of pin 3 of the first nand gate U6A is low, the charge of the eighth capacitor C8 is discharged through the first potentiometer WR1 and the seventh resistor R7, when the frequency is too low to maintain the threshold voltage of pin 5 and pin 6 of the second nand gate U6B, pin 4 of the second nand gate U6B outputs high level, and the high level signal is output to pin 10 of the plug terminal bank J1 through the sixth diode D6. Wherein, first potentiometre WR1 is the low frequency protection potentiometre, can set for the frequency lower limit value through adjusting this potentiometre, and this setting has further guaranteed the width and the adjustability of circuit application scope, can be better satisfy different users' user demand, set up scientifically, rationally.
The inverter is provided with low-frequency protection and double high-frequency protection, so that the inverter is safer and more reliable in the use process, meanwhile, diodes with a one-way transmission function are arranged among the 4 pins of the second NOR gate U1B, the 4 pins of the second NAND gate U6B, the terminal row J3 and the 10 pins of the plug-in terminal row J1 in the circuit, signal interference among different electric elements in the transmission process is effectively avoided, the possibility that the high level output by a certain electric element (the second NOR gate U1B or the second NAND gate U6B or the terminal row J3) is pulled down by other point positions is effectively avoided, the accuracy and the stability of the working state of the circuit are ensured, the circuit connection relation is reasonable, the layout is ingenious and concise, the circuit reaction speed is high, and the setting is scientific and reasonable.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic structural diagram of a phase-locked plate of a mother board according to the present invention;
in the figure: 1-a primary high-frequency protection circuit, 2-a secondary high-frequency protection circuit, 3-a low-frequency protection circuit, 4-a frequency protection board and 5-a mother board phase-locking board.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in FIGS. 1-2, a frequency protection circuit of the present invention comprises a circuit input terminal, a circuit output terminal, a first-stage high-frequency protection circuit 1,
the primary high-frequency protection circuit 1 comprises a first frequency divider U3, wherein the input end of the first frequency divider U3 is connected with the input end of the circuit, the output end of the first frequency divider U3 is connected with one input end of a second NOR gate U1B and the input end of a second bistable flip-flop U2B, the output end of the second bistable flip-flop U2B is connected with the other input end of a second NOR gate U1B, and the output end of a second NOR gate U1B is connected with the output end of the circuit.
Further, the second bistable trigger U2B is connected with the power supply through the first frequency modulation circuit,
the first frequency modulation circuit comprises a second potentiometer WR2, one end of the second potentiometer WR2 is connected with the power supply after being connected with the first resistor R1 in series, the other end of the second potentiometer WR2 is connected with a second capacitor C2 and a second bistable trigger U2B, and the other end of the second capacitor C2 is connected with the ground.
Further, the device also comprises a secondary high-frequency protection circuit 2,
the two-stage high-frequency protection circuit 2 comprises a third NOR gate U1C, two input ends of the third NOR gate U1C are respectively connected with an input end of a first frequency divider U3 and a first bistable flip-flop U2A, an output end of the third NOR gate U1C is connected with a second frequency divider U4 and a circuit output end, and a second frequency divider U4 is connected with the circuit output end.
Furthermore, the secondary high-frequency protection circuit 2 is connected with a power supply through a second frequency modulation circuit,
the second frequency modulation circuit comprises a fifth resistor R5 and a sixth resistor R6 which are connected in parallel, one end of the second frequency modulation circuit is connected with a power supply after the second frequency modulation circuit and the sixth resistor R6 are connected in parallel, the other end of the second frequency modulation circuit is connected with a first capacitor C1 and a first bistable trigger U2A, and the first capacitor C1 is connected with the ground.
Further, a fourth diode D4 is provided between the second frequency divider U4 and the circuit output terminal.
Further, the first frequency divider U3 is connected to the power supply through a third resistor R3.
Further, the first frequency divider U3 is connected to the input terminals of the second frequency divider U4 and the third nor gate U1C through a first diode D1 and a second diode D2, respectively.
Further, the low-frequency protection circuit 3 is also included,
the low-frequency protection circuit 3 comprises double D triggers U5, a first NAND gate U6A and a regulating circuit which are connected in sequence, the regulating circuit comprises a charging circuit and a discharging circuit which are connected in parallel, the charging circuit comprises a charging diode D5, the discharging circuit comprises a first potentiometer WR1 and a seventh resistor R7 which are connected in series, the regulating circuit is connected with the ground through an eighth capacitor C8 and connected with the circuit output end through a second NAND gate U6B, and the double D triggers U5 are connected with the circuit input end.
Further, a third diode D3 and a sixth diode D6 are respectively arranged between the second nor gate U1B, the second nand gate U6B and the circuit output end.
Further, the first bistable flip-flop U2A and the second bistable flip-flop U2B are disposed on the same flip-flop chip, the type of the flip-flop chip is CD4528,
the second nor gate U1B and the third nor gate U1C are provided on the same nor gate chip, the nor gate chip being of the type CD4001,
the first frequency divider U3 and the second frequency divider U4 are both CD4020,
the first NAND gate U6A and the second NAND gate U6B are arranged on the same NAND gate chip, and the model of the NAND gate chip is CD 4011.
The frequency protection circuit product board is a frequency protection board 4, the frequency protection board is installed on the motherboard phase-locking board 5 through a plug terminal row J1, wherein a circuit input end (6 pins collected by the plug terminal row J1) and a circuit output end (10 pins collected by the plug terminal row J1) are respectively connected with a frequency output end of a phase-locking circuit on the motherboard phase-locking board 5 and a frequency input end of a protection circuit. The frequency protection circuit is internally divided into a high-frequency part and a low-frequency part by acquiring the resonant frequencyThe upper frequency limit (F) is adjusted by a potentiometermax) And lower frequency limit (F)min) When the frequency exceeds the upper limit or the lower limit, a high level is output to trigger the protection circuit, so that the safety of the equipment is ensured. During the operation, equipment operating signal passes through in the plug terminal row J1 inputs the frequency protection circuit, and later the high frequency carries out analysis feedback through high frequency protection circuit, and the low frequency carries out analysis feedback through low frequency protection circuit, and wherein plug terminal row J1 gathers the input frequency square wave signal of 6 feet, and high frequency protection signal divide into two the tunnel, including one-level high frequency protection circuit and second grade high frequency protection circuit, has dual protection function.
Primary high-frequency protection: an input signal transmitted by the plug terminal row J1 is subjected to frequency division by the first frequency divider U3 and then is transmitted to the 12 pin A input end of the second bistable flip-flop U2B to be used as a rising edge trigger signal, wherein the second potentiometer WR2 is used for 14 pin stable RC time adjustment of the U2 chip, and the width of a comparison pulse during high-frequency protection can be determined by adjusting the resistance value of the second potentiometer WR2 during work; the pin 9 of the second bi-stable state flip-flop U2B is an inverting output terminal, the output signal and the frequency-divided frequency signal are sent to the second nor gate U1B logic circuit for comparison, if the frequency exceeds the set upper limit, the low level appears at the pins 5 and 6 of the second nor gate U1B, at this time, the pin 4 outputs a high level alarm signal, the signal passes through the third diode D3 and then outputs a protection signal to the pin 10 of the plug terminal row J1, and the phase-locked board 5 receives the protection signal and then sends out the alarm signal. Wherein, second potentiometre WR2 is the high frequency protection potentiometre, can set for the frequency upper limit value through adjusting this potentiometre, and this setting has effectively guaranteed the width and the adjustability of circuit application scope, and the user demand that satisfies different users that can be better sets up scientifically, rationally.
Secondary high-frequency protection: the second-stage protection function is started when the frequency of the input signal transmitted by the plug terminal row J1 is higher than the frequency value of the first-stage high-frequency protection (namely, the frequency of phase-locking failure is raised to the highest frequency). The input signal is directly input to the 4-pin A input end of the first bistable trigger U2A without frequency division, the 2-pin is a stable RC fixed value and is output through the 7-pin inverted output end, the output signal is compared with the signal input to the 6-pin of the plug terminal row J1 through the third NOR gate U1C logic circuit, if the frequency exceeds the set highest frequency value, the 10-pin of the third NOR gate U1C sends out high level, the terminal row J2 and J3 are connected with bit numbers to select direct output or output an alarm signal after the frequency division is counted by the second frequency divider U4, the alarm signal is output to the 10-pin of the plug terminal row J1 through the fourth diode D4, and the phase-lock plate 5 receives the alarm signal and controls the relevant alarm component to work. The number of the terminal row J2 and J3 is selected according to the power and frequency of the device. When the frequency is high, the signal is transmitted by the second frequency divider U4 by adopting a counting frequency division method, and when the frequency is low, the signal is directly transmitted without the second frequency divider U4, so that the safety and the stability of the equipment in the using process are effectively ensured by the arrangement. The secondary high-frequency protection is frequency limit protection and is a fixed value.
Low-frequency protection: the frequency of the double-D trigger U5 is divided by two and then is sent to the first NAND gate U6A for inversion processing, the processed high level charges the eighth capacitor C8 through the charging diode D5, when the output of the pin 3 of the first NAND gate U6A is low level, the charge of the eighth capacitor C8 is discharged through the first potentiometer WR1 and the seventh resistor R7, when the frequency is too low to maintain the threshold voltage of the pin 5 and the pin 6 of the second NAND gate U6B, the pin 4 of the second NAND gate U6B outputs high level, the high level signal is output to the pin 10 of the plug-in terminal row J1 through the sixth diode D6, and the phase-locked panel 5 sends out an alarm signal after receiving the protection signal. Wherein, first potentiometre WR1 is the low frequency protection potentiometre, can set for the frequency lower limit value through adjusting this potentiometre, and this setting has further guaranteed the width and the adjustability of circuit application scope, can be better satisfy different users' user demand, set up scientifically, rationally.
The invention is provided with a primary high-frequency protection circuit, a secondary high-frequency protection circuit and a low-frequency protection circuit which are parallel, so that the frequency signal acquired by the inverter is limited within a safety zone (plus or minus 10%) after being processed and compared by the circuits, a high-level alarm signal is sent out immediately once the frequency signal exceeds the safety zone, and the phase-locked plate 5 timely adjusts the working state of related parts to process a power supply after receiving the alarm signal. The 4 pins of the second NOR gate U1B, the 4 pins of the second NAND gate U6B, the 10 pins of the terminal row J3 and the plug-in terminal row J1 are all provided with diodes with a one-way transmission function, signal interference among different electrical elements in the transmission process is effectively avoided, the possibility that the high level output by a certain electrical element (the second NOR gate U1B or the second NAND gate U6B or the terminal row J3) is pulled down by other point positions is effectively avoided, the accuracy and the stability of the working state of the circuit are guaranteed, the circuit connection relation is reasonable, the layout is ingenious and concise, the circuit reaction speed is high, and the setting is scientific and reasonable.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. A frequency protection circuit is characterized by comprising a circuit input end, a circuit output end and a primary high-frequency protection circuit (1),
the one-stage high-frequency protection circuit (1) comprises a first frequency divider (U3), wherein the input end of the first frequency divider (U3) is connected with the input end of the circuit, the output end of the first frequency divider is connected with one input end of a second NOR gate (U1B) and the input end of a second bistable flip-flop (U2B), the output end of the second bistable flip-flop (U2B) is connected with the other input end of the second NOR gate (U1B), the output end of the second NOR gate (U1B) is connected with the output end of the circuit,
the low-frequency protection circuit (3) comprises a double-D trigger (U5), a first NAND gate (U6A) and an adjusting circuit which are connected in sequence, wherein the adjusting circuit comprises a charging circuit and a discharging circuit which are connected in parallel, the charging circuit comprises a charging diode (D5), the discharging circuit comprises a first potentiometer (WR1) and a seventh resistor (R7) which are connected in series, the adjusting circuit is connected with the ground through an eighth capacitor (C8) and is connected with the circuit output end through a second NAND gate (U6B), and the double-D trigger (U5) is connected with the circuit input end,
still include second grade high frequency protection circuit (2), second grade high frequency protection circuit (2) include third NOR gate (U1C), two inputs of third NOR gate (U1C) respectively with the input and the first bistable flip-flop (U2A) of first frequency divider (U3) are connected, and the output all is connected with second frequency divider (U4) and circuit output, second frequency divider (U4) is connected with the circuit output.
2. A frequency protection circuit according to claim 1, wherein said second bi-stable flip-flop (U2B) is connected to a power supply via a first frequency modulation circuit,
the first frequency modulation circuit comprises a second potentiometer (WR2), one end of the second potentiometer (WR2) is connected with a power supply after being connected with a first resistor (R1) in series, the other end of the second potentiometer (WR2) is connected with a second capacitor (C2) and the second bistable trigger (U2B), and the other end of the second capacitor (C2) is connected with the ground.
3. A frequency protection circuit according to claim 1, characterized in that the secondary high-frequency protection circuit (2) is connected to a power supply via a second frequency modulation circuit,
the second frequency modulation circuit comprises a fifth resistor (R5) and a sixth resistor (R6) which are connected in parallel, one end of the second frequency modulation circuit is connected with a power supply after the second frequency modulation circuit and the sixth resistor are connected in parallel, the other end of the second frequency modulation circuit is connected with a first capacitor (C1) and the first bistable trigger (U2A), and the first capacitor (C1) is connected with the ground.
4. A frequency protection circuit according to claim 1, characterized in that a fourth diode (D4) is arranged between the second frequency divider (U4) and the circuit output.
5. A frequency protection circuit according to claim 1, wherein the first frequency divider (U3) is connected to a power supply via a third resistor (R3).
6. A frequency protection circuit according to claim 1, wherein said first frequency divider (U3) is connected to the inputs of said second frequency divider (U4) and said third nor gate (U1C) via a first diode (D1) and a second diode (D2), respectively.
7. A frequency protection circuit according to claim 1, characterized in that a third diode (D3) and a sixth diode (D6) are provided between the second nor gate (U1B), the second nand gate (U6B) and the circuit output, respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710130091.4A CN106953302B (en) | 2017-03-07 | 2017-03-07 | Frequency protection circuit |
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| CN201710130091.4A CN106953302B (en) | 2017-03-07 | 2017-03-07 | Frequency protection circuit |
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| CN106953302B true CN106953302B (en) | 2021-01-22 |
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