CN103455469B - A kind of method of control processor frequency, Apparatus and system - Google Patents
A kind of method of control processor frequency, Apparatus and system Download PDFInfo
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- CN103455469B CN103455469B CN201210174227.9A CN201210174227A CN103455469B CN 103455469 B CN103455469 B CN 103455469B CN 201210174227 A CN201210174227 A CN 201210174227A CN 103455469 B CN103455469 B CN 103455469B
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Abstract
The embodiment of the invention discloses a kind of method of control processor frequency and device, described method comprises: obtains user and expects the expectation frequency parameter that multiple treater works, and obtains the maximum frequency parameter of described multiple treater permission work; If described expectation frequency parameter is greater than described maximum frequency parameter, then generate the first clocksignal according to described maximum frequency parameter; Described first clocksignal being exported to described treater, controls described treater and be operated in the first frequency corresponding to described first clocksignal, wherein, described first frequency is maximum frequency. The embodiment of the present invention solves in prior art and the frequency of multi-processor in electronic product is controlled, and causes cost to increase, and reduces the technical problem of electronic product extendability.
Description
Technical field
The present invention relates to terminal processing techniques, in particular to method, the Apparatus and system of a kind of control processor frequency.
Background technology
Along with the development of electronic product, high frequency and multi-functional become high-end electronic product two performance index the most important. But in the electronic product market of low and middle-end, still have a large amount of consumer groups, and from the personal demand of this consumer group, it is necessary to reduce the performance of this electronic product, thus meet the demand of this consumer group. Such as, in multinuclear treater (CPU), the treater not used carries out permanent cut out, or the frequency of treater is carried out permanent restriction etc. But the development of the production technology along with treater, a lot of high-quality electronic product " overclocking " can run when improving its frequency multiplication and outer frequency, thus it has been with material benefit to domestic consumer, also give some illegal retailer's opportunities simultaneously, a large amount of treater through Eemark (polishing) floods market, infringement consumer's interests.
To in the research and practice process of prior art, the present inventor finds, in existing implementation, the frequency of multiple treaters of existing high-end electronic product can not be control effectively, can only carry out deleting or lowering frequency, not only increase cost greatly, and also reduce the extendability of electronic product.
Summary of the invention
The embodiment of the present invention provides method, the Apparatus and system of a kind of control processor frequency, to solve in prior art, the frequency of multi-processor in electronic product is controlled, cause cost to increase, and reduce the technical problem of electronic product extendability.
For solving the problem, the embodiment of the present invention provides a kind of method of control processor frequency, and described method comprises:
Obtain user and expect the expectation frequency parameter that multiple treater works, and obtain the maximum frequency parameter of described multiple treater permission work;
If described expectation frequency parameter is greater than described maximum frequency parameter, then generate the first clocksignal according to described maximum frequency parameter;
Described first clocksignal being exported to described treater, controls described treater and be operated in the first frequency corresponding to described first clocksignal, wherein, described first frequency is maximum frequency
The embodiment of the present invention also provides the device of a kind of control processor frequency, comprising:
Acquiring unit, expects, for obtaining user, the expectation frequency parameter that multiple treater works, and obtains the maximum frequency parameter of described multiple treater permission work;
First generation unit, for when described expectation frequency parameter is greater than described maximum frequency parameter, generating the first clocksignal according to described maximum frequency parameter;
First control unit, for described first clocksignal is exported to described treater, is operated in the first frequency corresponding to described first clocksignal to control described treater; Wherein, described first frequency is maximum frequency.
The embodiment of the present invention reoffers a kind for the treatment of system, described system comprises: disposable programmable logic controller, disposable logic array device able to programme, limit are worth storer, expected value storer, frequency templates comparer, phaselocked loop, at least two switching devices frequently, wherein
Described disposable programmable logic controller, the logic array data disposable able to programme expecting programming for obtaining, and described disposable logic array data able to programme are carried out format conversion, and export the logic array data disposable able to programme after conversion to disposable logic array device able to programme;
Described disposable logic array device able to programme, for carrying out programming to receiving the logic array data disposable able to programme after changing, obtain the maximum frequency parameter of multiple treater permission work, and permanent high level signal or low level signal, and to the maximum frequency parameter of multiple treater permission work is sent to limit and is frequently worth storer, and described high level signal or low level signal are exported corresponding switching device;
Described limit is worth storer frequently, for storing the maximum frequency parameter of multiple treater permission work of described disposable logic array device able to programme input, and exports described maximum frequency parameter to frequency templates comparer;
Described expected value storer, for obtaining and store user and expect the expectation frequency parameter that multiple treater works, and export described expectation frequency parameter to frequency templates comparer;
Described frequency templates comparer, for judging whether described expectation frequency parameter is greater than described maximum frequency parameter, if be greater than, then exports described maximum frequency parameter to described phaselocked loop; Otherwise, export described expectation frequency parameter to described phaselocked loop;
Described phaselocked loop, for generating the first clocksignal by the described maximum frequency parameter that described frequency templates comparer inputs; And described first clocksignal is exported to corresponding treater, control described treater and it is operated in the first frequency corresponding to described first clocksignal; Or, the expectation frequency parameter inputted by described frequency templates comparer generates the 2nd clocksignal, and described 2nd clocksignal is exported to corresponding treater, controls described treater and is operated in the 2nd frequency corresponding to described 2nd clocksignal; Wherein, described first frequency is maximum frequency, and described 2nd frequency is for expecting frequency;
Described switching device, is in permanent closing condition for the described high level signal according to the described disposable logic array device a few days able to programme or the low level signal control treater corresponding with described switching device, or opened condition.
As shown from the above technical solution, in the embodiment of the present invention, by comparing the expectation frequency parameter of acquisition and the size of maximum frequency parameter (i.e. limit value frequently), and when described expectation frequency parameter is greater than maximum frequency parameter, generate the clocksignal of respective frequencies according to described maximum frequency parameter, control processor is operated in frequency corresponding to described clocksignal; Thus reach the effect that the frequency to treater limits.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, it is briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
The schema of the method for a kind of control processor frequency that Fig. 1 provides for the embodiment of the present invention;
The schema of the method for another kind of control processor frequency that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the device of a kind of control processor frequency that Fig. 3 provides for the embodiment of the present invention;
2nd structural representation of the device of a kind of control processor frequency that Fig. 4 provides for the embodiment of the present invention;
The structural representation of a kind for the treatment of system that Fig. 5 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete description, it is clear that described embodiment is only the present invention's part embodiment, instead of whole embodiments. Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Referring to Fig. 1, the schema of the method for a kind of control processor frequency that Fig. 1 provides for the embodiment of the present invention, described method comprises:
Step 101: obtain user and expect the expectation frequency parameter that multiple treater works, and obtain the maximum frequency parameter of described multiple treater permission work;
Wherein, described acquisition user expects the expectation frequency parameter that multiple treater works, it is possible to obtain the expectation frequency parameter of described multiple treater work by configuring interface; And store described expectation frequency parameter, as by expectation storer storage etc.
The process of the maximum frequency parameter of described acquisition multiple treater permission work comprises: obtain logic disposable able to programme (such as eFuse etc.) array data corresponding to described predeterminated frequency parameter (the frequency parameter estimated according to the applied environment of product when namely chip design or product are arranged, naturally it is also possible to formulate according to default rule) by technician by total line interface; Described disposable logic array data able to programme are carried out format conversion; Programming form turn after logic array data disposable able to programme, obtain corresponding maximum frequency parameter, it is possible to by limit frequently value latch store described maximum frequency parameter. Certainly, programming form turn after logic array data disposable able to programme, not only can obtain corresponding maximum frequency parameter, it is also possible to obtain permanent high level state or low level state.
Wherein, obtain can being obtained of logic array data disposable able to programme corresponding to described predeterminated frequency parameter by disposable programmable logic controller, then by after inter-process, disposable logic array data able to programme are converted to the data of disposable logic array device interface able to programme, by the disposable logic array data able to programme of disposable logic array device programming able to programme, obtain maximum frequency parameter, and maximum frequency parameter is exported to limit value latch storage frequently, but it is not limited to this, process can also be realized by other similar devices, the present embodiment is not restricted.
Step 102: if described expectation frequency parameter is greater than described maximum frequency parameter, then generate the first clocksignal according to described maximum frequency parameter;
In this embodiment, frequency templates comparer can compare expected value latch the expectation frequency parameter stored and the magnitude relationship limitting the maximum frequency parameter of value latch store frequently; When expectation frequency parameter is greater than maximum frequency parameter (i.e. limit value frequently), then this frequency templates comparer exports maximum frequency parameter to phaselocked loop (PLL, PhaseLockedLoop), otherwise, export and expect that frequency parameter is to PLL. Described PLL is a conventional basic device, after receiving the numerical value (such as maximum frequency parameter or expectation frequency parameter) exported from frequency templates comparer, according to the clocksignal of this numerical generation respective frequencies size. Its concrete generative process, for art technology, has been know technology, has not repeated them here.
Step 103: described first clocksignal is exported to described treater, controls described treater and is operated in the first frequency corresponding to described first clocksignal. Wherein, described first frequency is described maximum frequency.
In this embodiment, the clocksignal generating corresponding frequency size is outputted in treater by PLL, controls described treater and is operated in maximum frequency (i.e. the first frequency) corresponding to described first clocksignal.
In the embodiment of the present invention, by comparing the expectation frequency parameter of acquisition and the size of maximum frequency parameter (i.e. limit value frequently), and when described expectation frequency parameter is greater than maximum frequency parameter, generate the clocksignal of respective frequencies according to described maximum frequency parameter, control processor is operated in frequency corresponding to described clocksignal; Thus reach the effect that the frequency to treater limits.
Also referring to the schema of the method for another kind of control processor frequency that Fig. 2, Fig. 2 provide for the embodiment of the present invention, described method comprises:
Step 201: obtain user and expect the expectation frequency parameter that multiple treater works, and obtain the maximum frequency parameter of described multiple treater permission work;
The acquisition process of this step specifically refers to described in step 101, does not repeat them here.
Step 202: judge whether described expectation frequency parameter is greater than described maximum frequency parameter, if be greater than, performs step 203 and step 204; Otherwise, perform step 205 and step 206;
In this step, can be that frequency templates comparer compares the expectation frequency parameter of acquisition from expected value latch stores and the magnitude relationship of the maximum frequency parameter obtained from limit frequently value latch, such as, if it is desire to frequency corresponding to frequency parameter is 2GHZ, and frequency corresponding to maximum frequency parameter is 1GHZ, the frequency parameter of 1GHZ, after comparing, is sent to PLL by frequency templates comparer.
Step 203: generate the first clocksignal according to described maximum frequency parameter;
In this step, PLL generates the clocksignal of corresponding frequencies size according to this maximum frequency parameter of input, can be that the clock reference source with self compares, then the clocksignal of corresponding frequencies size is generated, its detailed process has been know technology to those skilled in the art, does not repeat them here.
Step 204: described first clocksignal is exported to described treater, controls described treater and is operated in the first frequency corresponding to described first clocksignal;
Step 205: generate the 2nd clocksignal according to described expectation frequency parameter;
This generative process is identical with the principle of the generative process of step 203, specifically refers to above-mentioned, does not repeat them here.
Step 206: described 2nd clocksignal is exported to described treater, controls described treater and is operated in the 2nd frequency corresponding to described 2nd clocksignal. Wherein, described 2nd frequency is described expectation frequency.
In the embodiment of the present invention, by comparing the expectation frequency parameter of acquisition and the size of maximum frequency parameter (i.e. limit value frequently), and when described expectation frequency parameter is greater than maximum frequency parameter, the first clocksignal is generated, and control processor is operated in the first frequency corresponding to described first clocksignal according to described maximum frequency parameter; And when described expectation frequency parameter is less than or equals maximum frequency parameter, generate the 2nd clocksignal according to described expectation frequency parameter, and control processor is operated in the 2nd frequency corresponding to described 2nd clocksignal. Thus reach the effect that the frequency to treater limits.
On the basis of above-described embodiment, described method can further include: during logic array data disposable able to programme after described programming form turns, also obtains multiple permanent high level signal or low level signal; It is in permanent closing condition according to corresponding treater in described high level signal or the low level signal described multiple treater of control, or opened condition; Wherein, described opened condition can comprise: the working order of treater and off working state.
Wherein, disposable logic array device able to programme is when to disposable logic array data programming able to programme, this device inside can only carry out the fuse of a programming, and after programming, the output of this disposable logic array device able to programme will be a permanent high or low level state. It should be noted that, the difference of disposable logic array device able to programme, its capacity is also different, thus output pin quantity is also different.
In the embodiment of the present invention, it is possible to use disposable logical course able to programme realizes needing permanent limit frequently for device (such as treater).
Optionally, for the treater of impermanency closing condition, described method can further include: if receiving the signal of the treater of the closedown impermanency closing condition of software controller input, then the treater controlling corresponding cut out impermanency closing condition is in closing condition; After the treater of described cut out impermanency closing condition is in closing condition, if receiving the start signal of the treater opening described closing condition of software controller input, then the treater controlling closing condition is in opened condition.
Such as, if a treater work for the treatment of state in multiple treaters of impermanency closing condition, and designer expects to close this in running order treater, then designer can be exported by software controller and expect that the signal of treater closedown is to switching device, described switching device, after receiving the signal that described expectation treater cuts out, cuts out this treater, namely allows this be in closing condition, certainly, this closing condition can also be permanent closing condition; Afterwards, if designer expects to open again this treater closed described, then sent the signal expecting that this treater is opened equally to this switching device by software controller, described switching device opens the treater of described cut out, and namely treater is in opened condition.
That is, when disposable logic output signal able to programme makes treater be in reset mode, the just permanent closedown of this treater; Otherwise, for the treater of impermanency closing condition, it is also possible to the control signal exported by software controller, the treater of impermanency closing condition cuts out, and after closedown, it is also possible to open this treater.
For another example, a product support 2 CPU processor, but work as changes in market demand, it is necessary to as long as during the product of a 1 CPU processor, so just do not need from newly developed and production chip, as long as one of them CPU forever being closed by disposable logic able to programme.
Realizing process based on aforesaid method, the embodiment of the present invention also provides the device of a kind of control processor frequency, and as shown in Figure 3, described device comprises the structural representation of its correspondence: acquiring unit 31, the first generation unit 32 and the first control unit 33, wherein,
Described acquiring unit 31, expects, for obtaining user, the expectation frequency parameter that multiple treater works, and obtains the maximum frequency parameter of described multiple treater permission work; Described first generation unit 32, for when described expectation frequency parameter is greater than described maximum frequency parameter, generating the first clocksignal according to described maximum frequency parameter; Described first control unit 33, for described first clocksignal is exported to described treater, is operated in the first frequency (i.e. maximum frequency) corresponding to described first clocksignal to control described treater.
Optionally, described device can further include: the 2nd generation unit and the 2nd control unit, wherein, and described 2nd generation unit, for when described expectation frequency parameter is less than or equals described maximum frequency parameter, generating the 2nd clocksignal according to described expectation frequency parameter; 2nd control unit, for described 2nd clocksignal is exported to described treater, controls described treater and is operated in the 2nd frequency (namely expecting frequency) corresponding to described 2nd clocksignal.
Optionally, the embodiment of the present invention also provides the device of another kind of control processor frequency, the structural representation of its correspondence is as shown in Figure 4, described device comprises: acquiring unit 41, judging unit 42, first generation unit 43 and the first control unit 44, the 2nd generation unit 45 and the 2nd control unit 46, wherein
Described acquiring unit 41, expects, for obtaining user, the expectation frequency parameter that multiple treater works, and obtains the maximum frequency parameter of described multiple treater permission work;
Described judging unit 42, for judging whether the described expectation frequency parameter that acquiring unit 41 obtains is greater than described maximum frequency parameter, and is sent to described first generation unit 43 by the judged result being greater than; The judged result being less than or equal is sent to described 2nd generation unit 45;
Described first generation unit 43, for when receiving described judging unit and send the judged result being greater than, generating the first clocksignal according to described maximum frequency parameter; Described first control unit 44, for described first clocksignal is exported to described treater, is operated in the first frequency corresponding to described first clocksignal to control described treater
Described 2nd generation unit 45, when receiving described judging unit and send the judged result being less than or equaling, generates the 2nd clocksignal according to described expectation frequency parameter; Described 2nd control unit 46, for described 2nd clocksignal is exported to described treater, controls described treater and is operated in the 2nd frequency corresponding to described 2nd clocksignal.
Optionally, described acquiring unit comprises: the first acquiring unit and the 2nd acquiring unit, wherein,
Described first acquiring unit, for obtaining the expectation frequency parameter of described multiple treater work by configuring interface; Described 2nd acquiring unit, for obtaining logic array data disposable able to programme corresponding to described predeterminated frequency parameter by total line interface; Described disposable logic array data able to programme are carried out format conversion; And programming form turn after logic array data disposable able to programme, obtain described multiple treater work maximum frequency parameter.
Wherein, described 2nd acquiring unit comprises: disposable programmable logic controller and disposable logic array device able to programme, wherein, described disposable programmable logic controller, for obtaining logic array data disposable able to programme corresponding to described predeterminated frequency parameter by total line interface; And described disposable logic array data able to programme are converted to the form of disposable logic array device identification able to programme; Described disposable logic array device able to programme, the logic array data disposable able to programme after changing for programming, and export the maximum frequency parameter of described multiple treater work.
Optionally, described disposable logic array device able to programme programming change after logic array data disposable able to programme time, also export multiple permanent high level signal or low level signal; Described device can further include: the 3rd acquiring unit and the 3rd control unit, wherein,
Described 3rd acquiring unit, for receiving multiple permanent high level signal or the low level signal that described disposable logic array device able to programme exports; 3rd control unit, for being in permanent closing condition according to corresponding treater in described high level signal or the low level signal described multiple treater of control, or opened condition.
Optionally, for the treater of impermanency closing condition, described device can further include: also comprises: the first reception unit, 4th control unit, 2nd reception unit and the 5th control unit, wherein, described first reception unit, for receiving the signal of the treater of the closedown impermanency closing condition of software controller input; Described 4th control unit, for the signal of the treater according to described closedown impermanency closing condition, closes the treater of described impermanency closing condition; Described 2nd reception unit, for, after the treater closing impermanency closing condition, receiving the signal of the treater of the open and close state of software controller input; Described 5th control unit, for the signal of the treater according to described open and close state, opens the treater of described closing condition.
In this embodiment, described first reception unit and the 2nd reception unit can integrate, it is also possible to independent deployment, the present embodiment is not restricted.
In the embodiment of the present invention, by disposable programmable logic technology, to forever not needing the device of work to carry out rigid closedown; The device needing permanent frequency to limit is carried out frequency limitation.
Also refer to Fig. 5, for a kind for the treatment of system that the embodiment of the present invention provides, its structural representation is as shown in Figure 5, described system comprises: disposable programmable logic controller 51, disposable logic array device 52 able to programme, limit frequency value storer 53, expected value storer 54, frequency templates comparer 55, phaselocked loop 56, at least two switching device 57(the present embodiment are for three switching devices), and for CPU0 to CPUn in multiple treater 58, figure. Wherein,
Described disposable programmable logic controller 51, the logic array data disposable able to programme of programming are preset for obtaining (obtaining as by total line interface), and described disposable logic array data able to programme are carried out format conversion, and export the logic array data disposable able to programme after conversion to disposable logic array device able to programme;
That is, this disposable programmable logic controller can obtain logic disposable able to programme (such as eFuse) array data presetting programming by total line interface, and by after inter-process, convert the data of disposable logic array device interface able to programme to, so that the disposable disposable logic array able to programme of logic array device programming able to programme.
Described disposable logic array device 52 able to programme, for carrying out programming to receiving the logic array data disposable able to programme after changing, obtain the maximum frequency parameter of multiple treater permission work, and permanent high level signal or low level signal, and to the maximum frequency parameter of multiple treater permission work is sent to limit and is frequently worth storer, and described high level signal or low level signal are exported corresponding switching device;
Such as, eFuse device, this eFuse device inside contains the fuse that can only carry out a programming, and after carrying out programming, the output of this eFuse device will be a permanent high level signal or low level signal. It should be noted that, the difference of eFuse device, its capacity is also different, thus output pin quantity is also different.
Described limit is value storer 53 frequently, for storing the maximum frequency parameter of multiple treater permission work of described disposable logic array device able to programme input, and exports described maximum frequency parameter to frequency templates comparer;
That is, the maximum frequency value parameter allowing treater work is latched by this limit frequency value storer, and after eFuse programming success, the numerical value in this limit frequency value storer is exactly a fixed value.
Described expected value storer 54, and stores user for obtaining (obtaining as by configuration interface) and expects the expectation frequency parameter that multiple treater works, and export described expectation frequency parameter to frequency templates comparer;
The numerical value of this expected value storer can not be modified by user, but product is arranged by chip personnel before completing. When wishing that device (such as treater) is operated in a certain frequency (but the operating frequency that this value is also not necessarily final, need to compare with limit frequency value), just need to configure parameter accurately to phase-locked loop pll, this expected value deposits device for latching this parameter value, and this parameter value is by configuring interface input.
Described frequency templates comparer 55, for judging whether described expectation frequency parameter is greater than described maximum frequency parameter, if be greater than, then exports described maximum frequency parameter to described phaselocked loop; Otherwise, export described expectation frequency parameter to described phaselocked loop;
Described phaselocked loop 56, for generating the first clocksignal corresponding to the first frequency by the described maximum frequency parameter that described frequency templates comparer inputs; And described first clocksignal is exported to corresponding treater, control described treater and it is operated in the first frequency corresponding to described first clocksignal; Or, the expectation frequency parameter inputted by described frequency templates comparer generates the 2nd clocksignal corresponding to the 2nd frequency, and described 2nd clocksignal is exported to corresponding treater, control described treater and it is operated in the 2nd frequency corresponding to described 2nd clocksignal;
Described switching device 57, is in permanent closing condition for the described high level signal according to the described disposable logic array device a few days able to programme or the low level signal control treater corresponding with described switching device, or opened condition.
Optionally, for the treater of impermanency closing condition, also comprising: software controller 59, its structural representation is as shown in Figure 5. Wherein,
Described software controller 59, for obtaining (obtaining as by control interface) and store the parameter expecting that the treater of impermanency closing condition cuts out or opens, and exports signal corresponding for described parameter to described switching device;
Described switching device 57, also for when the signal of the treater of the closedown impermanency closing condition receiving software controller input, the treater controlling the impermanency closing condition corresponding with described switching device is in cut out; And, after the closedown of the treater of impermanency closing condition, if receiving the signal of treater of the open and close state of software controller input, then according to the signal of the treater of described open and close state, open the treater of described closing condition.
As shown from the above technical solution, the object of the embodiment of the present invention has two: 1, control processor carries out permanent rigid limit frequently, specifically comprise: be operated in a certain range of frequency by disposable logic able to programme (such as eFuse) limiting processor, when exterior arrangement has exceeded eFuse range of frequency to the operating frequency of treater, so the present invention understands the maximum value that force processor can only be operated in range of frequency. When exterior arrangement to the operating frequency of treater not more than the range of frequency of eFuse restriction, so treater will be operated in the frequency of actual disposition; 2, control processor carries out the closedown of permanent rigid function, specifically comprise: carry out blowing of fuse by disposable logic able to programme (such as eFuse), the switch of control interiors of products functional unit (such as treater), reach the permanent rigid closedown of this function, otherwise, it is possible to the selection of the open and close of interiors of products function (such as treater) is carried out by software arrangements.
Therefore, in the embodiment of the present invention, it is possible to adopt disposable logic able to programme (such as eFuse) technology, to forever not needing the device (such as treater) of work to carry out rigid closedown; The device (such as treater) needing permanent frequency to limit can also be carried out frequency limitation.
For the ease of understanding, carry out lock core and limit frequently illustrating for the purpose processor of answering to multinuclear and high frequency below.
Such as product is the highest can support 16 CPU processor, and operating frequency is the highest can reach 2GHz. Now need the CPU to a wherein part to carry out permanent closedown, make them not work, and need the CPU maximum operation frequency of all working is reduced to 1GHz. This just can utilize the described technical scheme of this invention, and by the numerical value programming of 1GHz in eFuse, thus the output pin making eFuse is correct. So, the numerical value of limit frequently value latch will make the clock signal of PLL be 1GHz, thus reaches the effect of limit frequency. If it is desire to a certain the CPU closed, the system selector switch of its correspondence due to eFuse output pin invalid, and by software controller export close this CPU control signal to system selector switch (i.e. switching device), system selector switch makes CPU be in reset mode always, this CPU stops work, certainly, after this CPU stops work, can also by part controller export open this CPU control signal to this system selector switch, the CPU of this stopping process being opened by system selector switch.
It should be noted that, herein, the such as relational terms of first and second grades and so on is only used for separating an entity or operation with another entity or operational zone, and not necessarily requires or imply to there is any this kind of actual relation or sequentially between these entities or operation. And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, so that comprise the process of a series of key element, method, article or equipment not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise the key element intrinsic for this kind of process, method, article or equipment. When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Through the above description of the embodiments, the technician of this area can be well understood to the present invention and can realize by the mode that software adds required general hardware platform, naturally it is also possible to by hardware, but in a lot of situation, the former is better enforcement mode. Based on such understanding, the technical scheme of the present invention in essence or says that part prior art contributed can embody with the form of software product, this computer software product can be stored in storage media, such as ROM/RAM, magnetic disc, CD etc., comprise some instructions with so that a computer equipment (can be Personal Computer, server, or the network equipment etc.) perform the method described in some part of each embodiment of the present invention or embodiment.
The above is only the preferred embodiment of the present invention; it is noted that for those skilled in the art, under the premise without departing from the principles of the invention; can also making some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (11)
1. the method for a control processor frequency, it is characterised in that, comprising:
Obtain user and expect the expectation frequency parameter that multiple treater works, and obtain the maximum frequency parameter of described multiple treater permission work;
If described expectation frequency parameter is greater than described maximum frequency parameter, then generate the first clocksignal according to described maximum frequency parameter;
Described first clocksignal being exported to described treater, controls described treater and be operated in the first frequency corresponding to described first clocksignal, wherein, described first frequency is maximum frequency;
Wherein, the maximum frequency parameter of the multiple treater permission work of described acquisition, specifically comprises: obtain logic array data disposable able to programme corresponding to predeterminated frequency parameter by total line interface; Described disposable logic array data able to programme are carried out format conversion; Programming form turn after logic array data disposable able to programme, obtain corresponding maximum frequency parameter;
Further, during logic array data disposable able to programme after described programming form turns, multiple permanent high level signal or low level signal is also obtained; According to the permanent closing condition that corresponding treater in described high level signal or the low level signal described multiple treater of control is in, or opened condition.
2. method according to claim 1, it is characterised in that, also comprise:
If described expectation frequency parameter is less than or equals described maximum frequency parameter, then generate the 2nd clocksignal corresponding to the 2nd frequency according to described expectation frequency parameter;
Described 2nd clocksignal being exported to described treater, controls described treater and be operated in the 2nd frequency corresponding to described 2nd clocksignal, wherein, described 2nd frequency is for expecting frequency.
3. method according to claim 2, it is characterised in that, also comprise:
Judging whether described expectation frequency parameter is greater than described maximum frequency parameter, if be greater than, performing the described step generating the first clocksignal according to maximum frequency parameter; Otherwise, perform described according to expecting that frequency parameter generates the step of the 2nd clocksignal.
4. method according to claim 1, it is characterised in that, for the treater of impermanency closing condition, described method also comprises:
If receiving the signal of the treater of the closedown impermanency closing condition of software controller input, then the treater controlling corresponding cut out impermanency closing condition is in closing condition;
After the treater of described cut out impermanency closing condition is in closing condition, if receiving the start signal of the treater opening described closing condition of software controller input, then the treater controlling closing condition is in opened condition.
5. the device of a control processor frequency, it is characterised in that, comprising:
Acquiring unit, expects, for obtaining user, the expectation frequency parameter that multiple treater works, and obtains the maximum frequency parameter of described multiple treater permission work;
First generation unit, for when described expectation frequency parameter is greater than described maximum frequency parameter, generating the first clocksignal according to described maximum frequency parameter;
First control unit, for described first clocksignal is exported to described treater, is operated in the first frequency corresponding to described first clocksignal to control described treater; Wherein, described first frequency is maximum frequency;
Wherein, described acquiring unit comprises:
2nd acquiring unit, for obtaining logic array data disposable able to programme corresponding to predeterminated frequency parameter by total line interface; Described disposable logic array data able to programme are carried out format conversion; And programming form turn after logic array data disposable able to programme, obtain described multiple treater work maximum frequency parameter;
Described disposable logic array device able to programme programming change after logic array data disposable able to programme time, also export multiple permanent high level signal or low level signal; Also comprise:
3rd acquiring unit, for receiving multiple permanent high level signal or the low level signal that described disposable logic array device able to programme exports;
3rd control unit, for being in permanent closing condition according to corresponding treater in described high level signal or the low level signal described multiple treater of control, or opened condition.
6. device according to claim 5, it is characterised in that, also comprise:
2nd generation unit, for when described expectation frequency parameter is less than or equals described maximum frequency parameter, generating the 2nd clocksignal according to described expectation frequency parameter;
2nd control unit, for described 2nd clocksignal is exported to described treater, controls described treater and is operated in the 2nd frequency corresponding to described 2nd clocksignal; Wherein, described 2nd frequency is for expecting frequency.
7. device according to claim 6, it is characterised in that, also comprise:
Judging unit, for judging whether described expectation frequency parameter is greater than described maximum frequency parameter, and is sent to described first generation unit by the judged result being greater than; The judged result being less than or equal is sent to described 2nd generation unit;
Described first generation unit, also for when the judged result being greater than described in receiving, generating described first clocksignal according to described maximum frequency parameter;
Described 2nd generation unit, also for when the judged result being less than described in receiving or equal, generating described 2nd clocksignal according to described expectation frequency parameter.
8. device according to claim 5, it is characterised in that, described 2nd acquiring unit comprises:
Disposable programmable logic controller, for obtaining logic array data disposable able to programme corresponding to described predeterminated frequency parameter by total line interface; And described disposable logic array data able to programme are converted to the form of disposable logic array device identification able to programme;
Disposable logic array device able to programme, the logic array data disposable able to programme after changing for programming, and export the maximum frequency parameter of described multiple treater work.
9. device according to claim 5, it is characterised in that, for the treater of impermanency closing condition, also comprise:
First reception unit, for receiving the signal of the treater of the closedown impermanency closing condition of software controller input;
4th control unit, for the signal of the treater according to described closedown impermanency closing condition, closes the treater of described impermanency closing condition;
2nd reception unit, for, after the treater closing impermanency closing condition, receiving the signal of the treater of the open and close state of software controller input;
5th control unit, for the signal of the treater according to described open and close state, opens the treater of described closing condition.
10. a treatment system, it is characterised in that, comprising: disposable programmable logic controller, disposable logic array device able to programme, limit are worth storer, expected value storer, frequency templates comparer, phaselocked loop, at least two switching devices frequently, wherein,
Described disposable programmable logic controller, the logic array data disposable able to programme expecting programming for obtaining, and described disposable logic array data able to programme are carried out format conversion, and export the logic array data disposable able to programme after conversion to disposable logic array device able to programme;
Described disposable logic array device able to programme, for carrying out programming to receiving the logic array data disposable able to programme after changing, obtain the maximum frequency parameter of multiple treater permission work, and permanent high level signal or low level signal, and to the maximum frequency parameter of multiple treater permission work is sent to limit and is frequently worth storer, and described high level signal or low level signal are exported corresponding switching device;
Described limit is worth storer frequently, for storing the maximum frequency parameter of multiple treater permission work of described disposable logic array device able to programme input, and exports described maximum frequency parameter to frequency templates comparer;
Described expected value storer, for obtaining and store user and expect the expectation frequency parameter that multiple treater works, and export described expectation frequency parameter to frequency templates comparer;
Described frequency templates comparer, for judging whether described expectation frequency parameter is greater than described maximum frequency parameter, if be greater than, then exports described maximum frequency parameter to described phaselocked loop; Otherwise, export described expectation frequency parameter to described phaselocked loop;
Described phaselocked loop, for generating the first clocksignal by the described maximum frequency parameter that described frequency templates comparer inputs; And described first clocksignal is exported to corresponding treater, control described treater and it is operated in the first frequency corresponding to described first clocksignal; Or, the expectation frequency parameter inputted by described frequency templates comparer generates the 2nd clocksignal, and described 2nd clocksignal is exported to corresponding treater, controls described treater and is operated in the 2nd frequency corresponding to described 2nd clocksignal; Wherein, described first frequency is maximum frequency, and described 2nd frequency is for expecting frequency;
Described switching device, is in permanent closing condition for the described high level signal according to the described disposable logic array device a few days able to programme or the low level signal control treater corresponding with described switching device, or opened condition.
11. systems according to claim 10, it is characterised in that, for the treater of impermanency closing condition, also comprise:
Software controller, for obtaining and store the parameter expecting that the treater of impermanency closing condition cuts out or opens, and export signal corresponding for described parameter to described switching device;
Described switching device, also for when the signal of the treater of the closedown impermanency closing condition receiving software controller input, the treater controlling the impermanency closing condition corresponding with described switching device is in closing condition; And, after the closedown of the treater of impermanency closing condition, if receiving the signal of treater of the open and close state of software controller input, then according to the signal of the treater of described open and close state, open the treater of described closing condition.
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|---|---|---|---|---|
| US6438697B2 (en) * | 1991-12-17 | 2002-08-20 | Compaq Information Technologies Group, L.P. | Demand-based processor clock frequency switching |
| CN1737772A (en) * | 2004-08-04 | 2006-02-22 | 惠普开发有限公司 | Systems and methods to determine processor utilization |
| CN1791017A (en) * | 2004-12-16 | 2006-06-21 | 国际商业机器公司 | Method and system of power management of multi-processor servers |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438697B2 (en) * | 1991-12-17 | 2002-08-20 | Compaq Information Technologies Group, L.P. | Demand-based processor clock frequency switching |
| CN1737772A (en) * | 2004-08-04 | 2006-02-22 | 惠普开发有限公司 | Systems and methods to determine processor utilization |
| CN1791017A (en) * | 2004-12-16 | 2006-06-21 | 国际商业机器公司 | Method and system of power management of multi-processor servers |
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