CN106953302A - A kind of frequency protection circuit - Google Patents
A kind of frequency protection circuit Download PDFInfo
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- CN106953302A CN106953302A CN201710130091.4A CN201710130091A CN106953302A CN 106953302 A CN106953302 A CN 106953302A CN 201710130091 A CN201710130091 A CN 201710130091A CN 106953302 A CN106953302 A CN 106953302A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention belongs to inverter technology field; a kind of frequency protection circuit proposed; including one-level high frequency protecting circuit; one-level high frequency protecting circuit is arranged by inserting terminal and is connected with lock phase-plate circuit; one-level high frequency protecting circuit includes the first frequency divider; first fraction frequency device input end is connected with inserting terminal row; one input of output end and the second nor gate and the second flip and flop generator input are all connected with; another input is connected second flip and flop generator output end with the second nor gate, and the output end of the second nor gate is connected with inserting terminal row；Also include arranging the two grades of high frequency protecting circuits and low-frequency protection circuit that are connected with lock phase-plate circuit by inserting terminal.Present inventive concept is ingenious, solves that inverter control system security current in the prior art is poor, the high technical problem of maintenance replacement cost.
Description
Technical field
The invention belongs to inverter technology field, it is related to a kind of frequency protection circuit.
Background technology
Inverter is a kind of device that direct current (DC) is converted into alternating current (AC), by inverter bridge, control logic and filter
Wave circuit is constituted, and is widely used in air-conditioning, home theater, electric wheel, electric tool, computer, TV etc..Inverter typically leads to
Cross resonance circuit to control, be high-impedance state when being worked near resonance point, now resonance current minimum is in this frequency range
The place of safety worked for circuit.When load is changed or opened a way under the catastrophes such as short circuit, frequency can be sent out up or down suddenly
Raw mutation, no matter which direction change can all cause resonance current increased dramatically from, causes the damage of inverter.And at present inverse
Become device control system security poor, maintenance replacement cost is high.
The content of the invention
The present invention proposes a kind of frequency protection circuit, solves inverter control system security current in the prior art
Difference, the high technical problem of maintenance replacement cost.
The technical proposal of the invention is realized in this way：
A kind of frequency protection circuit, including circuit input end, circuit output end, one-level high frequency protecting circuit,
One-level high frequency protecting circuit includes the first frequency divider, and first fraction frequency device input end is connected with circuit input end,
One input of output end and the second nor gate and the second flip and flop generator input are all connected with, the second bistable state triggering
Device output end is connected with described another input of second nor gate, and output end and the circuit output end of second nor gate connect
Connect.
As further technical scheme, second flip and flop generator is connected by the first FM circuit with power supply,
First FM circuit include the second potentiometer, described second potentiometer one end connected with first resistor after with electricity
Source is connected, and the other end is all connected with the second electric capacity and second flip and flop generator, and the second electric capacity other end connects with ground
Connect.
As further technical scheme, also including two grades of high frequency protecting circuits,
Two grades of high frequency protecting circuits include the 3rd nor gate, two inputs of the 3rd nor gate respectively with institute
Output end and the connection of the first flip and flop generator of the first frequency divider are stated, output end connects with the second frequency divider and circuit output end
Connect, second frequency divider is connected with circuit output end.
As further technical scheme, two grades of high frequency protecting circuits are connected by the second FM circuit with power supply,
Second FM circuit includes the 5th resistance and the 6th resistance parallel with one another, one end and power supply after both parallel connections
Connection, the other end is all connected with the first electric capacity and first flip and flop generator, and first electric capacity is connected to ground.
As further technical scheme, the 4th diode is provided between second frequency divider and circuit output end.
As further technical scheme, first frequency divider is connected by 3rd resistor with power supply.
As further technical scheme, first frequency divider passes through the first diode, the second diode and institute respectively
State the input connection of the second frequency divider, the 3rd nor gate.
As further technical scheme, also including low-frequency protection circuit,
The low-frequency protection circuit includes the double D trigger being sequentially connected, the first NAND gate, regulation circuit, the regulation
Circuit includes charging circuit and discharge circuit parallel with one another, and the charging circuit includes charging diode, the discharge circuit
Including the first potentiometer and the 7th resistance being serially connected, the regulation circuit is connected to ground by the 8th electric capacity, passes through second
NAND gate is connected with circuit output end, and the double D trigger is connected with circuit input end.
As further technical scheme, divide between second nor gate, second NAND gate and circuit output end
The 3rd diode and the 6th diode are not provided with.
Use principle of the present invention and have the beneficial effect that：
1st, frequency protection circuit production board of the present invention is frequency protection plate, and frequency protection plate is arranged J1 by inserting terminal and installed
On motherboard lock phase-plate.Frequency protection circuit is exactly based on collection resonant frequency, is internally divided at high and low frequency two parts
Reason, upper frequency limit (F is adjusted by potentiometermax) and lower-frequency limit (Fmin) when frequency exceedes the upper limit or lower limit, output is high
Level carrys out trigger protection circuit, so that it is guaranteed that the safety of equipment.During work, equipment working signal is arranged J1 by inserting terminal and inputted
Into frequency protection circuit, high frequency carries out analysis feedback by high frequency protecting circuit afterwards, and low frequency is entered by low-frequency protection circuit
Row analysis feedback, wherein inserting terminal row J1 gather the incoming frequency square-wave signal of 6 pin, and high-frequency protecting signal is divided into two-way, wraps
One-level high frequency protecting circuit and two grades of high frequency protecting circuits are included, with double protection functions.
One-level carrier current protection：The input signal that J1 transmission is come in is arranged through inserting terminal, is sent after being divided through the first frequency divider U3
The 12 pin A inputs to the second flip and flop generator U2B are as rising edge trigger signal, wherein the second potentiometer WR2 is U2 cores
14 pin stable state RC time adjustments of piece, ratio during carrier current protection can be determined during work by adjusting the second potentiometer WR2 resistance
Compared with the width of pulse；Second flip and flop generator U2B 9 pin are reversed-phase output, and this output signal is believed with the frequency after frequency dividing
Number being sent to the second nor gate U1B logic circuits is compared, if frequency exceedes the upper limit of setting, will result in the second nor gate
The 5 of U1B, 6 pin have low level appearance, now 4 pin output high level alarm signal, by arriving inserting terminal after the 3rd diode D3
Arrange J1 10 pin output protection signals.Wherein, the second potentiometer WR2 is carrier current protection potentiometer, can by adjusting this potentiometer
Setpoint frequency higher limit, this setting effectively ensure that the width and adjustability of the circuit scope of application, can better meet not
With the use demand of user, science, rationally is set.
Two grades of carrier current protections：J1, which is arranged, through inserting terminal transmits the frequency input signal come in higher than one-level carrier current protection frequency
The second level defencive function that starts (is locked when mutually unsuccessfully frequency is raised to highest frequency) during value.Input signal is direct without frequency dividing
The first flip and flop generator U2A 4 pin A inputs are input to, 2 pin are stable state RC fixed values, are exported through 7 pin reversed-phase outputs,
The signal that this output signal arranges J1 6 pin of input with inserting terminal is compared through the 3rd nor gate U1C logic circuits, if frequency exceedes
The 3rd nor gate U1C 10 pin will send high level during the highest frequency value of setting, and by terminal block J2, J3 connection positions number are come
Selection directly output or the output alarm signal after the second frequency divider U4 counts frequency dividing, this alarm signal pass through the four or two pole
Pipe D4 is output to 10 pin that inserting terminal arranges J1.Wherein terminal block J2, J3 numbers selections are according to power, the frequency size of equipment
It is fixed.When frequency is high by the second frequency divider U4 using count frequency dividing method carry out signal transmission, when frequency is low without
Second frequency divider U4 is directly transmitted, and this setting effectively ensure that the safety and stability during equipment use.By
Protected in two grades of carrier current protections for frequency limitation, be fixed value.
Underfrequency protection：The first NAND gate U6A is sent to after double D trigger U5 two divided-frequencies and carries out anti-phase processing, after processing
High level by charging diode D5 to the 8th electric capacity C8 charging, when the first NAND gate U6A 3 pin are output as low level,
8th electric capacity C8 electric charge can be discharged by the first potentiometer WR1 and the 7th resistance R7, when frequency it is low to be unable to maintain that second and
The 5 of NOT gate U6B, the second NAND gate U6B 4 pin can export high level during the threshold voltage of 6 pin, and high level signal passes through the six or two
Pole pipe D6 is output to 10 pin that inserting terminal arranges J1.Wherein, the first potentiometer WR1 is underfrequency protection potentiometer, by adjusting this
Potentiometer can setpoint frequency lower limit, this setting further ensure that the width and adjustability of the circuit scope of application, Ke Yigeng
The good use demand for meeting different user, sets science, rationally.
The present invention is provided with underfrequency protection and dual carrier current protection so that more safe and reliable during inverter use,
The second nor gate U1B 4 pin, the second NAND gate U6B 4 pin, terminal block J3 and inserting terminal arrange the 10 of J1 in this circuit simultaneously
The diode with one-way transmission function is provided between pin, effectively prevent in different electrical equipment transmitting procedures mutually it
Between signal interference, effectively prevent a certain electrical equipment (the second nor gate U1B or the second NAND gate U6B or terminal block J3) defeated
The possibility that the high level gone out is dragged down by other point positions, it is ensured that the Stability and veracity of circuit working state, circuit connection
Relation sets reasonable, and layout is ingenious, succinct, and circuit reaction speed is fast, sets scientific and reasonable.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description.
Fig. 1 is schematic structural view of the invention；
Fig. 2 locks the structural representation of phase-plate for motherboard in the present invention；
In figure：1- one-level high frequency protecting circuits, bis- grades of high frequency protecting circuits of 2-, 3- low-frequency protection circuits, 4- frequency protections
Plate, 5- motherboards lock phase-plate.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As shown in Fig. 1~2, a kind of frequency protection circuit proposed by the present invention, including circuit input end, circuit output end,
One-level high frequency protecting circuit 1,
One-level high frequency protecting circuit 1 includes the first frequency divider U3, and the first frequency divider U3 inputs are connected with circuit input end,
Mono- input of output end and the second nor gate U1B and the second flip and flop generator U2B inputs are all connected with, and the second bistable state is touched
Hair device U2B output ends are connected with second nor gate U1B another input, the second nor gate U1B output end and circuit output
End connection.
Further, the second flip and flop generator U2B is connected by the first FM circuit with power supply,
First FM circuit include the second potentiometer WR2, second potentiometer WR2 one end connected with first resistor R1 after with electricity
Source is connected, and the other end is all connected with the second electric capacity C2 and the second flip and flop generator U2B, and the second electric capacity C2 other ends connect with ground
Connect.
Further, also including two grades of high frequency protecting circuits 2,
Two grades of high frequency protecting circuits 2 include the 3rd nor gate U1C, and the 3rd nor gate U1C two inputs are respectively with the
One frequency divider U3 output end and the first flip and flop generator U2A connections, output end and the second frequency divider U4 and circuit output end
It is all connected with, the second frequency divider U4 is connected with circuit output end.
Further, two grades of high frequency protecting circuits 2 are connected by the second FM circuit with power supply,
Second FM circuit includes the 5th resistance R5 and the 6th resistance R6 parallel with one another, one end and power supply after both parallel connections
Connection, the other end is all connected with the first electric capacity C1 and the first flip and flop generator U2A, and the first electric capacity C1 is connected to ground.
Further, it is provided with the 4th diode D4 between the second frequency divider U4 and circuit output end.
Further, the first frequency divider U3 is connected by 3rd resistor R3 with power supply.
Further, the first frequency divider U3 passes through the first diode D1, the second diode D2 and the second frequency divider U4, respectively
Three nor gate U1C input connection.
Further, also including low-frequency protection circuit 3,
Low-frequency protection circuit 3 includes the double D trigger U5, the first NAND gate U6A, regulation circuit being sequentially connected, regulation electricity
Road includes charging circuit and discharge circuit parallel with one another, and charging circuit includes charging diode D5, and discharge circuit includes mutual
The the first potentiometer WR1 and the 7th resistance R7 of series connection, regulation circuit are connected to ground by the 8th electric capacity C8, pass through the second NAND gate
U6B is connected with circuit output end, and double D trigger U5 is connected with circuit input end.
Further, it is respectively arranged with the three or two pole between the second nor gate U1B, the second NAND gate U6B and circuit output end
Pipe D3 and the 6th diode D6.
Further, the first flip and flop generator U2A, the second flip and flop generator U2B are arranged on same trigger chip,
Trigger chip model is CD4528,
Second nor gate U1B and the 3rd nor gate U1C are arranged on same nor gate chip, and nor gate chip model is
CD4001,
First frequency divider U3 and the second frequency divider U4 model are CD4020,
First NAND gate U6A, the second NAND gate U6B are arranged on same NAND gate chip, and NAND gate chip model is
CD4011。
Frequency protection circuit production board is frequency protection plate 4, and frequency protection plate arranges J1 by inserting terminal and is arranged on motherboard
Lock on phase-plate 5, wherein circuit input end (inserting terminal row J1 gathers 6 pin), circuit output end (inserting terminal row J1 collections 10
Pin) it is connected respectively with the frequency output terminal of phase lock circuitry, the frequency input of protection circuit on motherboard lock phase-plate 5.Frequency protection
Circuit is exactly based on collection resonant frequency, is internally divided into the processing of high and low frequency two parts, frequency is adjusted by potentiometer
The upper limit (Fmax) and lower-frequency limit (Fmin) when frequency exceedes the upper limit or lower limit, output high level carrys out trigger protection circuit, so that
Ensure the safety of equipment.During work, equipment working signal is arranged J1 by inserting terminal and inputted into frequency protection circuit, Zhi Hougao
Frequency carries out analysis feedback by high frequency protecting circuit, and low frequency carries out analysis feedback, wherein inserting terminal by low-frequency protection circuit
The incoming frequency square-wave signal that J1 gathers 6 pin is arranged, high-frequency protecting signal is divided into two-way, including one-level high frequency protecting circuit and two grades
High frequency protecting circuit, with double protection functions.
One-level carrier current protection：The input signal that J1 transmission is come in is arranged through inserting terminal, is sent after being divided through the first frequency divider U3
The 12 pin A inputs to the second flip and flop generator U2B are as rising edge trigger signal, wherein the second potentiometer WR2 is U2 cores
14 pin stable state RC time adjustments of piece, ratio during carrier current protection can be determined during work by adjusting the second potentiometer WR2 resistance
Compared with the width of pulse；Second flip and flop generator U2B 9 pin are reversed-phase output, and this output signal is believed with the frequency after frequency dividing
Number being sent to the second nor gate U1B logic circuits is compared, if frequency exceedes the upper limit of setting, will result in the second nor gate
The 5 of U1B, 6 pin have low level appearance, and now 4 pin output high level alarm signal, the signal is inserted by being arrived after the 3rd diode D3
Connecting terminal arranges J1 10 pin output protection signals, and lock phase-plate 5 sends alarm signal after receiving this protection signal.Wherein,
Two potentiometer WR2 are carrier current protection potentiometer, by adjust this potentiometer can setpoint frequency higher limit, this setting is effectively ensured
The width and adjustability of the circuit scope of application, can better meet the use demand of different user, set science, rationally.
Two grades of carrier current protections：J1, which is arranged, through inserting terminal transmits the frequency input signal come in higher than one-level carrier current protection frequency
The second level defencive function that starts (is locked when mutually unsuccessfully frequency is raised to highest frequency) during value.Input signal is direct without frequency dividing
The first flip and flop generator U2A 4 pin A inputs are input to, 2 pin are stable state RC fixed values, are exported through 7 pin reversed-phase outputs,
The signal that this output signal arranges J1 6 pin of input with inserting terminal is compared through the 3rd nor gate U1C logic circuits, if frequency exceedes
The 3rd nor gate U1C 10 pin will send high level during the highest frequency value of setting, and by terminal block J2, J3 connection positions number are come
Selection directly output or the output alarm signal after the second frequency divider U4 counts frequency dividing, this alarm signal pass through the four or two pole
Pipe D4 is output to 10 pin that inserting terminal arranges J1, lock phase-plate 5 receives control relative alarm part work after this alarm signal
Make.Wherein terminal block J2, depending on J3 numbers selections are according to the power of equipment, frequency size.Pass through the second frequency divider when frequency is high
U4 carries out signal transmission using the method for counting frequency dividing, is directly transmitted without the second frequency divider U4 when frequency is low,
This setting effectively ensure that the safety and stability during equipment use.Because two grades of carrier current protections are protected for frequency limitation
Shield, is fixed value.
Underfrequency protection：The first NAND gate U6A is sent to after double D trigger U5 two divided-frequencies and carries out anti-phase processing, after processing
High level by charging diode D5 to the 8th electric capacity C8 charging, when the first NAND gate U6A 3 pin are output as low level,
8th electric capacity C8 electric charge can be discharged by the first potentiometer WR1 and the 7th resistance R7, when frequency it is low to be unable to maintain that second and
The 5 of NOT gate U6B, the second NAND gate U6B 4 pin can export high level during the threshold voltage of 6 pin, and high level signal passes through the six or two
Pole pipe D6 is output to 10 pin that inserting terminal arranges J1, and lock phase-plate 5 sends alarm signal after receiving this protection signal.Wherein,
First potentiometer WR1 is underfrequency protection potentiometer, by adjust this potentiometer can setpoint frequency lower limit, this setting is further
The width and adjustability of the circuit scope of application are ensure that, the use demand of different user can be better met, science is set, closed
Reason.
The present invention is provided with parallel one-level high frequency protecting circuit, two grades of high frequency protecting circuits and low-frequency protection circuit, makes
The frequency signal that must be collected by inverter by processing of circuit relatively after amplitude limit within place of safety (± 10%), once it is super
To go out soon send high level alarm signal, lock phase-plate 5, which is received, adjusted in time after this alarm signal associated components work shape
State is handled power supply, and this setting effectively increases the security during inverter use, reduces rate of breakdown
With maintenance of equipment replacement cost.Second nor gate U1B 4 pin, the second NAND gate U6B 4 pin, terminal block J3 wherein in this circuit
The diode with one-way transmission function is provided between arranging J1 10 pin with inserting terminal, different electrically members are effectively prevent
In part transmitting procedure each other signal interference, effectively prevent a certain electrical equipment (the second nor gate U1B or second with it is non-
Door U6B or terminal block J3) output high level by other possibilities for dragging down of point positions, it is ensured that the accuracy of circuit working state
And stability, rationally, layout is ingenious, succinct for circuit connecting relation setting, and circuit reaction speed is fast, sets scientific and reasonable.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modifications, equivalent substitutions and improvements made etc. should be included within the scope of the present invention.
Claims (9)
1. a kind of frequency protection circuit, it is characterised in that including circuit input end, circuit output end, one-level high frequency protecting circuit
(1),
One-level high frequency protecting circuit (1) includes the first frequency divider (U3), and the first frequency divider (U3) input is inputted with circuit
End connection, input of output end and the second nor gate (U1B) and the second flip and flop generator (U2B) input are all connected with,
Second flip and flop generator (U2B) output end is connected with described another input of second nor gate (U1B), and described second
The output end of nor gate (U1B) is connected with circuit output end.
2. a kind of frequency protection circuit according to claim 1, it is characterised in that second flip and flop generator
(U2B) it is connected by the first FM circuit with power supply,
First FM circuit includes the second potentiometer (WR2), described second potentiometer (WR2) one end and first resistor (R1)
It is connected after series connection with power supply, the other end is all connected with the second electric capacity (C2) and second flip and flop generator (U2B), described
Two electric capacity (C2) other end is connected to ground.
3. a kind of frequency protection circuit according to claim 1, it is characterised in that also including two grades of high frequency protecting circuits
(2),
Two grades of high frequency protecting circuits (2) include the 3rd nor gate (U1C), two inputs of the 3rd nor gate (U1C)
End be connected with the output end and the first flip and flop generator (U2A) of first frequency divider (U3) respectively, output end and second point
Frequency device (U4) and circuit output end are all connected with, and second frequency divider (U4) is connected with circuit output end.
4. a kind of frequency protection circuit according to claim 3, it is characterised in that two grades of high frequency protecting circuits (2)
It is connected by the second FM circuit with power supply,
Second FM circuit includes the 5th resistance (R5) parallel with one another and the 6th resistance (R6), after both parallel connections one end with
Power supply is connected, and the other end is all connected with the first electric capacity (C1) and first flip and flop generator (U2A), first electric capacity
(C1) it is connected to ground.
5. a kind of frequency protection circuit according to claim 3, it is characterised in that second frequency divider (U4) and circuit
The 4th diode (D4) is provided between output end.
6. a kind of frequency protection circuit according to claim 1, it is characterised in that first frequency divider (U3) passes through
Three resistance (R3) are connected with power supply.
7. a kind of frequency protection circuit according to claim 3, it is characterised in that first frequency divider (U3) is led to respectively
Cross the first diode (D1), the second diode (D2) and second frequency divider (U4), the input of the 3rd nor gate (U1C)
End connection.
8. a kind of frequency protection circuit according to any one of claim 1~7, it is characterised in that also including underfrequency protection
Circuit (3),
The low-frequency protection circuit (3) includes the double D trigger (U5) being sequentially connected, the first NAND gate (U6A), regulation circuit,
The regulation circuit includes charging circuit and discharge circuit parallel with one another, and the charging circuit includes charging diode (D5),
The discharge circuit includes the first potentiometer (WR1) and the 7th resistance (R7) being serially connected, and the regulation circuit passes through the 8th
Electric capacity (C8) is connected to ground, and is connected by the second NAND gate (U6B) with circuit output end, the double D trigger (U5) and circuit
Input is connected.
9. a kind of frequency protection circuit according to claim 8, it is characterised in that second nor gate (U1B), described
Second NAND gate (U6B) is respectively arranged with the 3rd diode (D3) and the 6th diode (D6) between circuit output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710130091.4A CN106953302B (en) | 2017-03-07 | 2017-03-07 | Frequency protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710130091.4A CN106953302B (en) | 2017-03-07 | 2017-03-07 | Frequency protection circuit |
Publications (2)
| Publication Number | Publication Date |
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| CN106953302A true CN106953302A (en) | 2017-07-14 |
| CN106953302B CN106953302B (en) | 2021-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710130091.4A Active CN106953302B (en) | 2017-03-07 | 2017-03-07 | Frequency protection circuit |
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| CN106953302B (en) | 2021-01-22 |
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