CN106952914A - A kind of SOI single port statics random-access memory unit and preparation method thereof - Google Patents
A kind of SOI single port statics random-access memory unit and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 229910021332 silicide Inorganic materials 0.000 claims description 42
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 41
- 238000002955 isolation Methods 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
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- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
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- 230000008859 change Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of SOI single port statics random-access memory unit and preparation method thereof, and the unit includes：First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；Pipe is obtained, is made up of the 3rd nmos pass transistor and the 4th nmos pass transistor.In the present invention, the source electrode of four transistors of the first phase inverter and the second phase inverter is constituted using reinforcing source region, this reinforcing source region Box electric leakages, up and down corner electric leakage and sidewall leakage caused by it can effectively suppress the total dose effect of SOI device in the case of not increasing the area of device.And the present invention can also suppress the floater effect of transistor while total dose effect is effectively suppressed.This invention removes the shortcoming that traditional resistant to total dose ruggedized construction increase chip area and can not suppressing comprehensively leaks electricity caused by total dose effect.And the method for the present invention has the advantages that manufacturing process is simple, mutually compatible with stand CMOS.
Description
Technical field
The invention belongs to reservoir designs and make field, be related to a kind of SOI single port statics random-access memory unit and
Its preparation method.
Background technology
In astrionic system, SRAM (Static Random Access Memory, SRAM) is usually
Because the advantages of its operating rate is fast, technique is compatible with traditional cmos and by extensive use；Due to astrionic system building ring
Border is severe, SRAM be frequently subjected to particle radiation and cause its unit performance to influence and so that whole memory performance is degenerated.
Conventional static random access memory cell mainly uses six transistor types at present, by two pull-up P-type transistors, two drop-downs
N-type transistor and two transmission gate N-type transistors are constituted, and wordline controls the switch of two transmission gate N-type transistors, passes through bit line
Write-in reads data storage, wherein, this six transistors use common metal-oxide-semiconductor.
Most common radiation effect is total dose effect and single particle effect.For relative bulk silicon technological, SOI device
One layer of BOX insulating barrier is added between top layer silicon and substrate, so as to thoroughly inhibit incidental single-particle bolt in body silicon
Lock phenomenon；In addition, this BOX insulating barrier so that the charge number that single particle effect is produced is less and make it that SOI device is imitated in single-particle
Situation should be descended to have alleviated.So, the total dose effect of SOI device obtains more concern compared with single particle effect, is also urgently to solve
Certainly the problem of.On the other hand, the negative effect that the floater effect of SOI device is also due to BOX insulating barriers and brought.Accumulated dose is imitated
When should occur, particle provides additional energy so that some electronics of insulating material are ionized out, forms electron hole pair, one
After part electronics and hole-recombination, some electron hole pair is moved freely.Under electric field action, due to electron mobility
It is higher, it is difficult to be captured by it, is easily discharged from insulating materials, but hole is easier to be captured, and ultimately forms interfacial state, solid
Determine positive charge；These electric charges make it that device (more obvious in nmos pass transistor) threshold voltage itself, electric leakage change, so that
Unit performance is set to change.
As process node develops, it is considered that when gate oxide thickness is less than 3nm, accumulated dose causes the accumulation electricity in grid oxygen
Lotus is not enough to trigger threshold voltage, electric leakage change, therefore can neglect.Insulating materials only exists grid oxygen and field oxygen in SOI device
Two kinds of situations, so, the influence that total dose effect is caused to SOI MOS devices is mainly showed by field oxygen.
The electric leakage that common SOI MOS devices trigger due to total dose effect can be illustrated by Fig. 1, be shown in Fig. 1
Grid region 101, source region 102 and the drain region 103 of SOI MOS devices, wherein, the electric charge that field oxygen is produced with Si interfaces causes sidewall leakage
With Box electric leakages.Part leakage current I is also show in Fig. 1aAnd Ia’.In order to more preferably illustrate its drain conditions, referring to Fig. 2, it is aobvious
The A-A ' of structure shown in Fig. 1 is shown as to a part for profile, including source region 102, grid oxygen 104, fleet plough groove isolation structure 105
(Shallow Trench Insulation, abbreviation STI) and oxygen buried layer 106 (BuriedOxide, abbreviation BOX)；Such as Fig. 2 institutes
Show, sidewall leakage can substantially be divided into grid oxygen and isolate with fleet plough groove isolation structure contact portion, fleet plough groove isolation structure, shallow trench
Structure is leaked electricity with oxygen buried layer contact portion and oxygen buried layer contact portion, referred to as upper corner, side wall, lower corner and Box leakages
Electricity.
Cause memory cell performance degenerate case to solve total dose effect, carried out usually using H type grid structures
Reinforce.As shown in figure 3, being connected in the heavily doped P-type area that the two ends of H grid are formed with the PXing Ti areas below grid oxygen.Because H grid two
The part of body contact zone 107 at end is changed to heavily doped P-type area, rather than insulating material, so as to suppress the electricity that total dose effect is brought
Lotus is accumulated so that electric leakage is reduced.Referring to Fig. 4, the B-B ' of structure shown in Fig. 3 is shown as to a part for profile, wherein, H
The corresponding electric leakage of grid is mainly Box electric leakages and a small amount of lower corner electric leakage.Although H grid can solve corner and the leakage of side wall
Electric and most of lower corner electrical leakage problems, but its Box electric leakages and a small amount of lower corner drain conditions still have；And its
Device area is greatly increased.
Therefore, how a kind of SOI single port statics random-access memory unit and preparation method thereof is provided, is ensureing not increase
Effectively suppress the total dose effect of SOI static random access memory cells on the premise of chip area, as those skilled in the art
An important technological problems urgently to be resolved hurrily.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of SOI single port statics are random
Memory cell and preparation method thereof, for solve in the prior art SOI single port statics random-access memory unit due to total agent
Graded effect causes the problem of electric leakage increases.
In order to achieve the above objects and other related objects, the present invention provides a kind of SOI single port statics random access memory list
Member, the SOI single port statics random-access memory unit includes：
First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；
Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；
Pipe is obtained, is made up of the 3rd nmos pass transistor and the 4th nmos pass transistor；
Wherein, the source electrode of the 3rd NMOS tube is connected to the output end and second phase inverter of first phase inverter
Input, grid is connected to the wordline of memory, and drain electrode is connected to the bit line of memory；
The source electrode of 4th nmos pass transistor is connected to the output end and first phase inverter of second phase inverter
Input, grid is connected to the wordline of memory, and drain electrode is connected to the antiposition line of memory；Wherein：Described first, second
The source electrode of PMOS transistor and first, second nmos pass transistor is using reinforcing source region；For nmos pass transistor, the reinforcing source
Area includes the first heavily doped N-type area, the first heavily doped P-type area and shallow n-type area, and the first heavily doped P-type area surrounds institute
State longitudinal two ends and the lateral outer ends in the first heavily doped N-type area；For PMOS transistor, it is heavily doped that the reinforcing source region includes second
Miscellaneous p type island region, the second heavily doped N-type area and shallow p type island region, and the second heavily doped N-type area surrounds the second heavy doping P
Longitudinal two ends in type area and lateral outer ends.
Alternatively, the reinforcing source region top is formed with metal silicide；For nmos pass transistor, first heavy doping
N-type region and the first heavily doped P-type area are in contact with the metal silicide, and the shallow n-type area transverse ends respectively with
The body area of the metal silicide and the nmos pass transistor is in contact；For PMOS transistor, the second heavily doped P-type area
And second heavily doped N-type area be in contact with the metal silicide, and the shallow p type island region transverse ends respectively with the gold
The body area of category silicide and the PMOS transistor is in contact.
Alternatively, any one of the metal silicide in cobalt silicide and titanium silicide.
Alternatively, the drain electrode top of first, second PMOS transistor and first, second nmos pass transistor is each formed with
Metal silicide.
Alternatively, the SOI single port statics random-access memory unit is using from bottom to top successively including backing bottom, insulation
Between active area where the SOI substrate of buried regions and top layer silicon, each transistor by up and down through the top layer silicon shallow trench every
From structure isolation.
Alternatively, the source electrode of the 3rd nmos pass transistor and the 4th nmos pass transistor at least one using it is described reinforce
Source region.
Alternatively, at least one in the 3rd nmos pass transistor and the 4th nmos pass transistor uses common grid NMOS
Pipe, T-shaped grid NMOS tube or H type grid NMOS tubes.
Alternatively, for nmos pass transistor, the first heavily doped P-type area also surrounds the first heavily doped N-type area
Bottom；For PMOS transistor, the second heavily doped N-type area also surrounds the bottom in the second heavily doped P-type area.
The present invention also provides a kind of preparation method of SOI single port statics random-access memory unit, it is characterised in that including
Following steps：
S1：There is provided one includes the SOI substrate at backing bottom, insulating buried layer and top layer silicon successively from bottom to top, in the top layer
Fleet plough groove isolation structure is made in silicon, active area is defined；
S2：Position according to the active area makes N traps, the first p-well and the second p-well in the top layer silicon, wherein, institute
N traps are stated to be located between first p-well and the second p-well；
S3：The first PMOS transistor and the second PMOS transistor are made in the N traps；Made in first p-well
First nmos pass transistor and the 3rd nmos pass transistor；The second nmos pass transistor is made in second p-well and the 4th NMOS is brilliant
Body pipe；Wherein, first PMOS transistor, the first nmos pass transistor, the second PMOS transistor and the second nmos pass transistor
Source electrode is using reinforcing source region；For nmos pass transistor, the reinforcing source region includes the first heavily doped N-type area, the first heavy doping P
Type area and shallow n-type area, and the first heavily doped P-type area surrounds longitudinal two ends and the transverse direction in the first heavily doped N-type area
Outer end；For PMOS transistor, the reinforcing source region includes the second heavily doped P-type area, the second heavily doped N-type area and shallow p-type
Area, and the second heavily doped N-type area surrounds longitudinal two ends and the lateral outer ends in the second heavily doped P-type area；
S4：Metallic vias and respective metal line are made, to complete the making of the memory cell.
Alternatively, the step S3 includes step：
S3-1：Form first grid across first p-well and the N traps and the across the N traps and the second p-well
Two grids, and in the first p-well predeterminated position the 3rd grid of formation, in the second p-well predeterminated position the 4th grid of formation；
The first grid is shared by first nmos pass transistor and first PMOS transistor；The second grid is described
Second nmos pass transistor and second PMOS transistor are shared；
S3-2：The first, second p-well predeterminated position carry out N-type be lightly doped, formed described first, second, third and
The shallow n-type area of 4th nmos pass transistor；P-type is carried out in the N traps predeterminated position to be lightly doped, and forms first, second PMOS
The shallow p type island region of transistor；
S3-3：Side wall isolation structure is formed around first, second, third, fourth grid；
S3-4：N-type heavy doping is carried out in first, second p-well and the N traps predeterminated position, described first is formed, the
The reinforcing in the first heavily doped N-type area and first, second PMOS transistor in the reinforcing source region of bi-NMOS transistor
The second heavily doped N-type area in source region；P-type heavy doping is carried out in first, second p-well and the N traps predeterminated position,
The the first heavily doped P-type area and described first, second formed in the reinforcing source region of first, second nmos pass transistor
The second heavily doped P-type area in the reinforcing source region of PMOS transistor.
Alternatively, in the step S3-4, using together on the inside of the longitudinal interlude of reinforcing source region provided with opening
Mask plate, vertically carry out ion implanting via the mask plate, complete the first heavily doped N-type area N-type heavy doping or
The p-type heavy doping in the second heavily doped P-type area.
Alternatively, in the step S3-4, the first heavily doped P-type area and described are formed using ion implantation
Two heavily doped N-type areas；The concentration range of the ion implanting is 1E15-9E15/cm2。
Alternatively, in the step S3-4, it is additionally included in the first, second p-well predeterminated position and carries out N-type heavy doping
To form first, second, third, fourth nmos transistor drain and the three, the 4th nmos pass transistor source electrode, in institute
N traps predeterminated position is stated to carry out p-type heavy doping to form the step of first, second PMOS transistor drains.
Alternatively, the drain electrode of first nmos pass transistor is shared with the source electrode of the 3rd nmos pass transistor；Described
The drain electrode of bi-NMOS transistor is shared with the source electrode of the 4th nmos pass transistor.
Alternatively, in the step S3, it is additionally included in the step of metal silicide is formed at the reinforcing source region top；It is right
In nmos pass transistor, the first heavily doped N-type area of the metal silicide and the reinforcing source region, the first heavily doped P-type area with
And shallow n-type area is contacted with each other；For PMOS transistor, the metal silicide and the second heavy doping P of the reinforcing source region
Type area, the second heavily doped N-type area and shallow p type island region are contacted with each other.
Alternatively, the metal level and the Si under it are made by forming metal level in the reinforcing source region, and being heat-treated
Material reacts, and generates the metal silicide.
Alternatively, the temperature range of the heat treatment is 700-900 DEG C, and the time is 50-70 seconds.
Alternatively, in the step S3, first, second PMOS transistor and first, second NMOS are additionally included in
The step of drain electrode of transistor forms metal silicide with grid top, and in the source of the three, the 4th nmos pass transistor
The step of pole forms metal silicide with drain electrode top.
Alternatively, first nmos pass transistor is interconnected and form the first phase inverter with first PMOS transistor；It is described
Second nmos pass transistor is interconnected and form the second phase inverter with second PMOS transistor；The source electrode connection of 3rd NMOS tube
To the output end and the input of second phase inverter of first phase inverter, grid is connected to the wordline of memory, drains
It is connected to the bit line of memory；The source electrode of 4th nmos pass transistor is connected to the output end of second phase inverter and described
The input of first phase inverter, grid is connected to the wordline of memory, and drain electrode is connected to the antiposition line of memory.
Alternatively, first, second, third, fourth grid includes gate dielectric layer and on the gate dielectric layer
Polysilicon layer.
Alternatively, for nmos pass transistor, the first heavily doped P-type area also surrounds the first heavily doped N-type area
Bottom；For PMOS transistor, the second heavily doped N-type area also surrounds the bottom in the second heavily doped P-type area.
As described above, SOI single port static random-access memory units of the present invention and preparation method thereof, with following beneficial
Effect：In the SOI single port statics random-access memory unit, four transistors of the first phase inverter of composition and the second phase inverter
Source electrode using source region is reinforced, for nmos pass transistor, the reinforcing source region includes the first heavily doped N-type area, first heavily doped
Miscellaneous p type island region and shallow n-type area, and the first heavily doped P-type area surrounds longitudinal two ends and the horizontal stroke in the first heavily doped N-type area
Outward；For PMOS transistor, the reinforcing source region includes the second heavily doped P-type area, the second heavily doped N-type area and shallow P
Type area, and the second heavily doped N-type area surrounds longitudinal two ends and the lateral outer ends in the second heavily doped P-type area.It is this to add
Gu source region caused by it can effectively suppress the total dose effect of SOI device in the case of not increasing the area of device Box electric leakage, on
Lower corner electric leakage and sidewall leakage.And the present invention can also suppress transistor while total dose effect is effectively suppressed
Floater effect.Increase chip area this invention removes traditional resistant to total dose ruggedized construction and accumulated dose effect can not be suppressed comprehensively
The shortcoming of electric leakage caused by answering, and the present invention also has the advantages that manufacturing process is simple, mutually compatible with stand CMOS.
Brief description of the drawings
Fig. 1 is shown as the overlooking structure figure of common SOI MOS devices in the prior art.
Fig. 2 is shown as the A-A ' of structure shown in Fig. 1 to profile.
Fig. 3 is shown as the overlooking structure figure of H grid SOI MOS devices of the prior art.
Fig. 4 is shown as the B-B ' of structure shown in Fig. 3 to profile.
Fig. 5 is shown as the circuit theory schematic diagram of the SOI single port static random-access memory units of the present invention.
Fig. 6 is shown as having the NMOS crystal for reinforcing source region in the SOI single port static random-access memory units of the present invention
The overlooking the structure diagram of pipe.
Fig. 7-Fig. 9 be respectively indicated as the C-C ' of structure shown in Fig. 6 to, D-D ' to and E-E ' to profile.
Figure 10-Figure 11 be respectively indicated as the C-C ' of the structure shown in Fig. 6 in another embodiment to and E-E ' to profile
Figure 12-Figure 14 is respectively indicated as the NMOS transistor structure schematic diagram using common grid, T-shaped grid and H type grid.
Figure 15-Figure 21 is shown as each step in the preparation method of the SOI single port static random-access memory units of the present invention
The overlooking the structure diagram presented.
Component label instructions
101 grid regions
102 source regions
103 drain regions
104 grid oxygens
105 fleet plough groove isolation structures
106 oxygen buried layers
107 body contact zones
201 first phase inverters
2011 first PMOS transistors
2012 first nmos pass transistors
202 second phase inverters
2021 second PMOS transistors
2022 second nmos pass transistors
203 obtain pipe
2031 the 3rd nmos pass transistors
2032 the 4th nmos pass transistors
204 reinforce source region
2041 first heavily doped N-type areas
2042 first heavily doped P-type areas
2043 shallow n-type areas
205 drain electrodes
206 grids
2061 gate dielectric layers
2062 polysilicon layers
207 body areas
208 backing bottoms
209 insulating buried layers
210 fleet plough groove isolation structures
211 side wall isolation structures
212 metal silicides
213 common grid
214 T-shaped grid
215 H type grid
216 source regions
217 drain regions
218 body contact zones
20a, 20b, 20c, 20d active area
30 N traps
The p-wells of 40a first
The p-wells of 40b second
50a first grids
50b second grids
The grids of 50c the 3rd
The grids of 50d the 4th
60a, 60b shallow n-type area
The shallow p type island region of 70a, 70b
The heavily doped N-type area of 80a, 80b first
The heavily doped N-type area of 90a, 90b second
The heavily doped P-type area of 91a, 91b first
The heavily doped P-type area of 92a, 92b second
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by different specific in addition
Embodiment is embodied or practiced, and the various details in this specification can also not carried on the back based on different viewpoints and application
Various modifications or alterations are carried out under spirit from the present invention.
Fig. 5 is referred to Figure 21.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then in schema only display with relevant component in the present invention rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of SOI single port statics random-access memory unit, referring to Fig. 5, it is single-ended to be shown as the SOI
The circuit theory schematic diagram of mouth static random access memory cell, including：
First phase inverter 201, is made up of the first PMOS transistor 2011 and the first nmos pass transistor 2012；
Second phase inverter 202, is made up of the second PMOS transistor 2021 and the second nmos pass transistor 2022；
Pipe 203 is obtained, is made up of the 3rd nmos pass transistor 2031 and the 4th nmos pass transistor 2032；3rd NMOS tube
Source electrode be connected to the output end of first phase inverter and the input of second phase inverter, grid is connected to memory
Wordline WL, drain electrode is connected to the bit line BL of memory；The source electrode of 4th nmos pass transistor is connected to second phase inverter
Output end and first phase inverter input, grid is connected to the wordline of memory, and drain electrode is connected to the anti-of memory
Bit line BLB.
As an example, the source electrode of the PMOS transistor 2021 of the first PMOS transistor 2011 and second is and power end
VDD connections, the drain electrode respectively with the nmos pass transistor 2022 of the first nmos pass transistor 2012 and second that drains is connected, as anti-
The output end of phase device.The grid of the PMOS transistor 2021 of first PMOS transistor 2011 and second is respectively with described first
The grid of the nmos pass transistor 2022 of nmos pass transistor 2012 and second is connected, and is used as the input of phase inverter.First NMOS
The source grounding line GND of the nmos pass transistor 2022 of transistor 2012 and second, it is anti-phase to realize the first phase inverter 201 and second
The function of device 202.The first memory node Q and the second memory node QB position are also show in Fig. 5.
Particularly, in the phase inverter 202 of the first phase inverter 201 and second, first, second PMOS transistor
2011st, 2021 and first, second nmos pass transistor 2012,2022 source electrode using reinforce source region, wherein, for NMOS crystal
Pipe, the reinforcing source region includes the first heavily doped N-type area, the first heavily doped P-type area and shallow n-type area, and described first heavily doped
Miscellaneous p type island region surrounds longitudinal two ends and the lateral outer ends in the first heavily doped N-type area；For PMOS transistor, the reinforcing source
Area includes the second heavily doped P-type area, the second heavily doped N-type area and shallow p type island region, and the second heavily doped N-type area surrounds institute
State longitudinal two ends and the lateral outer ends in the second heavily doped P-type area.
It is pointed out that it is of the invention, it is parallel with transistor source and drain direction to be referred to as " transverse direction ", with transistor source and drain direction
Vertically it is referred to as " longitudinal direction ".Heretofore described " lateral inner ends ", " lateral outer ends " be for transistor body area, it is described
Reinforce source region close to the side in transistor body area to be referred to as " the inner ", the side of the reinforcing source region away from transistor body area is referred to as
For " outer end ".
As an example, referring to Fig. 6 to Fig. 9, it is shown with reinforcing the structural representation of the nmos pass transistor of source region, its
In, Fig. 6 is top view, Fig. 7-Fig. 9 be respectively structure shown in Fig. 6 C-C ' to, D-D ' to and E-E ' to profile.The present invention
In, the SOI single port statics random-access memory unit using include successively from bottom to top backing bottom 208, insulating buried layer 209 and
By up and down through the fleet plough groove isolation structure of the top layer silicon between the SOI substrate of top layer silicon, active area where each transistor
210 isolation.
Specifically, the backing bottom 208 includes but is not limited to the conventional semiconductor substrates such as Si, Ge, and there can be certain class
The doping of type.In the present embodiment, the backing bottom 208 uses p-type Si substrates, and the insulating buried layer 209 uses silica.
It is described to include reinforcing source region 204, drain electrode 205, grid using the nmos pass transistor for reinforcing source region as shown in Fig. 6-Fig. 9
Pole 206 and the body area 207 between the reinforcing source region 204 and drain electrode 205.The reinforcing source region 204 includes the first weight
Doped N-type area 2041, the first heavily doped P-type area 2042 and shallow n-type area 2043, and the first heavily doped P-type area 2042 wraps
Enclose longitudinal two ends and the lateral outer ends in the first heavily doped N-type area 2041.In the present embodiment, also set around the grid 206
There is side wall isolation structure 211, the side wall isolation structure 211 covers the part of shallow n-type area 2043.The grid 206 is wrapped
Include gate dielectric layer 2061 and the polysilicon layer 2062 on the gate dielectric layer 2061.
Further, as shown in figs. 7 to 9, reinforcing source region 204 top is formed with metal silicide 212, and described
First heavily doped N-type area 2041 and the first heavily doped P-type area 2042 are in contact with the metal silicide 212, the shallow n-type
Body area 207 of the transverse ends in area 2043 respectively with the metal silicide 212 and the nmos pass transistor is in contact.
The metal silicide 212 includes but is not limited to the conductive silicide such as cobalt silicide and titanium silicide, and it is with described first
Heavily doped P-type area 2042 of heavily doped N-type area 2041 and first forms Ohmic contact.As an example, the drain electrode 205 and grid
206 tops are also each formed with metal silicide 212, for reducing drain electrode and the contact resistance between grid and extraction electrode.
It is pointed out that the nmos pass transistor (described first, second to use reinforcing source region of Fig. 6-Fig. 9 displays
Nmos pass transistor 2012, structural representation 2022), for using the PMOS transistor (described first, second for reinforcing source region
PMOS transistor 2011,2021), its structure and basically identical, simply each doping using the NMOS transistor structure for reinforcing source region
The doping type in area is on the contrary, no longer illustrated herein.
In the SOI single port static random-access memory units of the present invention, the four of the first phase inverter and the second phase inverter are constituted
The source electrode of individual transistor using reinforce source region, for nmos pass transistor, the reinforcing source region include the first heavily doped N-type area,
First heavily doped P-type area and shallow n-type area, and the first heavily doped P-type area surrounds the longitudinal direction in the first heavily doped N-type area
Two ends and lateral outer ends.Because the first heavily doped P-type area is in contact with reinforcing the SI semi-insulation buried regions of source region bottom, and with
The fleet plough groove isolation structure is in contact, and can effectively block BOX and Si material interfaces, fleet plough groove isolation structure and Si materials circle
The leak channel in face, so that Box electric leakages, up and down corner electric leakage and side wall effectively caused by the total dose effect of suppression SOI device
Electric leakage, eliminates traditional resistant to total dose ruggedized construction increase chip area and can not effectively suppress the shortcoming of total dose effect.
For using the PMOS transistor for reinforcing source region, with similar effect.
In addition, in the present invention, for NMOS, contact resistance can not only be reduced by reinforcing the metal silicide on source region top,
The first heavily doped P-type area can also be connected to low level, because the first heavily doped P-type area connects with the body area
Touch so that the hole of body area accumulation is released, so as to while total dose effect is effectively suppressed, can also effectively suppress floating
Bulk effect, improves the stability of unit.Also, positioned at the first heavily doped P-type area of the first heavily doped N-type area lateral outer ends
Will be in parallel positioned at the first heavily doped P-type area at the longitudinal two ends in the heavily doped N-type area, relative to only in the first heavy doping N
Type area longitudinal direction two ends have the scheme in the first heavily doped P-type area, and the present invention can further reduce body contact resistance, more effectively
Suppress floater effect.For using the PMOS transistor for reinforcing source region, with similar effect.
The 3rd nmos pass transistor 2031 and the 4th nmos pass transistor 2032 used for the acquisition pipe 203, its source
But pole at least one use the reinforcing source region.The nmos pass transistor obtained in pipe 203 is favourable using source region is reinforced
There is disadvantage, can be selected according to specific application.
In another embodiment, can at least one in the 3rd nmos pass transistor 2031 and the 4th nmos pass transistor 2032
It is individual to use common grid NMOS tube, T-shaped grid NMOS tube or H type grid NMOS tubes.As shown in Figure 12-Figure 14, it is respectively indicated as using general
The NMOS transistor structure schematic diagram of pass gate 213, T-shaped grid 214 and H types grid 215, wherein grid both sides are respectively source region 216 and leakage
Area 217, for T-shaped grid NMOS and H type grid nmos pass transistors, also has body contact zone 218 respectively.Common grid NMOS tube, T-shaped grid
NMOS tube and H type grid NMOS tubes are known in the art, and here is omitted.
Embodiment two
The present embodiment uses essentially identical technical scheme with embodiment one, and difference is, right in embodiment one
The nmos pass transistor used in phase inverter, the first heavily doped P-type area 2042 surrounds the first heavily doped N-type area 2041
Longitudinal two ends and lateral outer ends, the bottom in the first heavily doped N-type area 2041 still contacts with BOX, it would still be possible to occur a little
Electric leakage.The PMOS transistor used for phase inverter, is also such.And in the present embodiment, used for phase inverter
Nmos pass transistor, longitudinal two ends and transverse direction of the first heavily doped P-type area 2042 except surrounding the first heavily doped N-type area 2041
Outer end, also further surrounds the bottom in the first heavily doped N-type area 2041；The PMOS transistor used for phase inverter, it is described
Longitudinal two ends and lateral outer ends of the second heavily doped N-type area except surrounding the second heavily doped P-type area, also further surround the second weight
The bottom in doped p-type area.
As shown in Figures 10 and 11, be shown as the C-C ' of structure shown in Fig. 6 in the present embodiment to and E-E ' to profile.By
Longitudinal two ends, the lateral outer ends in the first heavily doped N-type area 2041 are surrounded simultaneously in the first heavily doped P-type area 2042
And bottom, it can more fully suppress Box electric leakages, up and down corner electric leakage and side wall caused by the total dose effect of SOI device
Electric leakage.
Embodiment three
The present invention also provides a kind of preparation method of SOI single port statics random-access memory unit, comprises the following steps：
Step S1 is first carried out：There is provided one, the SOI including backing bottom, insulating buried layer and top layer silicon is served as a contrast successively from bottom to top
Bottom, makes fleet plough groove isolation structure in the top layer silicon, defines active area.
As an example, as shown in figure 15, defining four active areas 20a, 20b, 20c, 20d, this four active areas are successively
Arranged in parallel, each active area surrounding is formed with shallow channel, the shallow channel and constitutes shallow trench isolation junction filled with insulating materials
Structure.In the present embodiment, the insulating materials is silica.
Then step S2 is performed：As shown in figure 16, the position according to the active area makes N traps in the top layer silicon
30th, the first p-well 40a and the second p-well 40b, wherein, the N traps 30 are located between the first p-well 40a and the second p-well 40b.
Specifically, forming the N traps and first, second p-well using ion injection method.As an example, the N traps are used
Phosphonium ion injects, and the p-well is injected using boron ion.The N traps are used to make PMOS transistor, and its subregion is used as PMOS
The body area of transistor；First, second p-well be used for make nmos pass transistor, its subregion as nmos pass transistor body
Area.
Step S3 is performed again：As shown in Figure 17 to Figure 21, the first PMOS transistor 2011 and are made in the N traps 30
Two PMOS transistors 2021；The first nmos pass transistor 2012 and the 3rd nmos pass transistor are made in the first p-well 40a
2031；The second nmos pass transistor 2022 and the 4th nmos pass transistor 2032 are made in the second p-well 40b；Wherein, Tu18Zhong
Each transistor region is shown using dotted line frame.
Particularly, first PMOS transistor 2011, the first nmos pass transistor 2012, the second PMOS transistor 2021 and
The source electrode of second nmos pass transistor 2023 is using reinforcing source region.For nmos pass transistor, the reinforcing source region includes the first weight
Doped N-type area, the first heavily doped P-type area and shallow n-type area, and the first heavily doped P-type area surrounds the first heavy doping N
Longitudinal two ends in type area and lateral outer ends；For PMOS transistor, the reinforcing source region includes the second heavily doped P-type area, second
Heavily doped N-type area and shallow p type island region, and the second heavily doped N-type area surrounds longitudinal two ends in the second heavily doped P-type area
And lateral outer ends.
As an example, the step S3 includes step：
S3-1：As shown in figure 17, first grid 50a and the leap across the first p-well 40a and the N traps 30 are formed
The second grid 50b of the p-well 40b of N traps 30 and second, and in the first p-well 40a predeterminated positions the 3rd grid of formation
50c, in the 4th grid 50d of the second p-well 40b predeterminated positions formation；The first grid 50a is the first NMOS crystal
Pipe 2012 and first PMOS transistor 2011 are shared；The second grid 50b is second nmos pass transistor 2022
And second PMOS transistor 2021 is shared.
Specifically, described first, second, third, fourth grid 50a, 50b, 50c, 50d include gate dielectric layer and are located at
Polysilicon layer on the gate dielectric layer.
S3-2：As shown in figure 19, carry out N-type in first, second p-well 40a, the 40b predeterminated position to be lightly doped, form institute
State the shallow n-type area of first, second, third, fourth nmos pass transistor 2012,2022,2031,2032；Position is preset in the N traps 30
Put progress p-type to be lightly doped, form the shallow p type island region of first, second PMOS transistor 2011,2021.
It is pointed out that illustrate only first, second nmos pass transistor for ease of illustration, in Figure 17
2012nd, 2022 shallow n-type the area 60a, 60b reinforced in source region region and first, second PMOS transistor 2011,2021
Shallow the p type island region 70a, 70b reinforced in source region region.
S3-3：As shown in figure 20, formed around described first, second, third, fourth grid 50a, 50b, 50c, 50d
Side wall isolation structure 211.
S3-4：As shown in figure 21, N-type weight is carried out in first, second p-well 40a, 40b and the predeterminated position of N traps 30
Doping, the first heavily doped N-type area formed in the reinforcing source region of first, second nmos pass transistor 2012,2022
The second heavily doped N-type area in the reinforcing source region of 80a, 80b and first, second PMOS transistor 2011,2021
90a, 90b；P-type heavy doping is carried out in first, second p-well 40a, 40b and the predeterminated position of N traps 30, described the is formed
First, in the reinforcing source region of the second nmos pass transistor 2012,2022 the first heavily doped P-type area 91a, 91b and it is described first,
The second heavily doped P-type area 92a, 92b in the reinforcing source region of second PMOS transistor 2011,2021.
Specifically, using the mask plate for being provided with opening on the inside of the longitudinal interlude of reinforcing source region together, being covered via this
Film version vertically carries out ion implanting, completes the N-type heavy doping of the first heavily doped N-type area 80a, 80b or second weight
Doped p-type area 92a, 92b p-type heavy doping.
Specifically, also forming the first heavily doped P-type area 91a, 91b and second heavy doping using ion implantation
N-type region 90a, 90b；The concentration range of the ion implanting is 1E15-9E15/cm2。
Specifically, the first heavily doped N-type area 80a is being formed in this step, during 80b, also simultaneously in first, second P
Trap 40a, 40b predeterminated position carry out N-type heavy doping with formed the drain electrode of first, second nmos pass transistor 2012,2022 with
And the source-drain electrode of the three, the 4th nmos pass transistor 2031,2032；Forming the second heavily doped P-type area 92a, 92b
When, also simultaneously the predeterminated position of N traps 30 carry out p-type heavy doping with formed first, second PMOS transistor 2011,
2021 drain electrode.
In the present embodiment, the drain electrode of first nmos pass transistor 2012 and the source electrode of the 3rd nmos pass transistor 2031
Share；The drain electrode of second nmos pass transistor 2032 is shared with the source electrode of the 4th nmos pass transistor 2022.
Further, in this step, it is additionally included in the step of metal silicide is formed at the reinforcing source region top and (does not give figure
Show)；For nmos pass transistor, the metal silicide and the first heavily doped N-type area for reinforcing source region, the first heavy doping P
Type area and shallow n-type area are contacted with each other；For PMOS transistor, the metal silicide and the second weight of the reinforcing source region
Doped p-type area, the second heavily doped N-type area and shallow p type island region are contacted with each other.
Specifically, making the metal level and the Si under it by forming metal level in the reinforcing source region, and being heat-treated
Material reacts, and generates the metal silicide.In the present embodiment, the temperature range of the heat treatment is 700-900 DEG C, and the time is
50-70 seconds.
Specifically, while forming metal silicide on the reinforcing source region top, can also be described first, second
Metal silication is formed at the drain electrode of PMOS transistor 2011,2021 and first, second nmos pass transistor 2012,2022 and grid top
Thing, and in the source electrode and drain electrode top formation metal silicide of the three, the 4th nmos pass transistor 2031,2032, to drop
Contact resistance between low source-drain electrode and grid and extraction electrode.
Finally perform step S4：Metallic vias and respective metal line are made, to complete the making of the memory cell.
Specifically, to be interconnected and form first with first PMOS transistor 2011 anti-phase for first nmos pass transistor 2012
Device；Second nmos pass transistor 2022 is interconnected and form the second phase inverter with second PMOS transistor 2021；Described 3rd
The source electrode of NMOS tube 2031 is connected to the output end of first phase inverter and the input of second phase inverter, grid connection
To the wordline of memory, drain electrode is connected to the bit line of memory；The source electrode of 4th nmos pass transistor 2032 is connected to described
The input of the output end of second phase inverter and first phase inverter, grid is connected to the wordline of memory, and drain electrode is connected to
The antiposition line of memory.
The preparation method of the SOI single port static random-access memory units of the present invention has manufacturing process simple and conventional
The advantages of CMOS technology is mutually compatible.
Example IV
The present embodiment and embodiment three use essentially identical technical scheme, and difference is, what embodiment three made
In SOI single port static random-access memory units, the nmos pass transistor used for phase inverter, first heavily doped P-type
Area 2042 surrounds longitudinal two ends and the lateral outer ends in the first heavily doped N-type area 2041, the first heavily doped N-type area 2041
Bottom still contacted with BOX, it would still be possible to occur a little electric leakage.The PMOS transistor used for phase inverter, is also such.And
In the SOI single port static random-access memory units that the present embodiment makes, the nmos pass transistor used for phase inverter is described
Longitudinal two ends and lateral outer ends of the first heavily doped P-type area 2042 except surrounding the first heavily doped N-type area 2041, are also further wrapped
Enclose the bottom in the first heavily doped N-type area 2041；The PMOS transistor used for phase inverter, the second heavily doped N-type area
Longitudinal two ends and lateral outer ends except surrounding the second heavily doped P-type area, also further surround the bottom in the second heavily doped P-type area
Portion.
In the present embodiment, for the reinforcing source region of nmos pass transistor, what the bottom in its first heavily doped N-type area was newly increased
Heavily doped P-type area is replaced, and the heavily doped P-type area can be formed by ion implanting, by the energy for controlling ion implanting so that
P-type ion concentration peak value is close to the bottom for reinforcing source region.For the reinforcing source region of PMOS transistor, its first heavily doped P-type area
The heavily doped N-type area that is newly increased of bottom replace, the heavily doped N-type area can be formed by ion implanting, by control from
The energy of son injection so that N-type ion concentration peak value is close to the bottom for reinforcing source region.
In the present embodiment, in the reinforcing source region of the nmos pass transistor used by phase inverter, first heavily doped P-type
Area 2042 surrounds longitudinal two ends, lateral outer ends and the bottom in the first heavily doped N-type area 2041 simultaneously；The PMOS that phase inverter is used
In the reinforcing source region of transistor, the second heavily doped N-type area surrounds longitudinal two ends, the transverse direction in the second heavily doped P-type area simultaneously
Box electric leakages, up and down corner leakage caused by outer end and bottom, the total dose effect so as to more fully suppress SOI device
Electricity and sidewall leakage, improve cell stability.
In summary, in SOI single port static random-access memory units of the invention, the first phase inverter of composition and second anti-
The source electrode of four transistors of phase device is using source region is reinforced, for nmos pass transistor, and it is heavily doped that the reinforcing source region includes first
Miscellaneous N-type region, the first heavily doped P-type area and shallow n-type area, and the first heavily doped P-type area surrounds first heavily doped N-type
Longitudinal two ends in area and lateral outer ends；For PMOS transistor, the reinforcing source region includes the second heavily doped P-type area, the second weight
Doped N-type area and shallow p type island region, and the second heavily doped N-type area surround the second heavily doped P-type area longitudinal two ends and
Lateral outer ends.This reinforcing source region can effectively suppress the total dose effect of SOI device in the case where not increasing the area of device
Caused Box electric leakages, up and down corner electric leakage and sidewall leakage.And the present invention is while total dose effect is effectively suppressed, also
The floater effect of transistor can be suppressed.This invention removes traditional resistant to total dose ruggedized construction increase chip area and can not
Suppress the shortcoming leaked electricity caused by total dose effect, and the system of the SOI single port static random-access memory units of the present invention comprehensively
Making method also has the advantages that manufacturing process is simple, mutually compatible with stand CMOS.So, the present invention effectively overcomes existing
Various shortcoming in technology and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (21)
1. a kind of SOI single port statics random-access memory unit, the SOI single port statics random-access memory unit includes：
First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；
Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；
Pipe is obtained, is made up of the 3rd nmos pass transistor and the 4th nmos pass transistor；
Wherein, the source electrode of the 3rd NMOS tube be connected to first phase inverter output end and second phase inverter it is defeated
Enter end, grid is connected to the wordline of memory, and drain electrode is connected to the bit line of memory；
The source electrode of 4th nmos pass transistor be connected to second phase inverter output end and first phase inverter it is defeated
Enter end, grid is connected to the wordline of memory, and drain electrode is connected to the antiposition line of memory；
It is characterized in that：
The source electrode of first, second PMOS transistor and first, second nmos pass transistor is using reinforcing source region；For NMOS
Transistor, the reinforcing source region includes the first heavily doped N-type area, the first heavily doped P-type area and shallow n-type area, and described first
Heavily doped P-type area surrounds longitudinal two ends and the lateral outer ends in the first heavily doped N-type area；It is described to add for PMOS transistor
Gu source region includes the second heavily doped P-type area, the second heavily doped N-type area and shallow p type island region, and the second heavily doped N-type area is wrapped
Enclose longitudinal two ends and the lateral outer ends in the second heavily doped P-type area.
2. SOI single port statics random-access memory unit according to claim 1, it is characterised in that：The reinforcing source region
Top is formed with metal silicide；For nmos pass transistor, the first heavily doped N-type area and the first heavily doped P-type area with
The metal silicide is in contact, and the transverse ends in the shallow n-type area are brilliant with the metal silicide and the NMOS respectively
Ti Guanti areas are in contact；For PMOS transistor, the second heavily doped P-type area and the second heavily doped N-type area with it is described
Metal silicide is in contact, and the shallow p type island region transverse ends respectively with the metal silicide and the PMOS transistor
Body area be in contact.
3. SOI single port statics random-access memory unit according to claim 2, it is characterised in that：The metal silication
Any one of thing in cobalt silicide and titanium silicide.
4. SOI single port statics random-access memory unit according to claim 1, it is characterised in that：Described first, second
The drain electrode top of PMOS transistor and first, second nmos pass transistor is each formed with metal silicide.
5. SOI single port statics random-access memory unit according to claim 1, it is characterised in that：The SOI single ports
Static random access memory cell is used includes the SOI substrate at backing bottom, insulating buried layer and top layer silicon, each crystal successively from bottom to top
Isolated between active area where pipe by the fleet plough groove isolation structure up and down through the top layer silicon.
6. SOI single port statics random-access memory unit according to claim 1, it is characterised in that：3rd NMOS
The source electrode of transistor and the 4th nmos pass transistor at least one use the reinforcing source region.
7. SOI single port statics random-access memory unit according to claim 1, it is characterised in that：3rd NMOS
At least one in transistor and the 4th nmos pass transistor uses common grid NMOS tube, T-shaped grid NMOS tube or H type grid NMOS tubes.
8. SOI single port statics random-access memory unit according to claim 1, it is characterised in that：For NMOS crystal
Pipe, the first heavily doped P-type area also surrounds the bottom in the first heavily doped N-type area；For PMOS transistor, described second
Heavily doped N-type area also surrounds the bottom in the second heavily doped P-type area.
9. a kind of preparation method of SOI single port statics random-access memory unit, it is characterised in that comprise the following steps：
S1：There is provided one includes the SOI substrate at backing bottom, insulating buried layer and top layer silicon successively from bottom to top, in the top layer silicon
Fleet plough groove isolation structure is made, active area is defined；
S2：Position according to the active area makes N traps, the first p-well and the second p-well in the top layer silicon, wherein, the N
Trap is located between first p-well and the second p-well；
S3：The first PMOS transistor and the second PMOS transistor are made in the N traps；First is made in first p-well
Nmos pass transistor and the 3rd nmos pass transistor；The second nmos pass transistor and the 4th nmos pass transistor are made in second p-well；
Wherein, the source electrode of first PMOS transistor, the first nmos pass transistor, the second PMOS transistor and the second nmos pass transistor is equal
Using reinforcing source region；For nmos pass transistor, the reinforcing source region include the first heavily doped N-type area, the first heavily doped P-type area with
And shallow n-type area, and the first heavily doped P-type area surrounds longitudinal two ends and the lateral outer ends in the first heavily doped N-type area；It is right
In PMOS transistor, the reinforcing source region includes the second heavily doped P-type area, the second heavily doped N-type area and shallow p type island region, and institute
State longitudinal two ends and lateral outer ends that the second heavily doped N-type area surrounds the second heavily doped P-type area；
S4：Metallic vias and respective metal line are made, to complete the making of the memory cell.
10. the preparation method of SOI single port statics random-access memory unit according to claim 9, it is characterised in that：Institute
Stating step S3 includes step：
S3-1：Form the first grid across first p-well and the N traps and cross over the N traps and the second gate of the second p-well
Pole, and in the first p-well predeterminated position the 3rd grid of formation, in the second p-well predeterminated position the 4th grid of formation；It is described
First grid is shared by first nmos pass transistor and first PMOS transistor；The second grid is described second
Nmos pass transistor and second PMOS transistor are shared；
S3-2：N-type is carried out in the first, second p-well predeterminated position to be lightly doped, and forms described first, second, third and the 4th
The shallow n-type area of nmos pass transistor；P-type is carried out in the N traps predeterminated position to be lightly doped, and forms the first, second PMOS crystal
The shallow p type island region of pipe；
S3-3：Side wall isolation structure is formed around first, second, third, fourth grid；
S3-4：N-type heavy doping is carried out in first, second p-well and the N traps predeterminated position, described first, second is formed
The reinforcing source in the first heavily doped N-type area and first, second PMOS transistor in the reinforcing source region of nmos pass transistor
The second heavily doped N-type area in area；P-type heavy doping, shape are carried out in first, second p-well and the N traps predeterminated position
Into the first heavily doped P-type area in the reinforcing source region of first, second nmos pass transistor and first, second PMOS
The second heavily doped P-type area in the reinforcing source region of transistor.
11. the preparation method of SOI single port statics random-access memory unit according to claim 10, it is characterised in that：
In the step S3-4, using the mask plate for being provided with opening on the inside of the longitudinal interlude of reinforcing source region together, via this
Mask plate vertically carries out ion implanting, completes the N-type heavy doping in the first heavily doped N-type area or the second heavy doping P
The p-type heavy doping in type area.
12. the preparation method of SOI single port statics random-access memory unit according to claim 10, it is characterised in that：
In the step S3-4, the first heavily doped P-type area and the second heavily doped N-type area are formed using ion implantation；
The concentration range of the ion implanting is 1E15-9E15/cm2。
13. the preparation method of SOI single port statics random-access memory unit according to claim 10, it is characterised in that：
In the step S3-4, be additionally included in the first, second p-well predeterminated position carry out N-type heavy doping to form described first,
Second, third, the 4th nmos transistor drain and the three, the 4th nmos pass transistor source electrode, enter in the N traps predeterminated position
The heavy doping of row p-type is to form the step of first, second PMOS transistor drains.
14. the preparation method of SOI single port statics random-access memory unit according to claim 13, it is characterised in that：
The drain electrode of first nmos pass transistor is shared with the source electrode of the 3rd nmos pass transistor；The leakage of second nmos pass transistor
Pole and the source electrode of the 4th nmos pass transistor are shared.
15. the preparation method of SOI single port statics random-access memory unit according to claim 9, it is characterised in that：In
In the step S3, the step of metal silicide is formed at the reinforcing source region top is additionally included in；It is described for nmos pass transistor
Metal silicide mutually connects with the first heavily doped N-type area, the first heavily doped P-type area and the shallow n-type area of the reinforcing source region
Touch；For PMOS transistor, the metal silicide and the second heavily doped P-type area for reinforcing source region, the second heavily doped N-type
Area and shallow p type island region are contacted with each other.
16. the preparation method of SOI single port statics random-access memory unit according to claim 15, it is characterised in that：
By forming metal level in the reinforcing source region, and being heat-treated makes the metal level be reacted with the Si materials under it, generates institute
State metal silicide.
17. the preparation method of SOI single port statics random-access memory unit according to claim 16, it is characterised in that：
The temperature range of the heat treatment is 700-900 DEG C, and the time is 50-70 seconds.
18. the preparation method of SOI single port statics random-access memory unit according to claim 15, it is characterised in that：
In the step S3, drain electrode and the grid of first, second PMOS transistor and first, second nmos pass transistor are additionally included in
The step of metal silicide is formed at pole top, and formed in the source electrode of the three, the 4th nmos pass transistor with drain electrode top
The step of metal silicide.
19. the preparation method of SOI single port statics random-access memory unit according to claim 9, it is characterised in that：Institute
State the first nmos pass transistor and be interconnected and form the first phase inverter with first PMOS transistor；Second nmos pass transistor and institute
State the second PMOS transistor and be interconnected and form the second phase inverter；The source electrode of 3rd NMOS tube is connected to first phase inverter
The input of output end and second phase inverter, grid is connected to the wordline of memory, and drain electrode is connected to the bit line of memory；
The source electrode of 4th nmos pass transistor is connected to the output end of second phase inverter and the input of first phase inverter,
Grid is connected to the wordline of memory, and drain electrode is connected to the antiposition line of memory.
20. the preparation method of SOI single port statics random-access memory unit according to claim 9, it is characterised in that：Institute
Stating first, second, third, fourth grid includes gate dielectric layer and the polysilicon layer on the gate dielectric layer.
21. the preparation method of SOI single port statics random-access memory unit according to claim 9, it is characterised in that：It is right
In nmos pass transistor, the first heavily doped P-type area also surrounds the bottom in the first heavily doped N-type area；For PMOS crystal
Pipe, the second heavily doped N-type area also surrounds the bottom in the second heavily doped P-type area.
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| CN101009291A (en) * | 2006-01-27 | 2007-08-01 | 无锡中微晶园电子有限公司 | A radiation-resisting BTS SOI CMOS part structure |
| US20110012202A1 (en) * | 2009-07-20 | 2011-01-20 | International Business Machines Corporation | Selective Floating Body SRAM Cell |
| CN102176455A (en) * | 2011-03-15 | 2011-09-07 | 上海宏力半导体制造有限公司 | Static random access memory on silicon substrate of insulator and manufacturing method thereof |
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| US20060081930A1 (en) * | 2004-10-18 | 2006-04-20 | Renesas Technology Corp. | Semiconductor device, manufacturing method thereof, and memory circuit |
| CN101009291A (en) * | 2006-01-27 | 2007-08-01 | 无锡中微晶园电子有限公司 | A radiation-resisting BTS SOI CMOS part structure |
| US20110012202A1 (en) * | 2009-07-20 | 2011-01-20 | International Business Machines Corporation | Selective Floating Body SRAM Cell |
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