CN102176455A - Static random access memory on silicon substrate of insulator and manufacturing method thereof - Google Patents
Static random access memory on silicon substrate of insulator and manufacturing method thereof Download PDFInfo
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- CN102176455A CN102176455A CN2011100616630A CN201110061663A CN102176455A CN 102176455 A CN102176455 A CN 102176455A CN 2011100616630 A CN2011100616630 A CN 2011100616630A CN 201110061663 A CN201110061663 A CN 201110061663A CN 102176455 A CN102176455 A CN 102176455A
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Abstract
The invention provides a static random access memory on silicon substrate of an insulator and a manufacturing method thereof. The adjacent and different types of transistors are isolated from each other by a shallow trench so that the source areas of the adjacent and different types of transistors are completely isolated; the latch-up effect in the silicon substrate does not generate; meanwhile, the adjacent and the same kind of transistors are isolated by an ultra-shallow trench so that body areas among the adjacent and the same kind of transistors are communicated with each other; ions are injected in the source areas on the communicated area in a plurality of memory units to form derivation areas of the body areas, which have the same doping type as the body areas and are in contact with the body areas; and a floating body effect of the communicated area in the memory units can be removed by each derivation area of each body area. The static random access memory formed on the silicon substrate of the insulator reduces the number of the derivation areas of the body areas and the area of a device effectively and eliminates the floating body effect of the body areas.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of static RAM and manufacture method that is formed on the silicon-on-insulator substrate.
Background technology
According to data storage method, semiconductor memory is divided into dynamic random access memory (DRAM), non-volatility memorizer and static RAM (SRAM).SRAM can realize service speed fast in a kind of simple and mode low-power consumption, thereby sets up its special advantages.And, compare with DRAM, because SRAM does not need the periodic refresh canned data, so design and manufacturing are relatively easy.
Usually, sram cell is made up of two driving transistorss, two load devices and two access transistors.The circuit of a traditional complete CMOS SRAM is shown in Figure 1.As shown in Figure 1, the first inverter INV1 and the second inverter INV2 constitute latch, and INV1 and INV2 are driven by access transistor TA1 and TA2 respectively selectively.INV1 comprises the first load PMOS pipe TP1 and the first driving N metal-oxide-semiconductor TN1, and INV2 comprises the second load PMOS pipe TP2 and the second driving N metal-oxide-semiconductor TN2.Wherein, the source electrode of TP1 and TP2 links to each other with power vd D, and the drain electrode of TP1 links to each other with the drain electrode of TN1 and obtains the S1 point, and the drain electrode of TP2 links to each other with the drain electrode of TN2 and obtains the S2 point, the grid of TP1 links to each other with the grid of TN1 and is connected to the S1 point, and the grid of TP2 links to each other with the grid of TN2 and is connected to the S1 point.The grid of first access NMOS pipe TA1 links to each other with word line WL, and its source electrode links to each other with bit line BL, and its drain electrode links to each other with the S1 point.Similarly, the grid of second access NMOS pipe TA2 links to each other with word line, and DBL's its source electrode non-with bit line (Bit Line Bar) links to each other, and its drain electrode links to each other with the S2 point.Herein, the signal and the BL of DBL transmission are anti-phase.
In the operation of aforesaid complete CMOS sram cell, if word line WL is a high level, access NMOS pipe TA1 and TA2 conducting, therefore, the signal of bit line BL and the non-DBL of bit line is sent to worker NV1 and worker NV2 respectively, makes writing or reading and carried out of data.
When on the body silicon substrate, forming traditional complete CMOS SRAM, just can produce following problem.Nmos pass transistor needs P trap active area, and the PMOS transistor needs N trap active area.But when a N trap and P trap when disposed adjacent one another, may produce what is called " breech lock (latch-up) phenomenon.Thereby, between the source in the N trap/drain region P+ and the P trap, and must be isolated at a certain distance between the source in the P trap/drain region N+ and the N trap, that is to say, utilize an enough big distance to prevent latch-up.And this distance finally makes the chip size of SRAM increase.
Please referring to Fig. 2, the cross-sectional view when Fig. 2 is integrated on silicon-on-insulator (SOI) substrate for traditional cmos SRAM.SOI (Silicon On Insulator) is meant soi process.In the SOI technology, device only is manufactured in the very thin silicon fiml in top layer, separated by one deck buried oxidation layer between device and the substrate, this just structure makes the SOI skill state to have had the incomparable advantage of body silicon: parasitic capacitance is little, makes the SOI device have high-speed and low-power consumption; The full dielectric isolation of SOI cmos device has thoroughly been eliminated the parasitic door lock effect of body silicon CMOS device; The full dielectric isolation of SOI makes SOI technology integration density height and radiation-resisting performance good.As shown in Figure 2, when traditional cmos SRAM was integrated on silicon-on-insulator (SOI) substrate, transistor all was formed among the island district (Island) on the SOI substrate, formed STI between the district of island and isolated, and can not produce as the latch-up in the body silicon substrate.But, when the substrate that is adopted is partial depletion SOI, can form a tagma 100 under the transistorized grid, owing to this tagma current potential can change along with the difference of transistor operating state, promptly produce so-called " floater effect ", thereby influence transistorized performance.When traditional complete CMOS SRAM is integrated in PD SOI (partial depletion SOI) substrate, it is more obvious that this floater effect can embody, influence the performance of memory cell, such as increasing on the dynamic insulation body static RAM operating current on the silicon substrate etc., thereby influence the power consumption characteristics of sram chip.
In order to solve the floater effect of SOI technology, please referring to Fig. 3, prior art adopts the method for body contact (body contact) that " body " connect fixed potential (source end or ground) usually, as shown in Figure 3, the end at each transistor source 110 of being formed in the static RAM on the silicon-on-insulator substrate of prior art all needs that form and the injection region 120 identical doping type in tagma to link to each other with tagma below the grid, during cmos device work, the charge carrier of tagma accumulation is released by these injection region 120 passages, reaches the purpose that reduces body potential.But adopt this method technological process complicated, ghost effect increases, and has reduced the part electric property simultaneously and has increased device area.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of static RAM and manufacture method that is formed on the silicon-on-insulator substrate, the problem of the floater effect that exists with the static RAM that solves on the silicon-on-insulator substrate.
For solving the problems of the technologies described above, the invention provides a kind of static RAM that is formed on the silicon-on-insulator substrate, comprise a plurality of memory cell, described each storage cell comprises:
The first and second access nmos pass transistors;
The first driving N MOS transistor and the first load PMOS transistor, those transistors constitute first inverter, and its operation according to the second access nmos pass transistor is driven selectively; And
The second driving N MOS transistor and the second load PMOS transistor, those transistors constitute second inverter, and its operation according to the first access nmos pass transistor is driven selectively;
Described transistor all is formed on the active area of SOI substrate, and described active area comprises tagma, source region and drain region;
In described each memory cell and between described each memory cell, have fleet plough groove isolation structure between the adjacent dissimilar transistor, described fleet plough groove isolation structure contacts with the buried insulator layer of described SOI substrate; Has super fleet plough groove isolation structure between the transistor of adjacent same type, described super fleet plough groove isolation structure is opened the part active area isolation between the described adjacent same type transistor, make the source/drain regions between the described adjacent same type transistor be kept apart, and its tagma communicate by described super fleet plough groove isolation structure; Inject that to be formed with doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type in the active area on the tagma that communicates in described a plurality of memory cell by ion.
Optionally, the thickness of described super fleet plough groove isolation structure is 1500 dust to 2500 dusts.
The present invention also provides a kind of manufacture method that is formed at the static RAM on the silicon-on-insulator substrate, may further comprise the steps:
Step 2 is made fleet plough groove isolation structure on the silicon fiml of described SOI substrate, described fleet plough groove isolation structure contacts with described buried insulator layer;
Step 3 is made super fleet plough groove isolation structure again in the SOI substrate between described two fleet plough groove isolation structures, also remain with certain thickness described silicon fiml under the described super fleet plough groove isolation structure, and it does not contact with described buried insulator layer;
Step 4, on the SOI substrate between described fleet plough groove isolation structure and the described super fleet plough groove isolation structure, form transistor, transistor between described fleet plough groove isolation structure is the transistor of same type, and the transistor that is positioned at described fleet plough groove isolation structure both sides is dissimilar transistor; In the described transistorized active area formation source drain region and tagma;
Step 5, carrying out ion in the active area on the tagma that communicates in described a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type.
Optionally, the thickness of described super fleet plough groove isolation structure is 1500 dust to 2500 dusts.
The present invention also provides a kind of manufacture method that is formed at the static RAM on the silicon-on-insulator substrate, may further comprise the steps:
Step 2 is made super fleet plough groove isolation structure on the silicon fiml of described SOI substrate, also remain with certain thickness described silicon fiml under the described super fleet plough groove isolation structure, and it does not contact with described buried insulator layer;
Step 3 is made fleet plough groove isolation structure again on the SOI substrate between described two super fleet plough groove isolation structures, described fleet plough groove isolation structure contacts with described buried insulator layer;
Step 4, on the SOI substrate between described fleet plough groove isolation structure and the described super fleet plough groove isolation structure, form transistor, transistor between described fleet plough groove isolation structure is the transistor of same type, and the transistor that is positioned at described fleet plough groove isolation structure both sides is dissimilar transistor; In the described transistorized active area formation source drain region and tagma;
Step 5, carrying out ion in the active area on the tagma that communicates in described a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type.
Optionally, the thickness of described super fleet plough groove isolation structure is 1500 dust to 2500 dusts.
Static RAM and the manufacture method that is formed on the silicon-on-insulator substrate provided by the invention, between adjacent dissimilar transistors, adopt shallow trench isolation from, adjacent dissimilar transistorized active area is isolated fully, can not produce as the latch-up in the body silicon substrate; Between adjacent same type transistor, adopt simultaneously super shallow trench isolation from, make the tagma between the adjacent same type transistor communicate, carrying out ion in the active area on the tagma that communicates in a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type, each draw-out area, tagma can eliminate with its contacted a plurality of memory cell in the communicate floater effect in tagma.The static RAM that is formed on the silicon-on-insulator substrate of the present invention has effectively reduced the number of draw-out area, tagma, therefore can effectively reduce device area, has also eliminated the floater effect in tagma simultaneously.
Description of drawings
Fig. 1 is the circuit connection diagram of traditional CMOS SRAM;
Cross-sectional view when Fig. 2 is integrated on silicon-on-insulator (SOI) substrate for traditional cmos SRAM;
Fig. 3 suppresses the CMOS SRAM plan structure schematic diagram of floater effect for prior art adopts the body contact method;
Fig. 4 is the cross-sectional view that is formed at the static RAM on the silicon-on-insulator substrate of the present invention;
Fig. 5 is the plan structure schematic diagram that is formed at the static RAM on the silicon-on-insulator substrate of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Static RAM and the manufacture method that is formed on the silicon-on-insulator substrate provided by the invention can utilize multiple substitute mode to realize; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention undoubtedly.
Secondly, the present invention utilizes schematic diagram to describe in detail, and when the embodiment of the invention was described in detail in detail, for convenience of explanation, schematic diagram was disobeyed the local amplification of general ratio, should be with this as limitation of the invention.
Please referring to Fig. 4 and Fig. 5, Fig. 4 is the cross-sectional view that is formed at the static RAM on the silicon-on-insulator substrate of the present invention; Fig. 5 is the plan structure schematic diagram that is formed at the static RAM on the silicon-on-insulator substrate of the present invention.
As Fig. 4 and shown in Figure 5, the static RAM that is formed on the silicon-on-insulator substrate of the present invention comprises a plurality of memory cell;
Described each storage cell comprises:
The first and second access nmos pass transistors;
The first driving N MOS transistor and the first load PMOS transistor, those transistors constitute first inverter, and its operation according to the second access nmos pass transistor is driven selectively; And
The second driving N MOS transistor and the second load PMOS transistor, those transistors constitute second inverter, and its operation according to the first access nmos pass transistor is driven selectively;
Described transistor all is formed on the active area 203 of SOI substrate, described active area 203 comprise tagma 203a, source drain region 203b;
Wherein, in described each memory cell and between described each memory cell, have fleet plough groove isolation structure (STI) 210 between the adjacent dissimilar transistor (nmos pass transistor and PMOS transistor), described fleet plough groove isolation structure 210 contacts with the buried insulator layer 202 of described SOI substrate; (promptly between two nmos pass transistors or between two PMOS transistors) has super fleet plough groove isolation structure (VSTI) 220 between the transistor of adjacent same type, described super fleet plough groove isolation structure 220 is kept apart the part active area 203 between the described adjacent same type transistor, make the source/drain region 203b between the described adjacent same type transistor be kept apart, and its tagma 203a communicate by described super fleet plough groove isolation structure; Inject that to be formed with doping type identical and with draw-out area, contacted tagma, its tagma (not shown) with its tagma doping type in the active area on the tagma 203a that communicates in described a plurality of memory cell by ion.
The thickness of described super fleet plough groove isolation structure is 1500 dust to 2500 dusts.
Please, the invention provides a kind of manufacture method that is formed at the static RAM on the silicon-on-insulator substrate, may further comprise the steps in conjunction with referring to Fig. 4 and Fig. 5:
Step 2 is made fleet plough groove isolation structure (STI) 210 on the silicon fiml of described SOI substrate, described fleet plough groove isolation structure 210 contacts with described buried insulator layer 202;
Step 3, make super fleet plough groove isolation structure (VSTI) 220 in the SOI substrate 200 between described two fleet plough groove isolation structures 210 again, described super fleet plough groove isolation structure also remains with certain thickness described silicon fiml for 220 times, and it does not contact with described buried insulator layer 202;
Step 4, on the SOI substrate 200 between described fleet plough groove isolation structure 210 and the described super fleet plough groove isolation structure 220, form transistor according to conventional method, transistor between described fleet plough groove isolation structure 210 is the transistor of same type, and the transistor that is positioned at described fleet plough groove isolation structure 210 both sides is dissimilar transistor; In the described transistorized active area 203 the formation sources drain region 203b and tagma 203a;
Because there is certain thickness tagma 203a for 220 times in described super fleet plough groove isolation structure, the situation that in the transistor that forms, exists two or more transistorized tagma 203a to communicate then;
Step 5, carrying out ion in the active area on the tagma 203a that communicates in described a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type.
The present invention also provides a kind of manufacture method that is formed at the static RAM on the silicon-on-insulator substrate, may further comprise the steps:
Step 2 is made super fleet plough groove isolation structure (VSTI) 220 on the silicon fiml of described SOI substrate 200, described super fleet plough groove isolation structure also remains with certain thickness described silicon fiml for 220 times, and it does not contact with described buried insulator layer 202;
Step 3 is made fleet plough groove isolation structure (STI) 210 again on the SOI substrate 200 between described two super fleet plough groove isolation structures 220, described fleet plough groove isolation structure 210 contacts with described buried insulator layer 202;
Step 4, on the SOI substrate between described fleet plough groove isolation structure 210 and the described super fleet plough groove isolation structure 220, form transistor according to conventional method, transistor between described fleet plough groove isolation structure 210 is the transistor of same type, and the transistor that is positioned at described fleet plough groove isolation structure 210 both sides is dissimilar transistor; In the described transistorized active area 203 the formation sources drain region 203b and tagma 203a;
Because there is certain thickness tagma 203a for 220 times in described super fleet plough groove isolation structure, the situation that in the transistor that forms, exists two or more transistorized tagma 203a to communicate then;
Step 5, carrying out ion in the active area on the tagma 203a that communicates in described a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type.
Static RAM and the manufacture method that is formed on the silicon-on-insulator substrate provided by the invention, between adjacent dissimilar transistors, adopt shallow trench isolation from, adjacent dissimilar transistorized active area is isolated fully, can not produce as the latch-up in the body silicon substrate; Between adjacent same type transistor, adopt simultaneously super shallow trench isolation from, make the tagma between the adjacent same type transistor communicate, carrying out ion in the active area on the tagma that communicates in a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type, each draw-out area, tagma can eliminate with its contacted a plurality of memory cell in the communicate floater effect in tagma.The static RAM that is formed on the silicon-on-insulator substrate of the present invention has effectively reduced the number of draw-out area, tagma, therefore can effectively reduce device area, has also eliminated the floater effect in tagma simultaneously.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. a static RAM that is formed on the silicon-on-insulator substrate comprises a plurality of memory cell, and described each storage cell comprises:
The first and second access nmos pass transistors;
The first driving N MOS transistor and the first load PMOS transistor, those transistors constitute first inverter, and its operation according to the second access nmos pass transistor is driven selectively; And
The second driving N MOS transistor and the second load PMOS transistor, those transistors constitute second inverter, and its operation according to the first access nmos pass transistor is driven selectively;
Described transistor all is formed on the active area of SOI substrate, and described active area comprises tagma, source region and drain region; It is characterized in that,
In described each memory cell and between described each memory cell, have fleet plough groove isolation structure between the adjacent dissimilar transistor, described fleet plough groove isolation structure contacts with the buried insulator layer of described SOI substrate; Has super fleet plough groove isolation structure between the transistor of adjacent same type, described super fleet plough groove isolation structure is opened the part active area isolation between the described adjacent same type transistor, make the source/drain regions between the described adjacent same type transistor be kept apart, and its tagma communicate by described super fleet plough groove isolation structure; Inject that to be formed with doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type in the active area on the tagma that communicates in described a plurality of memory cell by ion.
2. the static RAM that is formed on the silicon-on-insulator substrate as claimed in claim 1 is characterized in that, the thickness of described super fleet plough groove isolation structure is 1500 dust to 2500 dusts.
3. a manufacture method that is formed at the static RAM on the silicon-on-insulator substrate is characterized in that, may further comprise the steps:
Step 1 provides SOI substrate, and described SOI substrate comprises processed wafer, buried insulator layer and silicon fiml;
Step 2 is made fleet plough groove isolation structure on the silicon fiml of described SOI substrate, described fleet plough groove isolation structure contacts with described buried insulator layer;
Step 3 is made super fleet plough groove isolation structure again in the SOI substrate between described two fleet plough groove isolation structures, also remain with certain thickness described silicon fiml under the described super fleet plough groove isolation structure, and it does not contact with described buried insulator layer;
Step 4, on the SOI substrate between described fleet plough groove isolation structure and the described super fleet plough groove isolation structure, form transistor, transistor between described fleet plough groove isolation structure is the transistor of same type, and the transistor that is positioned at described fleet plough groove isolation structure both sides is dissimilar transistor; In the described transistorized active area formation source drain region and tagma;
Step 5, carrying out ion in the active area on the tagma that communicates in described a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type.
4. the static RAM that is formed on the silicon-on-insulator substrate as claimed in claim 3 is characterized in that, the thickness of described super fleet plough groove isolation structure is 1500 dust to 2500 dusts.
5. a manufacture method that is formed at the static RAM on the silicon-on-insulator substrate is characterized in that, may further comprise the steps:
Step 1 provides SOI substrate, and described SOI substrate comprises processed wafer, buried insulator layer and silicon fiml;
Step 2 is made super fleet plough groove isolation structure on the silicon fiml of described SOI substrate, also remain with certain thickness described silicon fiml under the described super fleet plough groove isolation structure, and it does not contact with described buried insulator layer;
Step 3 is made fleet plough groove isolation structure again on the SOI substrate between described two super fleet plough groove isolation structures, described fleet plough groove isolation structure contacts with described buried insulator layer;
Step 4, on the SOI substrate between described fleet plough groove isolation structure and the described super fleet plough groove isolation structure, form transistor, transistor between described fleet plough groove isolation structure is the transistor of same type, and the transistor that is positioned at described fleet plough groove isolation structure both sides is dissimilar transistor; In the described transistorized active area formation source drain region and tagma;
Step 5, carrying out ion in the active area on the tagma that communicates in described a plurality of memory cell, inject to form doping type identical and with draw-out area, contacted tagma, its tagma with its tagma doping type.
6. the static RAM that is formed on the silicon-on-insulator substrate as claimed in claim 5 is characterized in that, the thickness of described super fleet plough groove isolation structure is 1500 dust to 2500 dusts.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102339836A (en) * | 2011-09-28 | 2012-02-01 | 上海宏力半导体制造有限公司 | Silicon on insulator device |
| CN103000518A (en) * | 2011-09-09 | 2013-03-27 | 联华电子股份有限公司 | Method for forming non-planar transistor |
| CN103000518B (en) * | 2011-09-09 | 2016-12-14 | 联华电子股份有限公司 | The method forming non-planar transistor |
| CN106952914A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI single port statics random-access memory unit and preparation method thereof |
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| US20020112137A1 (en) * | 2000-12-31 | 2002-08-15 | Texas Instruments Incorporated | Partial trench body ties in sram cell |
| CN1507035A (en) * | 2002-12-11 | 2004-06-23 | �Ҵ���˾ | Longitudinal static random access storage unit device and its forming method |
| CN1992280A (en) * | 2005-12-30 | 2007-07-04 | 中国科学院半导体研究所 | Static random access memory formed on PD SOI substrate and manufacturing method thereof |
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| US20020112137A1 (en) * | 2000-12-31 | 2002-08-15 | Texas Instruments Incorporated | Partial trench body ties in sram cell |
| CN1507035A (en) * | 2002-12-11 | 2004-06-23 | �Ҵ���˾ | Longitudinal static random access storage unit device and its forming method |
| CN1992280A (en) * | 2005-12-30 | 2007-07-04 | 中国科学院半导体研究所 | Static random access memory formed on PD SOI substrate and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000518A (en) * | 2011-09-09 | 2013-03-27 | 联华电子股份有限公司 | Method for forming non-planar transistor |
| CN103000518B (en) * | 2011-09-09 | 2016-12-14 | 联华电子股份有限公司 | The method forming non-planar transistor |
| CN102339836A (en) * | 2011-09-28 | 2012-02-01 | 上海宏力半导体制造有限公司 | Silicon on insulator device |
| CN102339836B (en) * | 2011-09-28 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | SOI device |
| CN106952914A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI single port statics random-access memory unit and preparation method thereof |
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| CN102176455B (en) | 2016-08-10 |
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