CN103000518B - The method forming non-planar transistor - Google Patents
The method forming non-planar transistor Download PDFInfo
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- CN103000518B CN103000518B CN201110266577.3A CN201110266577A CN103000518B CN 103000518 B CN103000518 B CN 103000518B CN 201110266577 A CN201110266577 A CN 201110266577A CN 103000518 B CN103000518 B CN 103000518B
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- 238000002955 isolation Methods 0.000 claims abstract description 41
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- 239000002184 metal Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 61
- 238000000059 patterning Methods 0.000 description 17
- 239000007800 oxidant agent Substances 0.000 description 16
- 230000001590 oxidative Effects 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- -1 silicon germanium Chemical compound 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N Hafnium(IV) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
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- 235000012239 silicon dioxide Nutrition 0.000 description 3
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- 210000003229 CMP Anatomy 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N Lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N Silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N Strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N Tantalum pentoxide Chemical compound O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N al2o3 Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910015846 BaxSr1-xTiO3 Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N HCl Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N Hafnium Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- VCFZGYGRRNTEGX-UHFFFAOYSA-N Hafnium(IV) silicate Chemical compound [Hf+4].[O-][Si]([O-])([O-])[O-] VCFZGYGRRNTEGX-UHFFFAOYSA-N 0.000 description 1
- 229910020696 PbZrxTi1−xO3 Inorganic materials 0.000 description 1
- 240000005511 Pisonia aculeata Species 0.000 description 1
- 101700057336 RCA1 Proteins 0.000 description 1
- 101700076371 RCA2 Proteins 0.000 description 1
- 102100005127 RNF139 Human genes 0.000 description 1
- 101710030991 RNF139 Proteins 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 101700064602 YTA12 Proteins 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N Zirconium(IV) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- YIFVJYNWLCNYGB-UHFFFAOYSA-N [Si]=O.[Zr] Chemical compound [Si]=O.[Zr] YIFVJYNWLCNYGB-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910000167 hafnon Inorganic materials 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910001941 lanthanum oxide Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- TWXTWZIUMCFMSG-UHFFFAOYSA-N nitride(3-) Chemical compound [N-3] TWXTWZIUMCFMSG-UHFFFAOYSA-N 0.000 description 1
- 229910052813 nitrogen oxide Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- 230000002093 peripheral Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 101700017580 rca Proteins 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910052846 zircon Inorganic materials 0.000 description 1
Abstract
The present invention provides a kind of method forming non-planar transistor.First providing substrate, in substrate, definition has active area and surrounding zone.It is engaged in the active area of substrate and forms multiple an ultra shallow trench isolations.Then the part of each an ultra shallow trench isolations is removed, to expose the partial sidewall of substrate.On suprabasil active area and surrounding zone, form conductive layer, and cover the partial sidewall of substrate.Patterned conductive layer so that this conductive layer forms the grid of planar transistor in this surrounding zone, and is positioned in active area the grid concurrently forming at least one non-planar transistor.Source/drain is formed in the both sides of the grid of non-planar transistor.
Description
Technical field
The present invention relates to a kind of method making non-planar transistor structure, particularly relate to a kind of energy simultaneously
Form non-planar transistor and the method for planar transistor.
Background technology
In recent years, along with various consumption electronic products constantly towards miniaturization, semiconductor element sets
The size of meter the most constantly reduces, to meet high integration, the high-effect and trend of low power consumption and product need
Ask.
But, along with the miniaturization of electronic product, existing planar transistor (planar transistor)
Cannot meet the demand of product.Therefore, a kind of non-planar transistor (non-planar) is developed at present
Fin transistor (Fin-FET) technology, its have solid grid groove (channel) structure, can be effective
Reduce the electric leakage of substrate, reduce short-channel effect, and there is higher driving electric current.But owing to fin-shaped is brilliant
Body pipe is belonging to the structure of solid, and relatively traditional structure is complicated, and manufacture difficulty is the most higher, be commonly
Formed, to be compatible to existing silicon base technique in silicon insulation (silicon-on-insulator, SOI) substrate
Then there is certain difficulty.Further, owing to the preparation method of fin transistor is the most special, because of and existing plane
When transistor is integrated, also can run into certain problem.
Summary of the invention
The present invention is in being to provide a kind of method concurrently forming non-planar transistor and planar transistor.
According to embodiment, the present invention provides a kind of method forming non-planar transistor.First substrate is provided,
In substrate, definition has active area and surrounding zone.Then in the active area of substrate, form multiple an ultra shallow groove
Isolation.Then an ultra shallow trench isolations of part is removed, to expose a part of sidewall of substrate.In substrate
On active area and surrounding zone on form conductive layer, and cover the partial sidewall of substrate.Patterning is led
Electric layer so that this conductive layer forms the grid of planar transistor in this surrounding zone, and is positioned in active area
Concurrently form the grid of at least one non-planar transistor.In fin-shaped electrode grid both sides formed source electrode/
Drain electrode.
The invention provides a kind of grid only needing one photomask can simultaneously define planar transistor
Pole and the method for non-planar transistor, and both have the grid of identical level height, technique is simple.
Additionally, the present invention also incorporate in active area formed an ultra shallow trench isolation process and in isolation area shape
The method becoming shallow trench isolation, and owing to being all to utilize same mask layer to carry out figure transfer, not
Integrated artistic can be affected.
Accompanying drawing explanation
Fig. 1 to Figure 10 depicts the present invention and forms the step schematic diagram of non-planar transistor.
Description of reference numerals
300 substrate 314 second grooves
301 active area 316 second insulating barriers
302 laying 317 an ultra shallow trench isolations
303 isolation areas 318 the 3rd pattern photoresist oxidant layer
304 mask layer 319 dielectric layers
305 surrounding zone 320 conductive layers
306 first patterning photoresist oxidant layer 321 fin structures
The grid of 308 first groove 322 planar transistors
310 first insulating barrier 323 source/drains
311 shallow trenchs isolate the grid of 324 non-planar transistors
Detailed description of the invention
For making the those skilled in the art of the technical field of the invention can be further understood that the present invention, hereafter
Spy enumerates several preferred embodiments of the present invention, and coordinates accompanying drawing, describes the constitution content of the present invention in detail
And the effect to be reached.
Refer to Fig. 1 to Figure 10, the depicted step schematic diagram forming non-planar transistor for the present invention.
As it is shown in figure 1, first provide substrate 300, substrate 300 can be silicon base (silicon substrate),
Epitaxial silicon (epitaxial silicon substrate), silicon germanium semiconductor substrate (silicon germanium
Substrate), silicon carbide substrate (silicon carbide substrate) or silicon-on-insulator
(silicon-on-insulator, SOI) substrate etc., but be not limited with above-mentioned.Define active in substrate 300
District 301, the isolation area 303 surrounding active area 301 and surrounding zone 305.Active area 301 is use
Produce the region of follow-up non-planar transistor, surrounding zone 305 the most e.g. high voltage device region, example
The peripheral circuit area (input/output region) of input/output in this way, follow-up can form operation wherein
At 1.8 volts or the MOS transistor of higher voltage, in an embodiment, these high pressure resistant MOS crystal
Pipe is planar transistor.Then, above substrate 300, laying 302 and mask layer 304 are formed.
In embodiments of the invention, laying 302 e.g. silicon dioxide layer (SiO2), and mask layer 304
E.g. nitride layer (SiN).The thickness of mask layer 304 is 60～150 angstroms (angstrom), is preferably
100 angstroms, and the thickness of laying 302 is 15～50 angstroms, preferably 20 angstroms.Then, at mask layer
The first patterning photoresist oxidant layer 306 is formed on 304.First patterning photoresist oxidant layer 306 can
To be single layer structure or multiple structure, in an embodiment, the first patterning photoresist oxidant layer 306 is such as
Anti-reflecting layer can be included.First patterning photoresist oxidant layer 306 has multiple opening, to expose
The mask layer 304 being positioned in isolation area 303.Then, with the first patterning photoresist oxidant layer 306 it is
Mask is etched technique, with etching mask layer 304, figure is transferred to mask layer 304 and liner
Layer 302, then removes the first patterning photoresist oxidant layer 306.
As in figure 2 it is shown, be etched technique to etch substrate 300 with mask layer 304 for mask, with
The isolation area 303 of substrate 300 is formed the first groove 308.The degree of depth of the first groove 308 is generally situated between
Between 2000～3000 angstroms.After defining the first groove 308, it is also possible to be optionally masked layer
304 retreat step (pull back) so that mask layer 304 is equidistantly away from the first groove 308.In enforcement
In example, it is also possible to be carried out step, such as, use RCA1 solution (NH4OH+H2O2+H2O) or
RCA2 solution (HCl+H2O2+H2O) bottom or sidewall to the first groove 308 are carried out.Or enter
Row situ steam growth step (in-situ stream growth, ISSG), with the bottom at the first groove 308
Or sidewall forms oxide layer (not shown).
As it is shown on figure 3, form the first insulating barrier 310 in substrate 300 comprehensively, and at least it is filled in the
In one groove 308.In embodiment, the first insulating barrier 310 e.g. silicon dioxide or other be suitable for
Insulant.Then, flatening process, such as CMP process (chemical are carried out
Mechanism polish, CMP) so that the end face of the first insulating barrier 310 and mask layer 304 is the neatest
Flat.
As shown in Figure 4, the mask layer 304 being positioned in active area 301 is patterned.Such as first in substrate 300
Upper formation second pattern photoresist oxidant layer (not shown) cover isolation area 303, surrounding zone 305 and
The active area 301 of part, and it is etched technique with the second patterning photoresist oxidant layer for mask, will
Figure is transferred to mask layer 304 and laying 302, then removes the second patterning photoresist oxidant layer.
Carry out another etch process the most again, with patterning after mask layer 304 and laying 302 as mask
A step etching of going forward side by side is to substrate 300, thus defines multiple second in the substrate 300 of active area 301
Groove 314.The degree of depth of the second groove 314 is generally between 200 to 500 angstroms, the most generally
Parallel, and can be arranged in active area 301.
Then as it is shown in figure 5, form the second insulating barrier 316 in substrate 300 so that it is be at least filled in
In second groove 314.Second insulating barrier 316 and the material of the first insulating barrier 310 can identical such as two
Silicon oxide but it also may differ.Finally, flatening process is carried out so that be positioned at the first groove 308
In the first insulating barrier 310 and be positioned at the second insulating barrier 316 and mask layer of each second groove 314
The end face of 304 generally flushes.Consequently, it is possible in active area 301, be positioned at the of isolation area 303
The first insulating barrier 310 in one groove 308 can be formed shallow trench isolation (shallow trench isolation,
STI) 311, and the second insulating barrier 316 being positioned at each second groove 314 of active area 301 i.e. defines
Multiple an ultra shallow trench isolations (very shallow trench isolation, VSTI) 317.Additionally, the present invention
After another enforcement example also can be initially formed these an ultra shallow trench isolations 317, recycle same layer mask layer
Forming these shallow trenchs isolation 311, this all should belong to the covering scope of the present invention.
As shown in Figure 6, substrate 300 is formed the 3rd patterning photoresist oxidant layer 318.In enforcement
In example, it is whole with expose in active area 301 that the 3rd patterning photoresist oxidant layer 318 has opening
The second insulating barrier 316.And in another preferred embodiment, as shown in Figure 6, the sidewall of opening can be slightly
Reduce slightly inwards, rest on the end face of an ultra shallow trench isolations 317 of outermost both sides, but will not stop
Stay on the mask layer 304 between two an ultra shallow trench isolations 317.
As it is shown in fig. 7, be etched technique with the 3rd patterning photoresist oxidant layer 318 for mask, with
Remove part the second insulating barrier 316 not covered by the 3rd patterning photoresist oxidant layer 318.Etching
The degree of depth less than the top surface of substrate 300, and can make the substrate 300 between each second groove 314 at least
Part exposes the fin structure 321 needed for sidewall, composition.
As shown in Figure 8, the 3rd patterning photoresist oxidant layer 318, mask layer 304 and lining are being removed
After bed course 302, substrate 300 sequentially forms dielectric layer 319 and conductive layer 320 comprehensively.Dielectric
Layer 319 can be such as silicon dioxide or dielectric layer with high dielectric constant.Dielectric layer with high dielectric constant example
As being selected from hafnium oxide (hafnium oxide, HfO2), hafnium silicate oxygen compound (hafnium silicon
Oxide, HfSiO4), hafnium silicate nitrogen oxide (hafnium silicon oxynitride, HfSiON), oxygen
Change aluminum (aluminum oxide, Al2O3), lanthana (lanthanum oxide, La2O3), tantalum oxide
(tantalum oxide, Ta2O5), yittrium oxide (yttrium oxide, Y2O3), zirconium oxide (zirconium oxide,
ZrO2), strontium titanates (strontium titanate oxide, SrTiO3), Zirconium orthosilicate. oxygen compound (zirconium
Silicon oxide, ZrSiO4), zirconic acid hafnium (hafnium zirconium oxide, HfZrO4), strontium bismuth tantalum oxygen
Compound (strontium bismuth tantalate, SrBi2Ta2O9, SBT), lead zirconate titanate (lead zirconate
Titanate, PbZrxTi1-xO3, PZT) and barium strontium (barium strontium titanate, BaxSr1-xTiO3,
BST) group formed.Conductive layer 320 e.g. polysilicon layer or metal level.Dielectric layer 319
Prepared by available chemical gaseous phase deposition or thermal oxide, and dielectric layer 319 and conductive layer 320 can be filled in
In each second groove 314 and touch the exposed top surface of substrate 300 and each sidewall, also can touch
The end face of each fin structure 321 and sidewall, and then it is effectively increased grid groove width.
The most as shown in Figures 9 and 10, patterned conductive layer 320.Conductive layer 320 after patterning
The grid 324 of at least one non-planar transistor can be formed in active area 301, and simultaneously in surrounding zone 305
The grid 322 of middle formation at least one planar transistor.In addition in embodiment, it is also possible at active area 301
Each grid both sides fin structure 321 in and the substrate 300 of surrounding zone 305 in, formed various suitable
When source/drain 323 doped region such as grade, and define the knot of non-planar transistor and planar transistor
Structure.And after completing non-planar transistor or planar transistor, it is also possible to include many steps, example
As formed stressor layers, or form metal silicide etc., repeated the most one by one at this.Scrutable
It is that aforesaid manufacture method is as example with the fin transistor (Fin-FET) in on-plane surface grid, but
In the case of not affecting present invention, also it is applicable to the making of other non-planar transistors.
It is noted that after Patternized technique, though the thickness of the grid 324 of non-planar transistor
Degree can be more than the thickness of grid 322 of planar transistor, but the grid 324 of non-planar transistor and flat
The grid 322 of junction transistor can have identical level height.Such it is advantageous in that, carries out if follow-up
During rearmounted metal gates (metal gate last) technique, carrying out flatening process to expose on-plane surface crystal
During the grid 322 of the grid 324 of pipe and planar transistor, less have the drop of height, and permissible
Expose both simultaneously.
For to sum up, the invention provides one only needs one photomask can define plane crystalline substance simultaneously
The grid of body pipe and the method for the grid with identical level height of non-planar transistor, technique letter
Single.Additionally, the present invention also incorporates forms an ultra shallow trench isolation process in active area and in isolation area
Middle formation shallow trench isolation method, and due to be all utilize same mask layer to carry out figure transfer,
Integrated artistic can't be affected.
The foregoing is only the preferred embodiments of the present invention, all equivalents done according to the claims in the present invention become
Change and modify, all should belong to the covering scope of the present invention.
Claims (8)
1. the method forming non-planar transistor, including:
Thering is provided substrate, in this substrate, definition has active area, surrounds the isolation area of this active area, and periphery
District, this active area is used to produce the region of non-planar transistor, and this surrounding zone is used to produce plane
The region of transistor；
Form mask layer on this substrate；
Pattern this mask layer, to form the first patterned mask layer in this isolation area；
With this first patterned mask layer for this substrate of mask etching, to form the first ditch in this isolation area
Groove, and in this first groove, insert the first insulating barrier to form shallow trench isolation；
Pattern this mask layer, to form the second patterned mask layer in this active area；
With this second patterned mask layer for this substrate of mask etching, to form at least one in this active area
Second groove, and in this second groove, insert the second insulating barrier to form an ultra shallow trench isolations, this ultra shallow
The degree of depth of trench isolations is less than the degree of depth of this shallow trench isolation；
Remove the part of each an ultra shallow trench isolations, so that this substrate structure exposed between each an ultra shallow trench isolations
Become multiple fin structure；
On this this active area suprabasil and this surrounding zone, form conductive layer, and cover each fin-shaped knot
Structure；
Pattern this conductive layer so that this conductive layer forms the grid of planar transistor in this surrounding zone,
And in this active area, form the grid of at least one non-planar transistor simultaneously；And
Source/drain is formed in this fin structure of these grid both sides of this non-planar transistor,
Wherein, this first patterned mask layer and this second patterned mask layer are shapes in different step
Become.
2. the method forming non-planar transistor as claimed in claim 1, wherein this conductive layer includes polysilicon
Or metal.
3. the method forming non-planar transistor as claimed in claim 1, after being initially formed the isolation of this shallow trench,
Form this ultra shallow trench isolations again.
4. the method forming non-planar transistor as claimed in claim 1, after being initially formed this ultra shallow trench isolations,
Form the isolation of this shallow trench again.
5. the method forming non-planar transistor as claimed in claim 1, wherein forms the plurality of fin structure
Step include:
Forming patterned mask layer in this substrate, this patterned mask layer has an opening, and this opening
Sidewall is correspondingly arranged in this ultra shallow trench isolations of this isolation area；And
It is etched technique for mask, to form the plurality of fin structure with this patterned mask layer.
6. the method forming non-planar transistor as claimed in claim 1, wherein this shallow trench is isolated in substrate
In the degree of depth be 2000 angstroms to 3000 angstroms.
7. the method forming non-planar transistor as claimed in claim 1, wherein this ultra shallow trench isolations is at base
The degree of depth at the end is 200 to 500 angstroms.
8. the method forming non-planar transistor as claimed in claim 1, wherein these grid of this planar transistor
Pole has identical level height with this grid of this non-planar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110266577.3A CN103000518B (en) | 2011-09-09 | The method forming non-planar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110266577.3A CN103000518B (en) | 2011-09-09 | The method forming non-planar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103000518A CN103000518A (en) | 2013-03-27 |
| CN103000518B true CN103000518B (en) | 2016-12-14 |
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|---|---|---|---|---|
| CN1819200A (en) * | 2005-01-27 | 2006-08-16 | 株式会社东芝 | Semiconductor device and method of manufacturing semiconductor device |
| CN101103463A (en) * | 2004-10-18 | 2008-01-09 | 国际商业机器公司 | Planar substrate devices integrated with finFETs and method of manufacture |
| CN101577278A (en) * | 2008-05-06 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| CN102176455A (en) * | 2011-03-15 | 2011-09-07 | 上海宏力半导体制造有限公司 | Static random access memory on silicon substrate of insulator and manufacturing method thereof |
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101103463A (en) * | 2004-10-18 | 2008-01-09 | 国际商业机器公司 | Planar substrate devices integrated with finFETs and method of manufacture |
| CN1819200A (en) * | 2005-01-27 | 2006-08-16 | 株式会社东芝 | Semiconductor device and method of manufacturing semiconductor device |
| CN101577278A (en) * | 2008-05-06 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| CN102176455A (en) * | 2011-03-15 | 2011-09-07 | 上海宏力半导体制造有限公司 | Static random access memory on silicon substrate of insulator and manufacturing method thereof |
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