TWI520226B - Semiconductor device and fabricating method thereof - Google Patents

Description

Semiconductor component and manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of forming a metal halide on a fin structure.

Metal-oxide-semiconductor (MOS) transistors are very important components in semiconductor integrated circuits, and the electrical performance of gate and source/drain is the key to the quality of MOS transistors. Conventional gates typically include a poly-silicon layer used as the primary conductive layer, and the source/drain electrodes are formed by doping regions of ions implanted on the single crystal germanium substrate, so A metal germanide layer is formed over the polysilicon layer and over the doped region to reduce the sheet resistance of the gate and increase the operating speed of the MOS transistor.

In recent years, non-planar crystals such as fin FETs have been developed, which can effectively increase the width of gate channels and improve the integration of integrated circuits, and thus are widely used in current semiconductors. industry. However, as the fin structure (fin) of the fin-shaped transistor becomes thinner and thinner, the technical difficulty of forming a metal telluride on the surface of the fin structure is also increased, and if excessive heating is performed during the formation of the metal telluride, This will cause the formed metal halide to penetrate into the germanium substrate, and increase the leakage current of the fin transistor, which seriously affects the quality of the fin transistor.

It is an object of the present invention to provide a method of fabricating a semiconductor device which forms a metal halide on the surface of a fin structure and which can effectively reduce the possibility of leakage current formation.

The present invention provides a method of fabricating a semiconductor device, comprising: providing a substrate having at least one fin structure, and then depositing a metal layer on the fin structure to form a metal telluride layer on the fin structure, After depositing the metal layer, the metal layer is directly removed without any heating step; after the metal layer is removed, a rapid heating process is performed.

The present invention provides a method of fabricating another semiconductor device, comprising providing a substrate having at least one fin structure, and then depositing a metal layer on the fin structure to form a metal halide layer on the fin structure. After depositing the metal layer, a low temperature heating step is performed, wherein the low temperature heating step has a temperature ranging from 80 ° C to 120 ° C, then the metal layer is removed, and a rapid heating process is performed.

The present invention further provides a semiconductor device structure including a substrate having at least one fin structure thereon, a metal telluride layer covering a top surface and two sidewalls of the fin structure, and the metal telluride layer having a uniform film thickness And a plurality of contacts on the metal halide layer.

In the process of forming a metal telluride, the present invention does not perform any heating step before removing the metal layer, or only performs a relatively low temperature heating step (80 ° C to 120 ° C) to form a very thin metal telluride on the fin. The surface of the structure, thus reducing the possibility of leakage current formation, thereby improving component performance.

Please refer to FIGS. 1-7, and FIGS. 1-7 are schematic diagrams showing the structure of a semiconductor device according to a first preferred embodiment of the present invention. First, as shown in FIG. 1, a substrate 100 is provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, or a silicon carbide substrate. The preferred embodiment of the present invention is exemplified by a bulk silicon substrate, but is not limited thereto. Next, a patterned mask layer 112 is formed over the substrate 100, and a patterned liner layer (not shown) is selectively formed between the substrate 100 and the patterned mask layer 112. In a preferred embodiment of the present invention, the patterned mask layer comprises various materials suitable for use as a hard mask, such as silicon nitride (SiN) or an advanced patterned film provided by Applied Materials (advanced). Pattern film, APF), etc., and the patterned liner layer may be, for example, a hafnium oxide layer (SiO ₂ ) or the like. Subsequently, a first etching process is performed with the patterned mask layer 112 as a mask to form at least one fin structure 110 on the substrate 100, each fin structure 110 having a width of about 10 nanometers (nm), and At the same time, a plurality of trenches 102 are formed in the substrate 100 around the fin structure 110.

Next, as shown in FIG. 2, a dielectric layer 114 is formed to cover the substrate 100 and the patterned mask layer 112, and fills the trenches 102. The dielectric layer 114 is then subjected to a planarization process, such as chemical mechanical polishing (CMP), and the patterned mask layer 112 is used as a stop layer to expose the patterned mask layer 112 to a flat surface. The surface of the dielectric layer 114. The dielectric layer 114 may be a dielectric material generally used to form shallow trench isolation (STI), which may be composed of a single layer or a plurality of layers of insulating materials. This is a general knowledge of those skilled in the art, and therefore will not be further described.

Then, as shown in FIG. 3, a portion of the dielectric layer 114 is removed by an etching process to form a shallow trench isolation (STI) 115 as the substrate 100 in each of the trenches 102 around the fin structure 110. The insulation between the upper fin structures 110. The etching process is not limited to the use of dry etching or wet etching or a combination thereof, and the dry etching conditions may be CF ₄ , O ₂ and Ar, and the wet etching conditions may be diluted hydrofluoric acid or the like. In addition, under appropriate conditions, in this embodiment, after the dielectric layer 114 covering the substrate 100 and the patterned mask layer 112 is formed, a portion of the dielectric layer 114 is directly removed by an etching process. A shallow trench isolation (STI) 115 is formed in a trench 102.

After the patterned mask layer 112 is removed, as shown in FIG. 4, a gate structure 124 is formed overlying the portion of the fin structure 110. The gate structure 124 includes a dielectric layer (not shown), a conductive layer (not shown), and a mask layer 125. The dielectric layer may include an oxide or a nitride, and the conductive layer may include polysilicon or The metal or the like, the mask layer may contain a nitride or an oxide or the like. In addition, the present embodiment can also be combined with a high-k first gate last process, a high-k last gate last process or a high-k last gate last process or The gate first process integrates the metal gate process of the front gate-high dielectric layer (high-k first), so that a lining can be selectively formed between the fin structure 110 and the dielectric layer. a pad layer (not shown), and the dielectric layer is preferably a high dielectric constant (high-k) material layer, which may be selected from hafnium oxide (HfO ₂ ), barium strontium sulphate. Hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), oxidation Tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium oxynitride (zirconium silicon oxide, ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), antimony Strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _{x )} A group consisting of Sr _1-x TiO ₃ , BST).

A sidewall 127 is then formed around the gate structure 124 to cover the side of the gate structure 124, and then the source/drain region 126 is formed by ion implantation on the fin structure 110 without being covered by the gate structure 124. In addition, an epitaxial layer may be selectively formed on the surface of the fin structure 110 before or after the source/drain region 126 is formed, or a part of the source/drain region may be removed first and then replaced by an epitaxial layer. The epitaxial layer may be, for example, germanium telluride (SiGe) or tantalum carbide (SiC), etc., and the epitaxial layer may be conformal, hexagonal, octagonal, or the like polygonal.

Please refer to FIG. 5, which is a schematic cross-sectional view taken along line AA' in FIG. 4. Taking an embodiment in which a conformal epitaxial layer 120 is formed on the surface of the fin structure 110 as an example, a metal layer 116 is deposited over the gate structure 124 and the fin structure 110, and when the metal layer 116 is deposited on the source/ On the surface of the drain region 126, a metal telluride layer 118 is formed at the interface between the metal layer 116 and the epitaxial layer 120 (or the fin structure 110), that is, the surface of the epitaxial layer 120 (or the fin) during deposition. The surface of the structure 110 is formed by depositing a very thin metal bismuth layer 118 having a thickness of only about 2 nm to 4 nm. The metal telluride 118 has a uniform film thickness covering the top surface of the fin structure 110. And two sidewalls, in the present invention, the metal telluride layer 118 is sufficient to effectively reduce the energy barrier difference between the metal and germanium interfaces, and improve the conduction efficiency between different materials. The metal layer 116 may be, for example, a material such as a nickel-platinum alloy (Ni/Pt), and the main component of the metal telluride layer 118 is, for example, Ni ₂ Si. Moreover, in the present embodiment, the epitaxial layer 120 covering the source/drain region 126 can be used to provide an additional source of germanium atoms for this self-aligned metal salicide process, without separately consuming the fin structure 110 or The germanium atom of the lower substrate 100, therefore, after the metal germanide 118 is formed, the fin structure 110 covered by the metal germanide 118 is not completely consumed. In other words, the fin structure 110 is still present in the metal telluride. Between the two side walls of the 118. In order to avoid an increase in leakage current of the semiconductor element after completion, it is possible to increase the gate channel width of the completed semiconductor element and to increase the carrier speed with a proper stress to the channel.

After the metal layer 116 is removed, as shown in FIG. 6, the metal telluride layer 118 is subjected to a rapid heating process 122, preferably at a temperature between 400 ° C and 600 ° C, to further reduce the metal telluride layer 118. The resistance value, for example, converts the composition inside the metal telluride layer 118 from Ni ₂ Si to NiSi.

It should be noted that in the self-aligned metal salicide process of the preferred embodiment, only one rapid heating process 122 is performed and is performed after the metal layer 116 is removed. Before the metal layer 116 is removed, the preferred embodiment does not perform any rapid heating process to avoid the formation of excessive metal germanium into the germanium substrate, resulting in an increase in leakage current of the fin transistor, which seriously affects the fin. The quality of the transistor. In other words, in the preferred embodiment of the present invention, in the process of forming the metal telluride layer 118, especially after depositing the metal layer 116 to remove the metal layer 116, no additional heating step is used, so the surface of the epitaxial layer 120 (or The metal telluride layer 118 formed on the surface of the fin structure 110 is extremely thin, so that excessive high temperature process during the formation of the metal telluride 118 can be effectively avoided, and the metal telluride 118 is continuously extended to the fin. The NiSi is converted inside the germanium structure 110 or in the germanium substrate, thereby causing a problem of excessive leakage current.

Then, as shown in FIG. 7, a dielectric layer 128 is deposited on the surface of the substrate 100, and covers the gate structure 124, the metal telluride layer 118 and the fin structure 110, and then forms a plurality of contacts 130 in the dielectric layer 128. Electrically connected to the gate structure 124 and the metal telluride layer 118 on the source/drain region 126, respectively. In addition, the preferred embodiment can also be applied in a post-contact process, that is, after the dielectric layer 128 covers the gate structure 124 and the fin structure 110, a plurality of dielectric layers 128 are formed. A contact hole (not shown) exposes the source/drain region 126, and then performs the self-aligned metal salicide process of the present invention, including successive steps of depositing a metal layer, removing the metal layer, and a rapid heating process, A thin metal tantalum layer is formed on a portion of the source/drain region exposed by the contact hole (not shown).

The different embodiments of the metal telluride layer of the present invention and the method for fabricating the same are described below, and for simplicity of explanation, the following description mainly focuses on the differences of the embodiments, and no longer focuses on the same. Overwrite the statement. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

8-9 are schematic views showing the structure of a semiconductor device according to a second preferred embodiment of the present invention. Referring to FIG. 8, the second preferred embodiment of the present invention has a substrate 100 having at least one fin structure 110 formed on the substrate, and then forming a gate structure, a mask layer and a sidewall portion. (not shown) on the fin structure 110, and the source/drain region 126 is formed on the surface of the fin structure 110 by ion implantation, and then covered with a metal layer 116 and a selective barrier cap layer (Fig. An epitaxial layer 120 is selectively formed on the surface of the fin structure 110 before the metal layer 116 is covered. The difference between the present embodiment and the first embodiment is that after depositing the metal layer 116 on the surface of the fin structure 110 or the surface of the epitaxial layer 120, a low temperature heating step 222 is additionally performed, which is different from the conventional manufacturing process. The heating temperature of the metal halide is lower, and the temperature of the conventional heating step is about 200 ° C, and the temperature of the low temperature heating step 222 of the present invention is only about 50 ° C to 150 ° C, preferably 80 ° C to 120 ° C. The second preferred embodiment of the present invention employs the low temperature heating step 222 to fine tune the thickness of the metal telluride layer 118 to increase the thickness of the metal telluride layer 118 by the low temperature heating step 222, but without excessive formation. The problem of large leakage current. The remaining steps and component use materials are the same as the first embodiment of the present invention. As shown in FIG. 9, the remaining steps are the same as in the first preferred embodiment, the metal layer 116 is removed, and then a rapid heating process 122 is performed again, and A dielectric layer is formed and contacted. Similarly, the semiconductor fabrication method of the present embodiment can also be applied to a plurality of fin-shaped components or post-contact processes, and the contacts can also be selected as columnar contacts or strip contacts.

In addition, the method of fabricating the semiconductor device of the present invention is not limited to being applied to only a single fin structure. In other words, when the substrate has a plurality of fin structures, the semiconductor device fabrication method of the present invention can simultaneously apply a plurality of fins. The structure is completed. In addition, the contact 130 mentioned in the present invention is not limited to a pole contact, but may also be a slot contact, and simultaneously spans a plurality of fin structures, for example, as the 10th. As shown in the figure, FIG. 10 is a schematic view showing the structure of a semiconductor device applied to a plurality of fin structures according to the present invention, which has a slot contact 140, which can simultaneously contact a plurality of fin structures, and the remaining components and steps are The same as the first preferred embodiment or the second preferred embodiment of the present invention, and details are not described herein again.

In summary, the present invention provides a method of fabricating a semiconductor device, characterized in that after the metal layer is covered on the fin structure, no additional heating step or a lower temperature heating step (80 ° C to 120 ° C) is performed. The thickness of the metal telluride layer formed on the surface of the fin structure 110 is controlled only in the range of 2 nm to 4 nm. At the same time, the additional heating step is omitted in the first preferred embodiment of the present invention, thereby reducing costs and increasing productivity. The metal telluride process of the invention can be widely applied to various semiconductor elements, improve the conductivity of the metal and germanium interface, and avoid the problem of excessive leakage current of the semiconductor element after completion, and greatly improve the process yield.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Base

102. . . ditch

110. . . Fin structure

112. . . Patterned mask layer

114. . . Dielectric layer

115. . . Shallow trench isolation (STI)

116. . . Metal layer

118. . . Metal telluride layer

120. . . Epitaxial layer

122. . . Rapid heating process

124. . . Gate structure

125. . . Mask layer

126. . . Source/bungee area

127. . . Side wall

128. . . Dielectric layer

130. . . First contact

140. . . Strip contact

222. . . Low temperature heating step

1 to 7 are views showing the structure of a semiconductor device according to a first preferred embodiment of the present invention.

8-9 are schematic views showing the structure of a semiconductor device according to a second preferred embodiment of the present invention.

Fig. 10 is a view showing the structure of a semiconductor device to which a plurality of fin structures are applied in the present invention.

100. . . Base

110. . . Fin structure

115. . . Shallow trench isolation (STI)

118. . . Metal telluride layer

120. . . Epitaxial layer

124. . . Gate structure

125. . . Mask layer

126. . . Source/bungee area

127. . . Side wall

128. . . Dielectric layer

130. . . First contact

Claims (20)

A method of fabricating a semiconductor device, comprising: providing a substrate having at least one fin structure; depositing a metal layer on the fin structure to form a metal telluride layer on the fin structure; After the metal layer, the metal layer is directly removed without any heating step; and after the metal layer is removed, a rapid heating process is performed. For example, the method for fabricating the semiconductor device of claim 1 further includes forming a shallow trench to surround the fin structure. The method for fabricating a semiconductor device according to claim 1, wherein the method further comprises forming an epitaxial layer on the surface of the fin structure before depositing the metal layer. The method for fabricating a semiconductor device according to claim 1, further comprising forming a gate structure on a portion of the fin structure. A method of fabricating a semiconductor device according to claim 4, wherein the gate structure comprises a polysilicon gate or a metal gate. The method for fabricating a semiconductor device according to claim 1, wherein the rapid heating process has a temperature ranging from 400 ° C to 600 ° C. The method for fabricating a semiconductor device according to claim 1, further comprising forming a plurality of contacts on the metal halide layer. A method of fabricating a semiconductor device according to claim 7 wherein the contact comprises a slot contact or a pole contact. A method of fabricating a semiconductor device, comprising: providing a substrate having at least one fin structure; depositing a metal layer on the fin structure to form a metal telluride layer on the fin structure; After the metal layer, a low temperature heating step is performed, wherein the low temperature heating step has a temperature ranging from 50 ° C to 150 ° C; the metal layer is removed; and a rapid heating process is performed. The method for fabricating a semiconductor device according to claim 9 of the patent application, further comprising forming a shallow trench to surround the fin structure. The method of fabricating a semiconductor device according to claim 9, wherein the method further comprises forming an epitaxial layer on the surface of the fin structure before depositing the metal layer. For example, the manufacturing method of the semiconductor component of the ninth application patent scope includes forming one The gate structure is on a portion of the fin structure. The method of fabricating a semiconductor device according to claim 12, wherein the gate structure comprises a polysilicon gate or a metal gate. The method for fabricating a semiconductor device according to claim 9 wherein the temperature of the rapid heating process ranges from 400 ° C to 600 ° C, and the temperature of the low temperature heating step is preferably between 80 ° C and 120 ° C. The method for fabricating a semiconductor device according to claim 9 of the patent application, further comprising forming a plurality of contacts on the metal halide layer. A method of fabricating a semiconductor device according to claim 15 wherein the contact comprises a slot contact or a pole contact. a semiconductor device structure comprising: a substrate having at least one fin structure; a metal telluride layer covering a top surface and two sidewalls of the fin structure, and the metal telluride layer has a uniform film thickness, and The metal telluride layer has a thickness between 2 and 4 nm; and a plurality of contacts are located on the metal halide layer. The semiconductor element structure of claim 17, wherein the fin structure Present between the two sidewalls of the metal telluride layer. The semiconductor component structure of claim 17, wherein the contact comprises a slot contact or a pole contact. The semiconductor device structure of claim 17, wherein the metal halide layer is located only between the fin structure and each of the contacts.