CN101009291A - A radiation-resisting BTS SOI CMOS part structure - Google Patents
A radiation-resisting BTS SOI CMOS part structure Download PDFInfo
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- CN101009291A CN101009291A CN 200610038106 CN200610038106A CN101009291A CN 101009291 A CN101009291 A CN 101009291A CN 200610038106 CN200610038106 CN 200610038106 CN 200610038106 A CN200610038106 A CN 200610038106A CN 101009291 A CN101009291 A CN 101009291A
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Abstract
A radiation-resistant BTS SOI CMOS apparatus structure relates to radiation-resistant SOI CMOS apparatus technique, specially a new radiation-resistant BTS SOI CMOS apparatus structure. The invention is imbursed by arming beforehand research item outlay of head fitting office. According to the design scheme provided in the invention, the middle part of the structure is polycrystal area, the right side of the polycrystal area is drain terminal, the left side of the polycrystal area is source terminal, it characterized in that: a drain terminal contact hole is at the drain terminal N+ source area, leading out wire is at the drain terminal contact hole, a source terminal contact hole is at the source terminal N+ source area, P+ source area is separately at the upper and lower side of the source terminal N+ source area, the left side of the source terminal N+ source area is P+ source area, two P+ source areas are lead out from P+ source area, two contacting holes are at the source terminal N+ source area and P+ source area, the source terminal N+ source area and two P+ source areas are connected together, there is also leading out wires at the contacting holes.
Description
Technical field
The present invention relates to radiation-resistant SOI (silicon on the insulator) CMOS (complementary type metal-oxide semiconductor fieldeffect transistor) device technology, particularly relate to a kind of new radiation-resisting BTS (source end body is drawn) SOI cmos device structure.
Background technology
Adopt the SOI CMOS integrated circuit of SIMOX (annotating oxygen isolates) SOI material preparation to become the main path that solves the high-performance anti-radiation very lagre scale integrated circuit (VLSIC).PD (part depletion) SOI cmos device and circuit are because its full dielectric isolation, source are omitted little, the no latch-up of living electric capacity, good advantages such as radiation resistance, become the major technique of producing radiation hardened integrated circuit, but it requires designs that body contact distinctive to solve " Kink (the unusual warpage that refers to the device curve of output) " effect problem is arranged.Traditional radiation-resistant SOI cmos device structure has BTS structure, H-type grid structure, T-type grid structure and ring-like grid structure, the BTS structure is not owing to there is limit, island (referring to does not have parasitic field edge pipe), domain is simple, wiring is convenient, radiation resistance is good, and is widely adopted, but the device architecture area is bigger than normal, make that in the same level processes, the scale of circuit is restricted.
Traditional BTS SOI nmos device structure such as Fig. 1,3 is polycrystalline, three drain terminal contact holes 4 are arranged on the drain terminal N+ active area 1, after linking together by the metal aluminum steel, three drain terminal contact holes 4 draw, end in contact hole, a source 4 is arranged on the source end N+ active area 1, the both sides of source end N+ active area 1 respectively have on 2, two P+ active areas 2 of a P+ active area contact hole 4 are respectively arranged, drawing after totally three contact holes 4 link together by the metal aluminum steel on source end N+ active area 1 and two the P+ active areas 2.
Traditional BTS SOI PMOS device architecture such as Fig. 3, polycrystalline is 3 districts, three drain terminal contact holes 4 are arranged on the drain terminal P+ active area 2, after linking together by the metal aluminum steel, three drain terminal contact holes 4 draw, end in contact hole, a source 4 is arranged on the source end P+ active area 2, the both sides of source end P+ active area 2 respectively have on 1, two N+ active area 1 of a N+ active area contact hole 4 are respectively arranged, drawing after totally three contact holes 4 link together by the metal aluminum steel on source end P+ active area 2 and two the N+ active areas 1.
Goal of the invention
One of purpose of the present invention is to provide a kind of new radiation-resisting BTS SOI cmos device structure, is used for the design of radiation-resistant SOI circuit;
Two of purpose is to provide a kind of new radiation-resisting BTS SOI cmos device structure, keeping under the constant situation of device breadth length ratio, new radiation-resisting BTS SOI cmos device structure is dwindled medicine 20% than the single device architecture area of traditional B TS SOICMOS, and the element circuit of forming also can correspondingly dwindle;
Three of purpose is to adopt the radiation-resistant SOI integrated circuit that this structure can process scale be bigger on same technique platform, and do not need to increase any operation, remedy increase problem, and capability of resistance to radiation is constant because of the circuit chip area that needs anti-radiation requirement to bring.
According to design provided by the present invention, at the middle part of structure is polycrystalline, on the right side of polycrystalline is drain terminal, in the left side of polycrystalline is the source end, it is characterized in that: a drain terminal contact hole is arranged on drain terminal N+ active area, draw lead on the drain terminal contact hole, end in contact hole, a source is arranged on the end N+ active area of source, respectively there is a P+ active area both sides up and down at source end N+ active area, left side at source end N+ active area is the P+ active area, two P+ active areas are drawn by the P+ active area, two and contact hole are together arranged on source end N+ active area and the P+ active area, source end N+ active area and two P+ active areas are linked together, on this and together contact hole, draw lead equally.
Perhaps, a kind of radiation-resisting BTS SOI cmos device structure, at the middle part of structure is polycrystalline, on the right side of polycrystalline is drain terminal, in the left side of polycrystalline is the source end, it is characterized in that: a drain terminal contact hole is arranged on drain terminal P+ active area, draw lead on the drain terminal contact hole, end in contact hole, a source is arranged on the end P+ active area of source, respectively there is a N+ active area both sides up and down at source end P+ active area, left side at source end P+ active area is the N+ active area, two N+ active areas are drawn by the N+ active area, two and together contact hole are arranged on source end N+ active area and the P+ active area, source end P+ active area and two N+ active areas are linked together, also draw lead equally on together the contact hole at this.
Advantage of the present invention is: 1, new radiation-resisting BTS SOI cmos device structure of the present invention is under the constant situation of device breadth length ratio, the new construction that provides dwindles about 20% than the single device architecture area of traditional SOI CMOS, the element circuit of composition can correspondingly dwindle; 2, the radiation-resistant SOI integrated circuit that new construction of the present invention can process scale be bigger on same technique platform, compare with traditional radiation-resisting BTS SOI cmos device technology, not needing increases any operation, thereby remedies because the circuit chip area that needs anti-radiation requirement to bring increases problem; 3, new construction of the present invention and traditional radiation-resisting BTS SOI cmos device are if adopt same process, and the radioresistance level of new construction can reach the level of traditional radiation-resisting BTS SOI cmos device.
Description of drawings
Fig. 1 is this traditional radiation-resisting BTS SOI NMOS structure.
Fig. 2 is a radiation-resistant SOI NMOS structure of the present invention.
Fig. 3 is traditional radiation-resisting BTS SOI NMOS structure.
Fig. 4 is a radiation-resistant SOI NMOS structure of the present invention.
Fig. 5 is the phase inverter of traditional radiation-resisting BTS structure.
The phase inverter of Fig. 6 radiation-resisting BTS structure of the present invention.
Embodiment
As shown in Figure 2: at the middle part of structure is polycrystalline 3, on the right side of polycrystalline 3 is drain terminal, in the left side of polycrystalline 3 is the source end, a drain terminal contact hole 4 is arranged on drain terminal N+ active area 1, draw lead on the drain terminal contact hole 4, end in contact hole, a source 4 is arranged on source end N+ active area 1, respectively there is a P+ active area 5 both sides up and down at source end N+ active area 1, left side at source end N+ active area 1 is a P+ active area 2, two P+ active areas 5 are drawn by P+ active area 2, two and contact hole 4 are together arranged on source end N+ active area 1 and the P+ active area 2, source end N+ active area 1 and two P+ active areas 5 are linked together, on this and together contact hole 4, draw lead equally.
The utility model also can adopt structure as shown in Figure 4, at the middle part of structure is polycrystalline 3, on the right side of polycrystalline 3 is drain terminal, in the left side of polycrystalline 3 is the source end, a drain terminal contact hole 4 is arranged on drain terminal P+ active area 2, draw lead on the drain terminal contact hole 4, end in contact hole, a source 4 is arranged on source end P+ active area 2, respectively there is a N+ active area 6 both sides up and down at source end P+ active area 2, left side at source end P+ active area 2 is a N+ active area 1, two N+ active areas 6 are drawn by N+ active area 1, two and contact hole 4 are together arranged on source end N+ active area 1 and the P+ active area 2, source end P+ active area 2 and two N+ active areas 6 are linked together, on this and together contact hole 4, draw lead equally.
The SOI CMOS technology that radiation-resisting BTS SOI CMOS structure of the present invention is based oneself upon does not adopt the Salicide technology, go in the technology of different stage, designs rule described in the schematic diagram is unified, specific as follows, base unit is λ: wherein, the polycrystalline width is λ, the contact hole dimension, lambda, polycrystalline covers place 0.6 λ, active area bag hole λ, and contact hole is λ apart from polycrystalline.
Traditional B TS SOI NMOS architecture schematic diagram is seen Fig. 1, for improving radiation resisting capability of device, adopts Wu Dao limit structure, N+ drain terminal width is 7 λ, and source end width is 7 λ, and the N+ effective width is 3 λ, it is the P+ district of 2 λ that respectively there is width on both sides, makes the NMOS pipe not have the limit, island.In the shared length of directions X is 3 λ+λ+3 λ=7 λ, is 0.6 λ+2 λ+3 λ+2 λ+0.6 λ=8.2 λ at the shared height of Y direction, and then area occupied is A=57.4 λ
2
New BTS SOI NMOS architecture schematic diagram of the present invention is seen Fig. 2: N+ drain terminal width is 5 λ, and source end width is 5 λ, and the N+ effective width is 3 λ, and it is the P+ district of 1 λ that respectively there is width on both sides, makes the NMOS pipe not have the limit, island.In the shared length of directions X is 1.8 λ+1.8 λ+λ+3 λ=7.6 λ, is 0.6 λ+1 λ+3 λ+1 λ+0.6 λ=6.2 λ at the shared height of Y direction, and then area occupied is A=47.12 λ
2
With regard to single BTS SOI nmos device, the area of new structure is 82% of a traditional structure.Traditional B TS SOI PMOS device architecture is seen Fig. 3, and new BTS SOI PMOS device architecture is seen Fig. 4.
Owing to need anti-radiation requirement, in traditional B TS SOI NMOS structure, on end both sides, the source of device P+ active area 2 is on one side arranged respectively, the body contact that realizes device like this is to eliminate " Kink " effect, and realized the Wu Dao limit of device, to improve the capability of resistance to radiation of device.In new BTS SOI NMOS structure, kept above design philosophy, the principle that body contact and Wu Dao limit are arranged that has promptly kept device, key is to have adopted on the structural design new method, in new construction, has adopted on end both sides, source does not have the P+ of contact hole 4 active area 5 to substitute the P+ active area 2 that contact hole 4 was arranged originally; Employing source end N+ active area 1 is realized being connected of P+ active area 5 with the butt hole of P+ active area 2, the contact hole 4 of special P+ active area 2 in the replace traditional structural; New structural design is like this compared with traditional structure and has been dwindled area significantly, and same design philosophy is applicable in the BTS SOI PMOS structure.
Applicating example
Adopt new radiation-resisting BTS SOI cmos device structure of the present invention, in circuit,, on the scaled down version area of pictural surface, can reach effect preferably if use rationally.As a phase inverter domain that adopts traditional structure to form sees Fig. 5, and area occupied is A=114.8 λ
2, a phase inverter domain that adopts new construction of the present invention to form is seen Fig. 5, area occupied is A=94.24 λ
2
Claims (2)
1, a kind of radiation-resisting BTS SOI cmos device structure, at the middle part of structure is polycrystalline (3), on the right side of polycrystalline (3) is drain terminal, in the left side of polycrystalline (3) is the source end, it is characterized in that: a drain terminal contact hole (4) is arranged on drain terminal N+ active area (1), the drain terminal contact hole is drawn lead on (4), end in contact hole, a source (4) is arranged on source end N+ active area (1), in the both sides up and down of source end N+ active area (1) a P+ active area (5) is arranged respectively, in the left side of source end N+ active area (1) is P+ active area (2), two P+ active areas (5) are drawn by P+ active area (2), two and contact hole (4) are together arranged on source end N+ active area (1) and the P+ active area (2), source end N+ active area (1) and two P+ active areas (5) are linked together, on this and contact hole (4) together, draw lead equally.
2, a kind of radiation-resisting BTS SOI cmos device structure, at the middle part of structure is polycrystalline (3), on the right side of polycrystalline (3) is drain terminal, in the left side of polycrystalline (3) is the source end, it is characterized in that: a drain terminal contact hole (4) is arranged on drain terminal P+ active area (2), the drain terminal contact hole is drawn lead on (4), end in contact hole, a source (4) is arranged on source end P+ active area (2), in the both sides up and down of source end P+ active area (2) a N+ active area (6) is arranged respectively, in the left side of source end P+ active area (2) is N+ active area (1), two N+ active areas (6) are drawn by N+ active area (1), two and contact hole (4) are together arranged on source end N+ active area (1) and the P+ active area (2), source end P+ active area (2) and two N+ active areas (6) are linked together, on this and contact hole (4) together, draw lead equally.
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| CN102629626A (en) * | 2011-02-04 | 2012-08-08 | 瑞萨电子株式会社 | Semiconductor device |
| CN103219384A (en) * | 2013-04-03 | 2013-07-24 | 北京大学 | Anti-single particle radiation multi-grid device and preparation method thereof |
| CN106952916A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI dual-port statics random-access memory unit and preparation method thereof |
| CN106952953A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI MOS devices of resistant to total dose effect and preparation method thereof |
| CN106952954A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI MOS devices and preparation method thereof |
| CN106952914A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI single port statics random-access memory unit and preparation method thereof |
| CN107516650A (en) * | 2016-06-17 | 2017-12-26 | 中国科学院上海微系统与信息技术研究所 | A kind of single-port SRAM unit based on SOI and preparation method thereof |
| CN107516676A (en) * | 2016-06-17 | 2017-12-26 | 中国科学院上海微系统与信息技术研究所 | A kind of MOS device structure based on SOI and preparation method thereof |
| CN107516659A (en) * | 2016-06-17 | 2017-12-26 | 中国科学院上海微系统与信息技术研究所 | A kind of dual-port sram cell based on SOI and preparation method thereof |
| CN112466950A (en) * | 2020-11-27 | 2021-03-09 | 中国科学院微电子研究所 | SOI MOS structure with edge leakage resistance and forming method thereof |
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| US5001528A (en) * | 1989-01-31 | 1991-03-19 | The United States Of America As Represented By The Secretary Of The Air Force | Radiation hardened CMOS on SOI or SOS devices |
| US5024965A (en) * | 1990-02-16 | 1991-06-18 | Chang Chen Chi P | Manufacturing high speed low leakage radiation hardened CMOS/SOI devices |
| USH1435H (en) * | 1991-10-21 | 1995-05-02 | Cherne Richard D | SOI CMOS device having body extension for providing sidewall channel stop and bodytie |
| US5293052A (en) * | 1992-03-23 | 1994-03-08 | Harris Corporation | SOT CMOS device having differentially doped body extension for providing improved backside leakage channel stop |
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| CN103219384A (en) * | 2013-04-03 | 2013-07-24 | 北京大学 | Anti-single particle radiation multi-grid device and preparation method thereof |
| CN103219384B (en) * | 2013-04-03 | 2015-05-20 | 北京大学 | Anti-single particle radiation multi-grid device and preparation method thereof |
| US9508852B2 (en) | 2013-04-03 | 2016-11-29 | Peking University | Radiation-hardened-by-design (RHBD) multi-gate device |
| CN106952954A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI MOS devices and preparation method thereof |
| CN106952953A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI MOS devices of resistant to total dose effect and preparation method thereof |
| CN106952916A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI dual-port statics random-access memory unit and preparation method thereof |
| CN106952914A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of SOI single port statics random-access memory unit and preparation method thereof |
| CN106952954B (en) * | 2016-01-07 | 2020-11-13 | 中国科学院上海微系统与信息技术研究所 | SOI MOS device and manufacturing method thereof |
| CN107516650A (en) * | 2016-06-17 | 2017-12-26 | 中国科学院上海微系统与信息技术研究所 | A kind of single-port SRAM unit based on SOI and preparation method thereof |
| CN107516676A (en) * | 2016-06-17 | 2017-12-26 | 中国科学院上海微系统与信息技术研究所 | A kind of MOS device structure based on SOI and preparation method thereof |
| CN107516659A (en) * | 2016-06-17 | 2017-12-26 | 中国科学院上海微系统与信息技术研究所 | A kind of dual-port sram cell based on SOI and preparation method thereof |
| CN107516676B (en) * | 2016-06-17 | 2022-05-17 | 中国科学院上海微系统与信息技术研究所 | MOS device structure based on SOI and manufacturing method thereof |
| CN112466950A (en) * | 2020-11-27 | 2021-03-09 | 中国科学院微电子研究所 | SOI MOS structure with edge leakage resistance and forming method thereof |
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Effective date of registration: 20160928 Address after: 203, room 214028, block A, 21 Changjiang Road, New District, Jiangsu, Wuxi Patentee after: Wuxi Zhongwei Microchips Co., Ltd. Patentee after: China Electronics Technology Group Corporation No.58 Research Institute Address before: 203, room 214035, block A, 21 Changjiang Road, New District, Jiangsu, Wuxi Patentee before: Wuxi Zhongwei Microchips Co., Ltd. |