CN106933750B - Verification method and device for data and state in multi-level cache - Google Patents
Verification method and device for data and state in multi-level cache Download PDFInfo
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Abstract
The invention discloses a method and a device for verifying data and states in a multi-level cache, wherein the method comprises the following steps: sequentially acquiring first cache information of each cache line in the nth-level cache, wherein the first cache information comprises first mark information and first data information; acquiring a first physical address set consisting of first physical addresses corresponding to each cache line in the nth-level cache according to the first cache information; sequentially acquiring second cache information of each cache line in the mth level cache, wherein the second cache information comprises second mark information and second data information; acquiring a second physical address set consisting of second physical addresses corresponding to each cache line in the mth level cache according to the second cache information; and if the second physical address set comprises the first physical address set, verifying the cache state of the same physical address according to the first cache information and the second cache information for each cache line in the nth-level cache. The method not only can verify the correctness of the cache state, but also can improve the verification efficiency of verifying the cache consistency among cores.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for verifying data and states in a multi-level cache.
Background
As the performance gap between processors and memory is getting larger and larger, multi-level caches can be added between processors and memory using the principle of locality of program access, and thus verification of multi-level caches between processors and memory becomes important.
In the related art, whether the system level verification is performed on a processor or the module level verification is performed on a memory system alone, the correctness of data in a multi-level cache is judged by applying excitation to an input signal and detecting an output signal.
However, the verification method can only verify whether the cached data is correct, and in the system level verification, a specific scenario can only be constructed through a directional test program, and it is difficult to achieve the requirement of fast convergence in the verification process, so that it may be hidden that a BUG (fault) related to the performance is not found, and the performance of the processor cannot be improved.
Disclosure of Invention
The object of the present invention is to solve at least to some extent one of the technical problems in the above-mentioned technology.
Therefore, a first objective of the present invention is to provide a method for verifying data and states in a multi-level cache, which can verify the correctness of the cache state, discover a performance-related BUG caused by the cache, and improve the verification efficiency for verifying the cache consistency between cores.
The second objective of the present invention is to provide a verification device for data and status in a multi-level cache.
To achieve the above object, an embodiment of a first aspect of the present invention provides a method for verifying data and status in a multi-level cache, including the following steps: sequentially acquiring first Cache information of each Cache line Cache _ line in an nth-level Cache, wherein the first Cache information comprises first mark Tag information and first Data information, and n is a positive integer; acquiring a first physical address set of the nth-level Cache according to the first Cache information, wherein the first physical address set consists of first physical addresses corresponding to Cache lines Cache _ line in the nth-level Cache; sequentially acquiring second Cache information of each Cache line Cache _ line in the mth-level Cache, wherein the second Cache information comprises second mark Tag information and second Data information, m is a positive integer, and m-n is more than or equal to 0 and less than or equal to 1; acquiring a second physical address set of the m-level Cache according to the second Cache information, wherein the second physical address set consists of second physical addresses corresponding to Cache lines Cache _ line in the m-level Cache; judging whether the second physical address set contains the first physical address set or not; and if the second physical address set comprises the first physical address set, verifying the Cache state belonging to the same physical address according to the first Cache information and the second Cache information aiming at each Cache line Cache _ line in the nth-level Cache.
According to the verification method for data and states in the multi-level Cache of the embodiment of the invention, a first physical address set is formed by sequentially acquiring the first Cache information of each Cache line in the nth level Cache and the first physical address corresponding to each Cache line, a second physical address set is formed by sequentially acquiring the second Cache information of each Cache line in the mth level Cache and the second physical address corresponding to each Cache line, the second physical address set is judged to contain the first physical address set, and the Cache states belonging to the same physical address are verified according to the first Cache information and the second Cache information aiming at each Cache line in the nth level Cache, the correctness of the Cache states can be verified, the BUG related to the performance caused by the Cache is found, and the overall performance of the processor is improved, and the verification efficiency for verifying the inter-core cache consistency can be improved by checking the state and data of the inter-core visible cache.
In an embodiment of the present invention, the verifying the cache states belonging to the same physical address according to the first cache information and the second cache information includes: determining the type of a write strategy of the nth-level cache; if the Write strategy type of the nth-level cache is Write _ through, judging whether the cache state belonging to the same physical address meets the preset design requirement according to the first cache information and the second cache information; if the Write strategy type of the nth level Cache is Write _ back, further judging whether the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is valid; if the Dirty bit state in the Cache line Cache _ line corresponding to the same physical address is valid, judging whether the Cache state belonging to the same physical address meets the preset design requirement or not according to the first Cache information and the second Cache information; if the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is invalid, judging whether the first Data information and the second Data information are consistent or not aiming at the Cache line Cache _ line corresponding to the same physical address; if the first Data information and the second Data information are inconsistent, judging that the cached Data in the multi-level cache is wrong; and if the first Data information is consistent with the second Data information, judging whether the caching state belonging to the same physical address meets the preset design requirement according to the first caching information and the second caching information.
In an embodiment of the present invention, the obtaining the first set of physical addresses of the nth-level cache according to the first cache information includes: and for each Cache line Cache _ line in the nth-level Cache, restoring a first physical address corresponding to each Cache line Cache _ line in the nth-level Cache according to the first Tag information to obtain a first physical address set of the nth-level Cache.
In an embodiment of the present invention, the obtaining the second physical address set of the m-th level cache according to the second cache information includes: and for each Cache line Cache _ line in the m-level Cache, restoring a second physical address corresponding to each Cache line Cache _ line in the m-level Cache according to the second Tag information to obtain a second physical address set of the m-level Cache.
In an embodiment of the present invention, the nth level cache has an instruction cache and a data cache, and when a data source of the instruction cache and the data cache is the same nth +1 level cache, the method further includes: respectively acquiring cache information of the instruction cache and the data cache; verifying the states of the instruction cache and the data cache according to the cache information of the instruction cache and the data cache; and if the states of the instruction cache and the data cache are all valid and dirty, judging that the states of the instruction cache and the data cache are wrong.
To achieve the above object, a second aspect of the present invention provides a device for verifying data and status in a multi-level cache, comprising: the first obtaining module is used for sequentially obtaining first Cache information of each Cache line Cache _ line in an nth-level Cache, wherein the first Cache information comprises first mark Tag information and first Data information, and n is a positive integer; a second obtaining module, configured to obtain a first physical address set of the nth-level Cache according to the first Cache information, where the first physical address set is composed of first physical addresses corresponding to Cache lines Cache _ line in the nth-level Cache; the third obtaining module is used for sequentially obtaining second Cache information of each Cache line Cache _ line in the mth-level Cache, wherein the second Cache information comprises second mark Tag information and second Data information, m is a positive integer, and m-n is greater than or equal to 0 and less than or equal to 1; a fourth obtaining module, configured to obtain a second physical address set of the m-level Cache according to the second Cache information, where the second physical address set is composed of second physical addresses corresponding to Cache lines Cache _ line in the m-level Cache; the judging module is used for judging whether the second physical address set comprises the first physical address set or not; and a verification module, configured to verify, for each Cache line Cache _ line in the nth-level Cache, a Cache state belonging to the same physical address according to the first Cache information and the second Cache information when the determination module determines that the second physical address set includes the first physical address set.
According to the verification device for data and states in the multi-level Cache, the first Cache information of each Cache line Cache _ line in the nth level Cache is sequentially acquired by the first acquisition module, the first physical address set is formed by the second acquisition module according to the first physical address corresponding to each Cache line Cache _ line, the second physical address set is formed by the third acquisition module according to the second Cache information of each Cache line Cache _ line in the mth level Cache and is formed by the fourth acquisition module according to the second physical address corresponding to each Cache line Cache _ line, the judgment module judges that the second physical address set comprises the first physical address set, and the verification module verifies the Cache states belonging to the same physical address according to the first Cache information and the second Cache information aiming at each Cache line Cache _ line in the nth level Cache. The device can verify the correctness of the cache state, finds the BUG related to the performance caused by the cache, improves the overall performance of the processor, and can improve the verification efficiency for verifying the consistency of the cache between the cores by checking the state and the data of the visible cache between the cores.
In one embodiment of the invention, the verification module comprises: a determining unit, configured to determine a type of a write policy of the nth level cache; the verification unit is used for judging whether the cache state belonging to the same physical address meets the preset design requirement or not according to the first cache information and the second cache information when the Write strategy of the nth-level cache is of Write _ through type; a first determining unit, configured to determine whether a state of a Dirty bit in a Cache line Cache _ line corresponding to the same physical address is valid when the Write policy of the nth-level Cache is Write _ back; the verification unit is further configured to, when the first determination unit determines that the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is valid, determine whether the Cache status belonging to the same physical address meets a preset design requirement according to the first Cache information and the second Cache information; a second judging unit, configured to, when the first judging unit judges that the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is invalid, judge, for the Cache line Cache _ line corresponding to the same physical address, whether the first Data information and the second Data information are consistent; the verification unit is further configured to determine that a cache Data error occurs in the multi-level cache when the second determination unit determines that the first Data information and the second Data information are inconsistent, and determine whether the cache state belonging to the same physical address meets a preset design requirement according to the first cache information and the second cache information when the second determination unit determines that the first Data information and the second Data information are consistent.
In an embodiment of the present invention, the second obtaining module is specifically configured to: and for each Cache line Cache _ line in the nth-level Cache, restoring a first physical address corresponding to each Cache line Cache _ line in the nth-level Cache according to the first Tag information to obtain a first physical address set of the nth-level Cache.
In an embodiment of the present invention, the fourth obtaining module is specifically configured to: and for each Cache line Cache _ line in the m-level Cache, restoring a second physical address corresponding to each Cache line Cache _ line in the m-level Cache according to the second Tag information to obtain a second physical address set of the m-level Cache.
In an embodiment of the present invention, the nth level cache has an instruction cache and a data cache, and when a data source of the instruction cache and the data cache is the same nth +1 level cache, the first obtaining module is further configured to: respectively acquiring cache information of the instruction cache and the data cache; the verification module is further to: and verifying the states of the instruction cache and the data cache according to the cache information of the instruction cache and the data cache, and judging that the states of the instruction cache and the data cache are wrong when the states of the instruction cache and the data cache are all valid and dirty.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow diagram of a verification method for data and status in a multi-level cache according to one embodiment of the invention;
FIG. 2 is a flow diagram of a verification method for data and status in a multi-level cache according to another embodiment of the invention;
FIG. 3 is a flow diagram of a verification method for data and status in a multi-level cache according to yet another embodiment of the invention;
FIG. 4 is a flow diagram of a verification method for data and status in a multi-level cache, according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the validation of the level 1, 2 cache structure of intel i7 according to an embodiment of the present invention;
FIG. 6 is a block diagram of a verification apparatus for data and status in a multi-level cache according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure of a verification module according to one embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
It should be noted that the main ideas of the present invention are: the higher level cache must be a subset of the lower level cache, and the state of the higher level cache must be consistent with the state of the lower level cache. Therefore, by utilizing the characteristic, the invention provides a method and a device for verifying data and state in a multi-level cache, so as to realize self-checking of the current state of the cache according to the state of the design to be tested. Specifically, the verification method and apparatus for data and status in a multi-level cache according to the embodiments of the present invention are described below with reference to the accompanying drawings.
FIG. 1 is a flow chart of a method for verifying data and status in a multi-level cache according to one embodiment of the invention.
As shown in fig. 1, the verification method for data and status in a multi-level cache may include:
s11, sequentially obtaining first Cache information of each Cache line Cache _ line in the nth level Cache, where the first Cache information includes first Tag information and first Data information, and n is a positive integer.
S12, a first physical address set of the nth level Cache is obtained according to the first Cache information, wherein the first physical address set is composed of first physical addresses corresponding to Cache lines Cache _ line in the nth level Cache.
Specifically, obtaining the first physical address set of the nth level cache according to the first cache information specifically includes: and for each Cache line Cache _ line in the nth-level Cache, restoring a first physical address corresponding to each Cache line Cache _ line in the nth-level Cache according to the first Tag information to obtain a first physical address set of the nth-level Cache.
S13, second Cache information of each Cache line Cache _ line in the mth level Cache is sequentially acquired, wherein the second Cache information comprises second mark Tag information and second Data information, m is a positive integer, and m-n is greater than or equal to 0 and less than or equal to 1.
And S14, acquiring a second physical address set of the m-th-level Cache according to the second Cache information, wherein the second physical address set is composed of second physical addresses corresponding to Cache lines Cache _ line in the m-th-level Cache.
Specifically, obtaining the second physical address set of the m-th level cache according to the second cache information includes: and for each Cache line Cache _ line in the mth level Cache, restoring a second physical address corresponding to each Cache line Cache _ line in the mth level Cache according to the second Tag information to obtain a second physical address set of the mth level Cache.
S15, determine whether the second set of physical addresses includes the first set of physical addresses.
And S16, if the second physical address set comprises the first physical address set, verifying the Cache state belonging to the same physical address according to the first Cache information and the second Cache information for each Cache line Cache _ line in the nth-level Cache.
Specifically, verifying the cache states belonging to the same physical address according to the first cache information and the second cache information, as shown in fig. 2, includes:
s161, determining the type of the write strategy of the nth level cache.
Specifically, a predefined design manual may be obtained, and the type of write strategy for the nth level cache may be determined according to the predefined design manual.
And S162, if the Write strategy type of the nth-level cache is Write _ through, judging whether the cache state belonging to the same physical address meets the preset design requirement according to the first cache information and the second cache information.
S163, if the Write policy of the nth level Cache is Write _ back, further determining whether the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is valid.
And S164, if the Dirty bit state in the Cache line Cache _ line corresponding to the same physical address is valid, judging whether the Cache state belonging to the same physical address meets the preset design requirement according to the first Cache information and the second Cache information.
And S165, if the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is invalid, judging whether the first Data information and the second Data information are consistent or not aiming at the Cache line Cache _ line corresponding to the same physical address.
And S166, if the first Data information and the second Data information are inconsistent, judging that the cache Data in the multi-level cache is wrong.
And S167, if the first Data information is consistent with the second Data information, judging whether the cache states belonging to the same physical address meet the preset design requirement according to the first cache information and the second cache information.
That is, in comparing whether the cache states of two adjacent levels of caches for the same physical address are in accordance with the preset state of the design requirement, the type of the write strategy of the nth level of cache may be determined first, and then different verification operations may be performed according to the type of the write strategy. For example, if the nth-level cache Write-back policy is Write _ back and the status is valid and not dirty, the data information of the cache _ line corresponding to the nth-level cache and the mth-level cache needs to be compared, and the data must be consistent until the comparison of the cache _ line information of all the nth-level caches is completed. After the comparison of the data information of the cache _ line corresponding to the nth-level cache and the mth-level cache is completed, some cache attributes customized by design engineers or selectable in the caches are checked, and the states of the attributes need to be consistent with those described in the design manual, such as a lock function under the MIPS ISA. It is specified in the MIPS manual that a cache function can be added for improving performance in a specific scenario. When the lock state of the cache _ line is 1, the cache _ line cannot be replaced when there are other non-lock cache _ lines in the set. The situation of detecting whether the state of the function is correct is as follows: when the cache _ line of the nth-level cache is in a lock state, the state of the mth-level cache corresponding to the physical address of the nth-level cache is also necessarily in a lock state. These performance-related and function-independent verification points cannot be verified at random.
In summary, the verification method according to the embodiment of the present invention mainly verifies the caches between two adjacent levels, but the caches at different levels do not need to be compared, for example, the m-th level cache does not need to be compared with the m + 2-th level cache in terms of state. The comparison sequence should be compared layer by layer from the highest level cache to the lowest level cache, and the consistency between the data of each two adjacent levels of cache and the state is ensured.
It should be noted that, if there are multiple caches in the nth level cache, and the data sources in these caches are from the same nth +1 level cache, the statuses of the two caches also need to be compared. As an example, when the nth level cache has an instruction cache and a data cache, and when the data sources of the instruction cache and the data cache are the same nth +1 level cache, as shown in fig. 3, the method further includes:
and S31, respectively obtaining the cache information of the instruction cache and the data cache.
And S32, verifying the states of the instruction cache and the data cache according to the cache information of the instruction cache and the data cache.
S33, if the states of the instruction cache and the data cache are all valid and dirty, the states of the instruction cache and the data cache are determined to be incorrect.
That is, the peer cache also needs to be checked, i.e. the instruction cache and the data cache also need to be compared: firstly, respectively obtaining the information of an instruction cache and a data cache, after obtaining the information of the instruction cache and the data cache, searching in the other cache by taking the physical address in any one cache as an index, and if the states of the two caches are all valid and dirty, indicating that the states of the instruction cache and the data cache are wrong. It is understood that the content of the verification in the embodiment of the present invention may be subject to the specific definition of the design to be tested.
According to the verification method for data and states in the multi-level Cache of the embodiment of the invention, a first physical address set is formed by sequentially acquiring the first Cache information of each Cache line in the nth level Cache and the first physical address corresponding to each Cache line, a second physical address set is formed by sequentially acquiring the second Cache information of each Cache line in the mth level Cache and the second physical address corresponding to each Cache line, the second physical address set is judged to contain the first physical address set, and the Cache states belonging to the same physical address are verified according to the first Cache information and the second Cache information aiming at each Cache line in the nth level Cache, the correctness of the Cache states can be verified, the BUG related to the performance caused by the Cache is found, and the overall performance of the processor is improved, and the verification efficiency for verifying the inter-core cache consistency can be improved by checking the state and data of the inter-core visible cache.
In order to make those skilled in the art understand the present invention more clearly, the verification method for data and status in multi-level cache according to the embodiment of the present invention is used to verify the level 1 and level 2 cache of intel i7, and the present invention is further described in detail with reference to fig. 4 and fig. 5. FIG. 4 is a flow diagram of a method for verifying data and status in a multi-level cache, according to an embodiment of the invention. FIG. 5 is a schematic diagram of the verification of the level 1, 2 cache structure of intel i7 according to an embodiment of the present invention. As shown in fig. 5, the instruction cache (icache) and the data cache (dcache) are level 1 caches, the second cache (cache) is a level two cache, and the write-back policies are write _ back. The virtual address is 48 bits, the physical address is 36 bits, and the cache _ line size is 512 bits. The mapping mode of the instruction cache is 4-way group phase, and the mapping mode of the data cache and the second-level cache is 8-way group connection. The primary cache is 32KB and the secondary cache is 256 KB. The first-level cache is a virtual index and a physical identifier; the second level cache is a physical index and a physical identifier.
As shown in fig. 4, the verification method may include:
first Cache information of Cache _ line of each Cache line in a level 1 Cache in intel i7 is sequentially acquired through S401 to fetch tag and data information in the Icache, S402 calculates an effective physical address corresponding to the Cache _ line in the Icache, and puts state and data information of the Icache into an Icache _ info dynamic array shown in FIG. 5, and then second Cache information of Cache line Cache _ line in a level 2 Cache in the intel i7 is sequentially acquired through S403 to fetch tag and data information in the Cache, and S404 calculates an effective physical address corresponding to the Cache _ line in the Cache, and puts state and data information of the Cache into the Cache _ info dynamic array shown in FIG. 5. Then, S405 queries the cache _ info using the valid physical address in the Icache _ info as an index, and if no corresponding information is queried, it indicates that the cache status is incorrect. Then, S406 checks the Icache state, and since the write-back policy of the first-level cache of the intel i7 is write _ back, it is necessary to detect the Dirty bit in the cache state, for example, to determine whether the Dirty bit in the Icache _ info corresponding to the valid physical address is 1, if not, it is necessary to compare the data information of the two-level caches corresponding to the physical address, and if the data is inconsistent, it is determined that the cache data is incorrect; if the data is consistent, S407 is also required to check the design-defined cache state information. When all the cache states are consistent with the states described in the design document, S408 performs comparison of the valid physical addresses in the next instruction cache until all the valid physical addresses in the instruction cache are compared, and obtains the check result1 shown in fig. 5, after the state check of the instruction cache and the second level cache passes, the states of the data cache and the second level cache need to be checked, and the comparison process is consistent with the comparison method of the instruction cache and the second level cache, and obtains the check result2 shown in fig. 5.
Corresponding to the verification methods for data and states in a multi-level cache provided in the above embodiments, an embodiment of the present invention further provides a verification apparatus for data and states in a multi-level cache, and since the verification apparatus for data and states in a multi-level cache provided in the embodiment of the present invention corresponds to the verification method for data and states in a multi-level cache provided in the above embodiment, the foregoing embodiments of the verification method for data and states in a multi-level cache are also applicable to the verification apparatus for data and states in a multi-level cache provided in this embodiment, and will not be described in detail in this embodiment. FIG. 6 is a block diagram of a verification apparatus for data and status in a multi-level cache according to an embodiment of the present invention. As shown in fig. 6, the apparatus may include: a first obtaining module 100, a second obtaining module 200, a third obtaining module 300, a fourth obtaining module 404, a judging module 500 and a verifying module 600.
The first obtaining module 100 is configured to sequentially obtain first Cache information of each Cache line Cache _ line in an nth-level Cache, where the first Cache information includes first Tag information and first Data information, and n is a positive integer.
The second obtaining module 200 is configured to obtain a first physical address set of the nth-level Cache according to the first Cache information, where the first physical address set is composed of first physical addresses corresponding to Cache lines Cache _ line in the nth-level Cache.
Specifically, the second obtaining module 200 is specifically configured to: and for each Cache line Cache _ line in the nth-level Cache, restoring a first physical address corresponding to each Cache line Cache _ line in the nth-level Cache according to first mark Tag information to obtain a first physical address set of the nth-level Cache.
The third obtaining module 300 is configured to sequentially obtain second Cache information of each Cache line Cache _ line in the mth-level Cache, where the second Cache information includes second Tag information and second Data information, m is a positive integer, and m-n is greater than or equal to 0 and less than or equal to 1.
The fourth obtaining module 400 is configured to obtain a second physical address set of the m-th-level Cache according to the second Cache information, where the second physical address set is composed of second physical addresses corresponding to Cache lines Cache _ line in the m-th-level Cache.
Specifically, the fourth obtaining module 400 is specifically configured to: and for each Cache line Cache _ line in the mth level Cache, restoring a second physical address corresponding to each Cache line Cache _ line in the mth level Cache according to the second Tag information to obtain a second physical address set of the mth level Cache.
The determining module 500 is configured to determine whether the second physical address set includes the first physical address set.
The verification module 600 is configured to verify, according to the first Cache information and the second Cache information, a Cache state belonging to the same physical address for each Cache line Cache _ line in the nth-level Cache when the determination module 500 determines that the second physical address set includes the first physical address set.
Specifically, in one embodiment of the present invention, as shown in fig. 7, the verification module 600 may include: a determination unit 601, a verification unit 602, a first judgment unit 603, and a second judgment unit 604.
Specifically, the determining unit 601 is configured to determine a type of a write policy of the nth level cache.
The verifying unit 602 is configured to determine whether a cache state belonging to the same physical address meets a preset design requirement according to the first cache information and the second cache information when the Write policy of the nth-level cache is Write _ through.
The first determining unit 603 is configured to determine whether a status of a Dirty bit in a Cache line Cache _ line corresponding to the same physical address is valid when the Write policy of the nth-level Cache is Write _ back.
The verifying unit 602 is further configured to, when the first determining unit 603 determines that the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is valid, determine whether the Cache status belonging to the same physical address meets a preset design requirement according to the first Cache information and the second Cache information.
The second determining unit 604 is configured to determine whether the first Data information and the second Data information are consistent for the Cache line Cache _ line corresponding to the same physical address when the first determining unit 603 determines that the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is invalid.
The verifying unit 602 is further configured to determine that a Data error occurs in the multi-level cache when the second determining unit 604 determines that the first Data information and the second Data information are inconsistent, and determine whether the cache state belonging to the same physical address meets a preset design requirement according to the first cache information and the second cache information when the second determining unit 604 determines that the first Data information and the second Data information are consistent.
In an embodiment of the present invention, the nth level cache includes an instruction cache and a data cache, and when a data source of the instruction cache and the data cache is the same nth +1 level cache, the first obtaining module 100 is further configured to: and respectively obtaining the cache information of the instruction cache and the data cache. The verification module 600 is further configured to verify the states of the instruction cache and the data cache according to the cache information of the instruction cache and the data cache, and determine that the states of the instruction cache and the data cache are incorrect when the states of the instruction cache and the data cache are all valid and dirty.
According to the verification device for data and states in the multi-level Cache of the embodiment of the invention, the first Cache information of each Cache line Cache _ line in the nth level Cache is sequentially acquired by the first acquisition module, the first physical address set is formed by the second acquisition module according to the first physical address corresponding to each Cache line Cache _ line, the second physical address set is formed by the third acquisition module according to the second Cache information of each Cache line Cache _ line in the mth level Cache and the second physical address set is formed by the fourth acquisition module according to the second physical address corresponding to each Cache line Cache _ line, the judgment module judges that the second physical address set comprises the first physical address set, the verification module verifies the Cache states belonging to the same physical address according to the first Cache information and the second Cache information aiming at each Cache line Cache _ line in the nth level Cache, and the method can verify the correctness of the Cache states, the performance-related BUG caused by the cache is found, the overall performance of the processor is improved, and the verification efficiency for verifying the cache consistency between the cores can be improved by checking the state and the data of the visible cache between the cores.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (8)
1. A verification method for data and status in a multi-level cache is characterized by comprising the following steps:
sequentially acquiring first Cache information of each Cache line Cache _ line in an nth-level Cache, wherein the first Cache information comprises first mark Tag information and first Data information, and n is a positive integer;
acquiring a first physical address set of the nth-level Cache according to the first Cache information, wherein the first physical address set consists of first physical addresses corresponding to Cache lines Cache _ line in the nth-level Cache;
sequentially acquiring second Cache information of each Cache line Cache _ line in the mth-level Cache, wherein the second Cache information comprises second mark Tag information and second Data information, m is a positive integer, and m-n is more than or equal to 0 and less than or equal to 1;
acquiring a second physical address set of the m-level Cache according to the second Cache information, wherein the second physical address set consists of second physical addresses corresponding to Cache lines Cache _ line in the m-level Cache;
judging whether the second physical address set contains the first physical address set or not; and
if the second physical address set comprises the first physical address set, verifying the Cache state belonging to the same physical address according to the first Cache information and the second Cache information aiming at each Cache line Cache _ line in the nth-level Cache;
wherein, the verifying the cache state belonging to the same physical address according to the first cache information and the second cache information comprises:
determining the type of a write strategy of the nth-level cache;
if the Write strategy type of the nth-level cache is Write _ through, judging whether the cache state belonging to the same physical address meets the preset design requirement according to the first cache information and the second cache information;
if the Write strategy type of the nth level Cache is Write _ back, further judging whether the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is valid;
if the Dirty bit state in the Cache line Cache _ line corresponding to the same physical address is valid, judging whether the Cache state belonging to the same physical address meets the preset design requirement or not according to the first Cache information and the second Cache information;
if the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is invalid, judging whether the first Data information and the second Data information are consistent or not aiming at the Cache line Cache _ line corresponding to the same physical address;
if the first Data information and the second Data information are inconsistent, judging that the cached Data in the multi-level cache is wrong;
and if the first Data information is consistent with the second Data information, judging whether the caching state belonging to the same physical address meets the preset design requirement according to the first caching information and the second caching information.
2. The method as claimed in claim 1, wherein said obtaining the first set of physical addresses of the nth level cache according to the first cache information comprises:
and for each Cache line Cache _ line in the nth-level Cache, restoring a first physical address corresponding to each Cache line Cache _ line in the nth-level Cache according to the first Tag information to obtain a first physical address set of the nth-level Cache.
3. The method as claimed in claim 1, wherein said obtaining the second set of physical addresses of the m-th level cache according to the second cache information comprises:
and for each Cache line Cache _ line in the m-level Cache, restoring a second physical address corresponding to each Cache line Cache _ line in the m-level Cache according to the second Tag information to obtain a second physical address set of the m-level Cache.
4. The method as claimed in claim 1, wherein said nth level cache has an instruction cache and a data cache, and when the data source of said instruction cache and said data cache is the same nth +1 level cache, said method further comprises:
respectively acquiring cache information of the instruction cache and the data cache;
verifying the states of the instruction cache and the data cache according to the cache information of the instruction cache and the data cache;
and if the states of the instruction cache and the data cache are all valid and dirty, judging that the states of the instruction cache and the data cache are wrong.
5. An apparatus for verifying data and status in a multi-level cache, comprising:
the first obtaining module is used for sequentially obtaining first Cache information of each Cache line Cache _ line in an nth-level Cache, wherein the first Cache information comprises first mark Tag information and first Data information, and n is a positive integer;
a second obtaining module, configured to obtain a first physical address set of the nth-level Cache according to the first Cache information, where the first physical address set is composed of first physical addresses corresponding to Cache lines Cache _ line in the nth-level Cache;
the third obtaining module is used for sequentially obtaining second Cache information of each Cache line Cache _ line in the mth-level Cache, wherein the second Cache information comprises second mark Tag information and second Data information, m is a positive integer, and m-n is greater than or equal to 0 and less than or equal to 1;
a fourth obtaining module, configured to obtain a second physical address set of the m-level Cache according to the second Cache information, where the second physical address set is composed of second physical addresses corresponding to Cache lines Cache _ line in the m-level Cache;
the judging module is used for judging whether the second physical address set comprises the first physical address set or not; and
a verification module, configured to verify, for each Cache line Cache _ line in the nth-level Cache, a Cache state belonging to the same physical address according to the first Cache information and the second Cache information when the determination module determines that the second physical address set includes the first physical address set;
wherein the verification module comprises:
a determining unit, configured to determine a type of a write policy of the nth level cache;
the verification unit is used for judging whether the cache state belonging to the same physical address meets the preset design requirement or not according to the first cache information and the second cache information when the Write strategy of the nth-level cache is of Write _ through type;
a first determining unit, configured to determine whether a state of a Dirty bit in a Cache line Cache _ line corresponding to the same physical address is valid when the Write policy of the nth-level Cache is Write _ back;
the verification unit is further configured to, when the first determination unit determines that the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is valid, determine whether the Cache status belonging to the same physical address meets a preset design requirement according to the first Cache information and the second Cache information;
a second judging unit, configured to, when the first judging unit judges that the status of the Dirty bit in the Cache line Cache _ line corresponding to the same physical address is invalid, judge, for the Cache line Cache _ line corresponding to the same physical address, whether the first Data information and the second Data information are consistent;
the verification unit is further configured to determine that a cache Data error occurs in the multi-level cache when the second determination unit determines that the first Data information and the second Data information are inconsistent, and determine whether the cache state belonging to the same physical address meets a preset design requirement according to the first cache information and the second cache information when the second determination unit determines that the first Data information and the second Data information are consistent.
6. The apparatus of claim 5, wherein the second obtaining module is specifically configured to:
and for each Cache line Cache _ line in the nth-level Cache, restoring a first physical address corresponding to each Cache line Cache _ line in the nth-level Cache according to the first Tag information to obtain a first physical address set of the nth-level Cache.
7. The apparatus for verifying data and status in a multi-level cache of claim 5, wherein the fourth obtaining module is specifically configured to:
and for each Cache line Cache _ line in the m-level Cache, restoring a second physical address corresponding to each Cache line Cache _ line in the m-level Cache according to the second Tag information to obtain a second physical address set of the m-level Cache.
8. The apparatus as claimed in claim 5, wherein the nth level cache has an instruction cache and a data cache, and when the data source of the instruction cache and the data cache are the same nth +1 level cache,
the first obtaining module is further configured to: respectively acquiring cache information of the instruction cache and the data cache;
the verification module is further to: and verifying the states of the instruction cache and the data cache according to the cache information of the instruction cache and the data cache, and judging that the states of the instruction cache and the data cache are wrong when the states of the instruction cache and the data cache are all valid and dirty.
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