CN102880537A - Software simulation verification method based on Cache coherence protocol - Google Patents
Software simulation verification method based on Cache coherence protocol Download PDFInfo
- Publication number
- CN102880537A CN102880537A CN2012103290806A CN201210329080A CN102880537A CN 102880537 A CN102880537 A CN 102880537A CN 2012103290806 A CN2012103290806 A CN 2012103290806A CN 201210329080 A CN201210329080 A CN 201210329080A CN 102880537 A CN102880537 A CN 102880537A
- Authority
- CN
- China
- Prior art keywords
- protocol
- message
- simulator
- state
- protocol tables
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention provides a software simulation verification method based on a Cache coherence protocol. According to the method, pseudo random test which is capable of compiling constraint models and also carrying out band constraint in a manual mode is subject to software simulation and verification; specific objects are verified, and the accuracy and defect of the protocols are fed back. The method based on software simulation comprises the following steps of: firstly determining a multi-stage coherence description mode based on an expanded Cache Coherence protocol; and subsequently realizing the software simulation verification method, counting the coverage rate and carrying out error report. With the adoption of the method, the Cache Coherence protocol in multi-stage domains in a multi-state space can be verified effectively so as to enable a protocol table to realize the establishment of corresponding logic relationship, judge whether the state transition of a system in accordance with the protocol table accords with the coherence definition through an overall checker, and primarily judge whether a mode established in accordance with the protocol table has expected properties. The model system has the remarkable advantages that counter-examples can be generated automatically so as to assist in debugging errors of the system and accelerating system diagnosis and debugging.
Description
Technical field
The present invention relates to the Computer Applied Technology field, specifically a kind of Cache consistency protocol software simulation verification method.
Background technology
The consistent distributed shared memory multicomputer system of Cache is current a kind of important system architecture.Processor directly articulates internal memory at present, itself supports the Cache consistency protocol, and is therefore when making up multicomputer system, usually that these processors are direct-connected, by the consistance between their agreement maintenance processor own, and form a single Cache coherency domains.But because restrictions such as protocol specification, link port, the single territory multicomputer system scale that forms like this is usually limited.For realizing large-scale CC-NUMA multicomputer system, need by Node Controller NC(Node Controller) expansion coherency domains space.The Node Controller that the present invention relates to has the overall Cache consistance of maintenance and two kinds of functions of expanding system scale: at first, each Node Controller connects 1 to 4 processor, form a node and first order Cache coherency domains, consistance is safeguarded jointly by processor and Node Controller in the territory; Secondly, Node Controller direct interconnection or connect to form extensive CC-NUMA system by the node-routing device.Internodal second level Cache consistance is safeguarded by Node Controller.The large-scale CC-NUMA system that consists of like this need to set up multi-level agreement in the expansion of processor direct connection Cache consistency protocol basis, and safeguards global coherency.In the multistage coherency domains CC-NUMA system protocol of design extension-based type Cache Coherence agreement, its simulating, verifying work is also become important process.Fig. 1 has showed a multistage coherency domains system.
Summary of the invention
The purpose of this invention is to provide a kind of Cache consistency protocol software simulation verification method.
The present invention proposes a kind of Cache consistency protocol software simulation verification method.The software simulation checking can be write the pseudorandom test that restricted model is carried out belt restraining simultaneously by manual type, verifies for specific target, and the correctness of feedback protocols and defective.Based on the method for software simulation, at first determine the multistage consistance describing mode of extension-based type Cache Coherence agreement, then realize a kind of method of software simulation checking and add up coverage rate and carry out mistake report.This method can effectively be verified the Cache Coherence consistency protocol of multilevel field under the multimode space, so that protocol tables realizes setting up in logic corresponding relation, and whether meet conformance definition by global-inspection's device decision-making system according to the state transition of protocol tables, and tentatively judge whether the model that makes up according to this protocol tables has the character of expectation.
The objective of the invention is to realize in the following manner, system comprises: 1) system simulator, 2) test and excitation automatic generator, 3) global-inspection's device, 4) the Node Controller simulator, wherein:
1) system simulator comprises following two parts:
(1) bus functional model: simulation has realized the interconnection network between Cache, storage and processor in the processor; Support self-defined system topology; Provide the transaction-level simulation of memory access behavior has been supported; Real-time behavior and the state of simulating and provide each memory access affairs, Cache, storage in the system according to the direct-connected Cache consistency protocol of processor in service;
(2)
The Node Controller simulator: the api interface by bus functional model articulates thereon, and simulation has realized the own Multi-Level Cache consistency protocol of Node Controller; Use processor Cache consistency protocol message and processor to communicate, and between each Node Controller, communicate by the Node Controller network with the Cache consistency protocol message of expansion, finish the conversion of the consistency protocol between the multilevel field;
2) test and excitation maker: for generation of high-quality test and excitation; The test and excitation maker produces memory access affairs to the at random kind of same address with at random speed at random Cache, and affairs are sent on the bus functional model, bus functional model is converted to message according to the direct-connected Cache consistency protocol of processor with the memory access affairs and moves in simulator;
3) global-inspection's device: operate on the whole system simulator, check the Data Cache consistance of the overall situation, system state in the simulation system and message flow are carried out real-time inspection, be used for finding that the simulation process system departs from the behavior of agreement, and whether check system deadlock, hungry to death occurs.
4) protocol tables simulator, the protocol tables simulator is the core of Node Controller simulator, the protocol tables simulator is the key that the Node Controller simulator can work, because protocol tables is the target that is verified, therefore protocol tables all may be modified in whole proof procedure, we need realize reshuffling protocol tables, the action of protocol tables simulator is described, this protocol tables simulator comprises three key modules parts: the entry condition requestor, state conversion actuator and protocol tables query scheduling device, when the Node Controller simulator is received a piece of news, protocol tables query scheduling device comes into operation, at first the entry condition requestor is searched according to the state of the message of receiving and current system, finds to forward corresponding state conversion actuator behind the entrance to and carry out corresponding state transcode; When satisfying next conditioned disjunction response message and satisfy release queueing message, advance the next item down protocol tables search procedure, the below describes respectively:
The entry condition requestor: the entry condition requestor detects current state and protocol tables corresponding relation, the state mutual exclusion that protocol tables is every, current state can only be mated a protocol tables entrance at the most, this realizes adopting two kinds of methods, method one: travel through whole protocol tables, until current state match protocol table changes state conversion actuator over to, and no longer carry out follow-up searching, prevent from again searching after the state conversion; Method two: the at first coding method of define system status register: because the value figure place of each status register is fixed, so all status registers are converted to use behind the corresponding binary number search the list item entry mode, to save the dry run time;
State conversion actuator: the state conversion that might carry out in the protocol tables comprises two classes, shares the transmission with message of filling in of storage information data structure, shared storage fill in use general fill in function, its value is imported into as parameter; The transmission of message is then write different messages according to the difference that sends message and is sent function, when the entry condition requestor inquires corresponding entrance, control is handed to state conversion actuator, and state conversion actuator is set respectively the new value of corresponding storer and is sent message according to the value of reading in next step state cell of protocol tables;
Protocol tables scheduler: according to type of message and message destination node, dispatch each message traversed node controller and need experience the protocol tables of searching, and advance the corresponding message that blocks to enter treatment scheme according to finishing message, prevent deadlock and phenomenon hungry to death that message is processed.
The invention has the beneficial effects as follows:
1) remarkable advantage of this model system is that it can generate counter-example automatically, with the mistake of helping debug system, is used for accelerating system diagnosis and debugging;
2) modelling verification can be recorded and be used state transition, so that protocol tables realizes setting up in logic corresponding relation, and whether meets conformance definition by global-inspection's device decision-making system according to the state transition of protocol tables;
3) have fast modeling pattern, lower checking cost.
Description of drawings
Fig. 1 is multistage coherency domains system topology figure;
Fig. 2 is multistage coherency domains system topology figure;
Fig. 3 is Node Controller simulator structure synoptic diagram.
Embodiment
Explain below with reference to Figure of description method of the present invention being done.
We are divided into verification system as shown in Figure 2
System simulator,
The test and excitation automatic generator,
Global-inspection's device,The Node Controller simulator, wherein: accessing operation simulation and the Correctness checking work of the main realize target of system simulator system; The test and excitation generator is then mainly for generation of high-quality test and excitation; Global-inspection's device operates on the system simulator, checks whether the Data Cache consistance of the overall situation and check system deadlock, hungry to death etc. occurs.The below discusses respectively.
System simulator,This simulator mainly comprises following part:
Bus functional model: simulation has realized the interconnection network between Cache, storage and processor in the processor; Support self-defined system topology; Provide the transaction-level simulation of memory access behavior has been supported; Real-time behavior and the state of simulating and provide each memory access affairs, Cache, storage in the system according to the direct-connected Cache consistency protocol of processor in service;
The Node Controller simulator: the api interface by bus functional model articulates thereon, and simulation has realized the own Multi-Level Cache consistency protocol of Node Controller; Use processor Cache consistency protocol message and processor to communicate, and between each Node Controller, communicate by the Node Controller network with the Cache consistency protocol message of expansion.Finish the conversion of the consistency protocol between the multilevel field.
Global-inspection's device: operate on the whole system, check the Data Cache consistance of the overall situation, the system state in the simulation system and message flow are carried out real-time inspection, be used for finding that the simulation process system departs from the behavior of agreement, and whether check system deadlock, hungry to death etc. occurs.
The test and excitation maker: the test and excitation maker produces memory access affairs to the at random kind of same address with at random speed at random Cache, and affairs are sent on the bus functional model, bus functional model is converted to message according to the direct-connected Cache consistency protocol of processor with the memory access affairs and moves in simulator;
The protocol tables simulatorBe
The Node Controller simulatorCore, the protocol tables simulator is the key that the Node Controller simulator can work.Because protocol tables is the target that is verified, therefore protocol tables all may be modified in whole proof procedure.We need realize reshuffling protocol tables, the action of description list simulator.
The protocol tables simulator comprises three key modules parts: entry condition requestor, state conversion actuator and protocol tables query scheduling device.When the Node Controller simulator is received a piece of news, protocol tables query scheduling device comes into operation, at first the entry condition requestor is searched according to the state of the message of receiving and current system, finds to forward corresponding state conversion actuator behind the entrance to and carry out corresponding state transcode; When satisfying next conditioned disjunction response message and satisfy release queueing message, advance the next item down protocol tables search procedure, the below describes respectively:
The entry condition requestor: the entry condition requestor detects current state and protocol tables corresponding relation, the state mutual exclusion that protocol tables is every, and current state can only be mated a protocol tables entrance at the most.This realization can be adopted two kinds of methods.Method one: travel through whole protocol tables, until current state match protocol table changes state conversion actuator over to, and no longer carries out follow-up searching, prevent from again searching after the state conversion.Method two: the at first coding method of define system status register: because the value figure place of each status register is fixed, so all status registers are converted to use behind the corresponding binary number search the list item entry mode, to save the dry run time.
State conversion actuator: the state conversion that might carry out in the protocol tables comprises two classes, shares the transmission with message of filling in of storing information data structure.The general function of filling in is used in filling in of shared storage, and its value is imported into as parameter; The transmission of message is then write different messages according to the difference that sends message and is sent function.When the entry condition requestor inquires corresponding entrance, control is handed to state conversion actuator, state conversion actuator is set respectively the new value of corresponding storer and is sent message according to the value of reading in next step state cell of protocol tables.
Protocol tables scheduler: according to type of message and message destination node, dispatch each message traversed node controller and need experience the protocol tables of searching.And according to finishing message, advance the corresponding message that blocks to enter treatment scheme, prevent deadlock and phenomenon hungry to death that message is processed.
Except the described technical characterictic of instructions, be the known technology of those skilled in the art.
Claims (1)
1. a Cache consistency protocol software simulation verification method is characterized in that system comprises: 1) system simulator, 2) test and excitation automatic generator, 3) global-inspection's device, 4) the Node Controller simulator, wherein:
1) system simulator comprises following two parts:
(1) bus functional model: simulation has realized the interconnection network between Cache, storage and processor in the processor; Support self-defined system topology; Provide the transaction-level simulation of memory access behavior has been supported; Real-time behavior and the state of simulating and provide each memory access affairs, Cache, storage in the system according to the direct-connected Cache consistency protocol of processor in service;
(2)
The Node Controller simulator: the api interface by bus functional model articulates thereon, and simulation has realized the own Multi-Level Cache consistency protocol of Node Controller; Use processor Cache consistency protocol message and processor to communicate, and between each Node Controller, communicate by the Node Controller network with the Cache consistency protocol message of expansion, finish the conversion of the consistency protocol between the multilevel field;
2) test and excitation maker: for generation of high-quality test and excitation; The test and excitation maker produces memory access affairs to the at random kind of same address with at random speed at random Cache, and affairs are sent on the bus functional model, bus functional model is converted to message according to the direct-connected Cache consistency protocol of processor with the memory access affairs and moves in simulator;
3) global-inspection's device: operate on the whole system simulator, check the Data Cache consistance of the overall situation, system state in the simulation system and message flow are carried out real-time inspection, be used for finding that the simulation process system departs from the behavior of agreement, and whether check system deadlock, hungry to death occurs;
4)
The protocol tables simulator,It is the core of Node Controller simulator, the protocol tables simulator is the key that the Node Controller simulator can work, because protocol tables is the target that is verified, therefore protocol tables all may be modified in whole proof procedure, we need realize reshuffling protocol tables, the action of protocol tables simulator is described, this protocol tables simulator comprises three key modules parts: the entry condition requestor, state conversion actuator and protocol tables query scheduling device, when the Node Controller simulator is received a piece of news, protocol tables query scheduling device comes into operation, at first the entry condition requestor is searched according to the state of the message of receiving and current system, finds to forward corresponding state conversion actuator behind the entrance to and carry out corresponding state transcode; When satisfying next conditioned disjunction response message and satisfy release queueing message, advance the next item down protocol tables search procedure, the below describes respectively:
The entry condition requestor: the entry condition requestor detects current state and protocol tables corresponding relation, the state mutual exclusion that protocol tables is every, current state can only be mated a protocol tables entrance at the most, this realizes adopting two kinds of methods, method one: travel through whole protocol tables, until current state match protocol table changes state conversion actuator over to, and no longer carry out follow-up searching, prevent from again searching after the state conversion; Method two: the at first coding method of define system status register: because the value figure place of each status register is fixed, so all status registers are converted to use behind the corresponding binary number search the list item entry mode, to save the dry run time;
State conversion actuator: the state conversion that might carry out in the protocol tables comprises two classes, shares the transmission with message of filling in of storage information data structure, shared storage fill in use general fill in function, its value is imported into as parameter; The transmission of message is then write different messages according to the difference that sends message and is sent function, when the entry condition requestor inquires corresponding entrance, control is handed to state conversion actuator, and state conversion actuator is set respectively the new value of corresponding storer and is sent message according to the value of reading in next step state cell of protocol tables;
Protocol tables scheduler: according to type of message and message destination node, dispatch each message traversed node controller and need experience the protocol tables of searching, and advance the corresponding message that blocks to enter treatment scheme according to finishing message, prevent deadlock and phenomenon hungry to death that message is processed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103290806A CN102880537A (en) | 2012-09-07 | 2012-09-07 | Software simulation verification method based on Cache coherence protocol |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103290806A CN102880537A (en) | 2012-09-07 | 2012-09-07 | Software simulation verification method based on Cache coherence protocol |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102880537A true CN102880537A (en) | 2013-01-16 |
Family
ID=47481872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103290806A Pending CN102880537A (en) | 2012-09-07 | 2012-09-07 | Software simulation verification method based on Cache coherence protocol |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102880537A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103150264A (en) * | 2013-01-18 | 2013-06-12 | 浪潮电子信息产业股份有限公司 | Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method |
| CN103415085A (en) * | 2013-07-15 | 2013-11-27 | 同济大学 | Automatic generation method of general MAC protocol processor |
| CN103488505A (en) * | 2013-09-16 | 2014-01-01 | 杭州华为数字技术有限公司 | Patching method, device and system |
| CN104317736A (en) * | 2014-09-28 | 2015-01-28 | 曙光信息产业股份有限公司 | Method for implementing multi-level caches in distributed file system |
| CN104360944A (en) * | 2014-11-12 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | Automated testing method and system |
| CN105404572A (en) * | 2015-12-08 | 2016-03-16 | 北京时代民芯科技有限公司 | Cache system formal verification method based on traversal search storage model |
| CN105930299A (en) * | 2016-04-25 | 2016-09-07 | 浪潮电子信息产业股份有限公司 | BFM-based SystemVerilog protocol verification platform building method |
| CN106155853A (en) * | 2015-03-23 | 2016-11-23 | 龙芯中科技术有限公司 | The verification method of processor IP, device and system |
| CN106201881A (en) * | 2016-07-12 | 2016-12-07 | 桂林电子科技大学 | A kind of CSP concurrent system adjustment method based on ASP |
| CN106933750A (en) * | 2015-12-31 | 2017-07-07 | 北京国睿中数科技股份有限公司 | For data in multi-level buffer and the verification method and device of state |
| CN108027775A (en) * | 2015-09-24 | 2018-05-11 | 高通股份有限公司 | Avoid using and retry and respond the deadlock in the non-system based on processor for retrying bus consistency protocol in order |
| EP3355525A4 (en) * | 2015-10-15 | 2018-08-01 | Huawei Technologies Co., Ltd. | Computing apparatus, node device, and server |
| CN110674055A (en) * | 2019-09-11 | 2020-01-10 | 上海高性能集成电路设计中心 | Cache consistency simulation verification method for component level and component combination level |
| CN110727611A (en) * | 2019-09-09 | 2020-01-24 | 无锡江南计算技术研究所 | Configurable consistency verification system with state monitoring function |
| CN112199291A (en) * | 2020-10-16 | 2021-01-08 | 天津飞腾信息技术有限公司 | Multi-core processor Cache consistency simulation verification method and verification device |
| CN114428749A (en) * | 2022-04-07 | 2022-05-03 | 沐曦科技(北京)有限公司 | Detector for verifying cache |
| CN115643124A (en) * | 2022-06-23 | 2023-01-24 | 南京轶诺科技有限公司 | PC simulation automobile CAN bus communication system |
| CN116795728A (en) * | 2023-08-25 | 2023-09-22 | 中电科申泰信息科技有限公司 | Multi-core cache consistency verification module and method based on UVM |
| CN116962259A (en) * | 2023-09-21 | 2023-10-27 | 中电科申泰信息科技有限公司 | Consistency processing method and system based on monitoring-directory two-layer protocol |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436521A (en) * | 2011-09-27 | 2012-05-02 | 浪潮(北京)电子信息产业有限公司 | Random verification method and system |
-
2012
- 2012-09-07 CN CN2012103290806A patent/CN102880537A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436521A (en) * | 2011-09-27 | 2012-05-02 | 浪潮(北京)电子信息产业有限公司 | Random verification method and system |
Non-Patent Citations (1)
| Title |
|---|
| 夏竞: "CC-NUMA系统中Cache一致性协议模拟验证方法研究", 《中国优秀硕士学位论文全文数据库工程科技辑2011年》, no. 1, 15 December 2011 (2011-12-15) * |
Cited By (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014110922A1 (en) * | 2013-01-18 | 2014-07-24 | 浪潮电子信息产业股份有限公司 | Extended cache coherence protocol-based multi-level coherence domain simulation verification and test method |
| CN103150264A (en) * | 2013-01-18 | 2013-06-12 | 浪潮电子信息产业股份有限公司 | Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method |
| EP2869194A4 (en) * | 2013-01-18 | 2016-08-03 | Inspur Electronic Information Industry Co Ltd | Extended cache coherence protocol-based multi-level coherence domain simulation verification and test method |
| CN103415085B (en) * | 2013-07-15 | 2016-08-10 | 同济大学 | A kind of automatic generation method of general MAC protocol processor |
| CN103415085A (en) * | 2013-07-15 | 2013-11-27 | 同济大学 | Automatic generation method of general MAC protocol processor |
| CN103488505B (en) * | 2013-09-16 | 2016-03-30 | 杭州华为数字技术有限公司 | Patch method, equipment and system |
| CN103488505A (en) * | 2013-09-16 | 2014-01-01 | 杭州华为数字技术有限公司 | Patching method, device and system |
| CN104317736A (en) * | 2014-09-28 | 2015-01-28 | 曙光信息产业股份有限公司 | Method for implementing multi-level caches in distributed file system |
| CN104317736B (en) * | 2014-09-28 | 2017-09-01 | 曙光信息产业股份有限公司 | A kind of distributed file system multi-level buffer implementation method |
| CN104360944A (en) * | 2014-11-12 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | Automated testing method and system |
| CN106155853B (en) * | 2015-03-23 | 2018-09-14 | 龙芯中科技术有限公司 | The verification method of processor IP, device and system |
| CN106155853A (en) * | 2015-03-23 | 2016-11-23 | 龙芯中科技术有限公司 | The verification method of processor IP, device and system |
| CN108027775A (en) * | 2015-09-24 | 2018-05-11 | 高通股份有限公司 | Avoid using and retry and respond the deadlock in the non-system based on processor for retrying bus consistency protocol in order |
| EP3355525A4 (en) * | 2015-10-15 | 2018-08-01 | Huawei Technologies Co., Ltd. | Computing apparatus, node device, and server |
| US10366006B2 (en) | 2015-10-15 | 2019-07-30 | Huawei Technologies Co., Ltd. | Computing apparatus, node device, and server |
| CN105404572A (en) * | 2015-12-08 | 2016-03-16 | 北京时代民芯科技有限公司 | Cache system formal verification method based on traversal search storage model |
| CN106933750A (en) * | 2015-12-31 | 2017-07-07 | 北京国睿中数科技股份有限公司 | For data in multi-level buffer and the verification method and device of state |
| CN105930299A (en) * | 2016-04-25 | 2016-09-07 | 浪潮电子信息产业股份有限公司 | BFM-based SystemVerilog protocol verification platform building method |
| CN105930299B (en) * | 2016-04-25 | 2018-11-27 | 浪潮电子信息产业股份有限公司 | BFM-based SystemVerilog protocol verification platform building method |
| CN106201881A (en) * | 2016-07-12 | 2016-12-07 | 桂林电子科技大学 | A kind of CSP concurrent system adjustment method based on ASP |
| CN106201881B (en) * | 2016-07-12 | 2019-02-01 | 桂林电子科技大学 | A kind of CSP concurrent system adjustment method based on ASP |
| CN110727611A (en) * | 2019-09-09 | 2020-01-24 | 无锡江南计算技术研究所 | Configurable consistency verification system with state monitoring function |
| CN110727611B (en) * | 2019-09-09 | 2022-01-07 | 无锡江南计算技术研究所 | Configurable consistency verification system with state monitoring function |
| CN110674055A (en) * | 2019-09-11 | 2020-01-10 | 上海高性能集成电路设计中心 | Cache consistency simulation verification method for component level and component combination level |
| CN110674055B (en) * | 2019-09-11 | 2023-10-03 | 上海高性能集成电路设计中心 | Cache consistency simulation verification method for component level and component joint level |
| CN112199291A (en) * | 2020-10-16 | 2021-01-08 | 天津飞腾信息技术有限公司 | Multi-core processor Cache consistency simulation verification method and verification device |
| CN114428749A (en) * | 2022-04-07 | 2022-05-03 | 沐曦科技(北京)有限公司 | Detector for verifying cache |
| CN115643124A (en) * | 2022-06-23 | 2023-01-24 | 南京轶诺科技有限公司 | PC simulation automobile CAN bus communication system |
| CN116795728A (en) * | 2023-08-25 | 2023-09-22 | 中电科申泰信息科技有限公司 | Multi-core cache consistency verification module and method based on UVM |
| CN116795728B (en) * | 2023-08-25 | 2023-10-27 | 中电科申泰信息科技有限公司 | Multi-core cache consistency verification module and method based on UVM |
| CN116962259A (en) * | 2023-09-21 | 2023-10-27 | 中电科申泰信息科技有限公司 | Consistency processing method and system based on monitoring-directory two-layer protocol |
| CN116962259B (en) * | 2023-09-21 | 2024-02-13 | 中电科申泰信息科技有限公司 | Consistency processing method and system based on monitoring-directory two-layer protocol |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102880537A (en) | Software simulation verification method based on Cache coherence protocol | |
| CN103150264B (en) | Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method | |
| WO2016197768A1 (en) | Chip verification method, device, and system | |
| CN100476837C (en) | MPU FPGA verification device supporting stochastic instruction testing | |
| CN102508753B (en) | IP (Internet protocol) core verification system | |
| CN108376221A (en) | A kind of software system security verification and appraisal procedure based on AADL model extensions | |
| CN115130402B (en) | Cache verification method, system, electronic equipment and readable storage medium | |
| CN110674055B (en) | Cache consistency simulation verification method for component level and component joint level | |
| US20160267209A1 (en) | Design and verification of a multichip coherence protocol | |
| CN111859832B (en) | Chip simulation verification method and device and related equipment | |
| CN113486625B (en) | Chip verification method and verification system | |
| US9058463B1 (en) | Systems and methods for specifying. modeling, implementing and verifying IC design protocols | |
| CN105205205A (en) | Method for FPGA coarse-grained parallel wiring based on optimal division of netlist position information | |
| CN111353266B (en) | Verification system and verification method for cooperative work among integrated circuit modules | |
| CN103713940A (en) | Method for reconfigurable distributed real-time simulation based on RTX-HLA reflection storage card | |
| CN105959176A (en) | Consistency protocol testing method and consistency protocol testing system based on Gem5 simulator | |
| CN105701294A (en) | Method and system for realizing complex project modification of chips | |
| US9477806B2 (en) | System-level analysis with transactions from protocol probes | |
| Carmona et al. | Compatibility in a multi-component environment | |
| CN114706768A (en) | I3C bus verification method and verification system | |
| CN113033785B (en) | Chip, neural network training system, memory management method, device and equipment | |
| Tarasyuk et al. | Formal development and quantitative assessment of a resilient multi-robotic system | |
| CN110727611B (en) | Configurable consistency verification system with state monitoring function | |
| US9619608B1 (en) | Concurrent design process | |
| US20140067358A1 (en) | Determining an optimal global quantum for an event-driven simulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130116 |