CN112199291A - Multi-core processor Cache consistency simulation verification method and verification device - Google Patents
Multi-core processor Cache consistency simulation verification method and verification device Download PDFInfo
- Publication number
- CN112199291A CN112199291A CN202011109721.8A CN202011109721A CN112199291A CN 112199291 A CN112199291 A CN 112199291A CN 202011109721 A CN202011109721 A CN 202011109721A CN 112199291 A CN112199291 A CN 112199291A
- Authority
- CN
- China
- Prior art keywords
- consistency
- verification
- cache
- protocol
- transaction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012795 verification Methods 0.000 title claims abstract description 118
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004088 simulation Methods 0.000 title claims abstract description 35
- 238000012360 testing method Methods 0.000 claims abstract description 50
- 230000005284 excitation Effects 0.000 claims abstract description 35
- 238000013508 migration Methods 0.000 claims abstract description 10
- 230000005012 migration Effects 0.000 claims abstract description 10
- 238000012545 processing Methods 0.000 claims description 27
- 230000015654 memory Effects 0.000 claims description 25
- 238000012423 maintenance Methods 0.000 claims description 23
- 238000013461 design Methods 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 16
- 238000013142 basic testing Methods 0.000 claims description 9
- 238000007639 printing Methods 0.000 claims description 9
- 239000003999 initiator Substances 0.000 claims description 7
- 230000006399 behavior Effects 0.000 claims description 6
- 238000012544 monitoring process Methods 0.000 claims description 6
- 238000012805 post-processing Methods 0.000 claims description 4
- 230000007547 defect Effects 0.000 claims description 3
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 238000005457 optimization Methods 0.000 claims description 3
- 238000010200 validation analysis Methods 0.000 claims 7
- 230000007704 transition Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 230000006872 improvement Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000013507 mapping Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3676—Test management for coverage analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a Cache consistency simulation verification method and a verification device for a multi-core processor, wherein the verification method comprises the following steps: configuring a verification environment and verification excitation, and performing excitation test in the verification environment; and after the excitation test is finished, coverage rate collection and performance statistics are carried out, and whether the system carries out correct migration of the state according to the protocol requirements is judged through global protocol correctness check. The authentication apparatus is constructed based on the authentication method described above. The invention has the advantages of simple principle, simple and convenient operation, good verification effect and the like.
Description
Technical Field
The invention mainly relates to the technical field of Cache memories, in particular to a Cache consistency simulation verification method and a Cache consistency simulation verification device suitable for a multi-core processor.
Background
In processor design, Cache (Cache memory) is a primary memory existing between a processor core and a main memory, and in a multi-core processor system, Cache consistency is a problem. When a plurality of caches contain the same data block, if any one of the caches modifies the data block without notifying other caches, the situation of data inconsistency is generated. Cache consistency is a protocol for maintaining the consistency of data of a plurality of caches. The design of the Cache consistency protocol is one of core technologies of a multi-core processor system, and therefore, the verification of the Cache consistency is very important work.
At present, a software simulation method is generally adopted for verifying the consistency of the Cache, and as the consistency protocol of the Cache is increasingly complex, the states and paths to be covered in the verification are increased in geometric multiples, and the complexity of the verification environment is higher and higher. The existing verification methods are all constructed manually, and much time is consumed to develop a perfect verification model and a test excitation set in the initial verification stage. Meanwhile, in terms of coverage collection, a verifier usually needs to invest a great deal of effort to write a complete coverage group and assertion, so as to ensure completeness of verification. In addition, in the aspect of reusability, the traditional verification method is not based on the UVM verification methodology, and the verification environment still needs long debugging time when being integrated from a module level to a subsystem level and a system level. In conclusion, the whole cache consistency verification period is time-consuming.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a Cache consistency simulation verification method and a verification device for a multi-core processor, which have the advantages of simple principle, simple and convenient operation and good verification effect.
In order to solve the technical problems, the invention adopts the following technical scheme:
a multi-core processor Cache consistency simulation verification method is provided, which comprises configuring a verification environment and verification excitation, and performing excitation test in the verification environment; and after the excitation test is finished, coverage rate collection and performance statistics are carried out, and whether the system carries out correct migration of the state according to the protocol requirements is judged through global protocol correctness check.
As a further improvement of the process of the invention: and on the basis that the relevant state of the consistency protocol and the execution result of the message flow are verified, checking whether the global data consistency meets the protocol requirement.
As a further improvement of the process of the invention: and when the verification environment is configured, generating corresponding basic test excitation and random test excitation according to the number of the request nodes needing to be configured.
As a further improvement of the process of the invention: generating a coverage rate model by filling a coverage rate table of a consistency protocol; and after the excitation is finished, collecting the coverage rate, and continuously carrying out iterative tests according to the coverage rate data until the coverage rate reaches 100%.
As a further improvement of the process of the invention: the coverage rate table comprises the message type to be verified, legal values of each domain segment of the message, a migration path of the Cache state and illegal state determination.
As a further improvement of the process of the invention: carrying out random pressure test through the generated random test excitation, carrying out protocol processing flow correctness check in real time, and carrying out result check and performance statistics on all requests after the test; and if the random pressure test does not pass, searching the access transaction flow according to the error reporting information of the correctness check, determining error points, and executing the random pressure test again after the errors are eliminated.
As a further improvement of the process of the invention: and (4) counting the performance of the access transaction, and determining the performance defect and the optimization direction.
As a further improvement of the process of the invention: the process of the global protocol correctness checking unit comprises the following steps:
step S11: collecting data packets processed by a protocol at a design interface, and comparing the data packets with data packets of a standard protocol model to judge whether the processing process is correct or not; firstly, judging whether a request transaction at an inlet is correct according to a Cache state read by a back door, ensuring that an issued request conforms to protocol regulations, setting validity of a domain segment of each message in a transaction processing flow to check, and recording and printing error transaction information when an illegal state is found;
step S12: after the simulation is finished, checking a buffer queue in the design to be verified, wherein the buffer queue in the design is empty after all things are correctly processed, and if not, indicating that an unfinished transaction exists, and forming related information of the unfinished transaction for analysis;
step S13: and collecting data flow at the interface of the request node and data flow at the interface of the memory, comparing, checking whether input data and output data of the system are consistent, and verifying whether a path from the request node to the memory is correct.
As a further improvement of the process of the invention: the performance statistics process comprises the following steps:
step S21: recording and storing the initiation time of the transaction according to the ID of each memory access transaction and the ID of the request node, and recording and printing the end time of the transaction when the processing of the transaction is judged to be ended;
step S22: and performing post-processing of performance statistics, namely collecting performance statistical data in the printing information, outputting the starting and ending time, the processing time and the transaction type of each transaction as a table, and analyzing to obtain performance information such as bandwidth, delay, reading and writing speed and the like.
The invention further provides a Cache consistency simulation verification device of the multi-core processor, which comprises the following steps:
the verification environment generation unit is used for generating a complete verification environment comprising a UVM component and an interface according to the interconnection structure of the Cache, the storage and the processor core of the processor to be verified;
the verification excitation generating unit is used for generating required test excitation according to the configured interconnection structure of the multi-core processor;
the coverage rate generation unit is used for generating a coverage rate model, adding the generated coverage rate model to the verification environment and finishing the collection of the coverage rate of the consistency protocol;
the global protocol correctness checking unit is used for checking the real-time correctness of the whole flow of the consistency protocol processing;
and the performance statistic unit is used for collecting information and carrying out performance statistics on the access transaction processing flow.
As a further improvement of the device of the invention: the verification environment generation unit realizes the interconnection structure of a plurality of processor cores, a plurality of Cache consistency maintenance units and a plurality of memories through the generated verification environment simulation, and realizes the verification of each part in the consistency protocol.
As a further improvement of the device of the invention: the verification environment generation unit carries out transaction-level simulation verification of the protocol, and records the processing flow of the access and storage behaviors including real-time behaviors and states in the whole running process.
As a further improvement of the device of the invention: the components include one or more of a requesting node, a master node (e.g., a consistency maintenance node), and a slave node (storage node).
As a further improvement of the device of the invention: the test stimulus comprises a basic test stimulus for path verification; the basic test excitation for path verification refers to that each request initiator sends read-after-write operation to a memory for verifying whether a data path is correct, and additionally comprises that each request initiator sends consistency request operation to the same address for verifying whether a consistency maintenance node can correctly send monitoring operation and verifying whether a monitoring path between a request node and a consistency maintenance node is correct.
As a further improvement of the device of the invention: the test excitation also comprises random test excitation, and the random test excitation comprises random type access transactions of a plurality of request nodes to the same Cache address, random type access transactions to continuous Cache addresses and random type access transactions to random Cache addresses; the method also comprises fixed-type access transactions of a plurality of request nodes to the same Cache address, continuous Cache address and random Cache address.
As a further improvement of the device of the invention: the coverage rate generating unit is used for filling a coverage rate table according to the used consistency protocol, and describing the existing transaction types, legal attributes of each field section of each transaction, legal Cache states and migration, interface signals, bit width and hardware hierarchical structures in detail; after the coverage rate table is completely filled, the coverage rate generation script completes generation of a coverage rate model and required hardware connection according to the filled table, and then the generated coverage rate model is added to a file list to complete collection of the coverage rate of the consistency protocol.
Compared with the prior art, the invention has the advantages that:
1. the multi-core processor Cache consistency simulation verification method and the verification device have the advantages of simple principle, simple and convenient operation and good verification effect, can improve the building efficiency of the Cache consistency verification environment, and can greatly shorten the time for the verifier to build the environment and develop the excitation particularly for the super-large-scale multi-core processor system at the present stage. Meanwhile, the use of the correctness checking tool and the coverage rate model can help engineers to search design errors more efficiently, and focus on writing of directional test stimuli, so that verification has stronger pertinence.
2. According to the method and the device for simulating and verifying the Cache consistency of the multi-core processor, the performance statistical unit can provide performance data of Cache consistency design, and guidance is provided for designers to optimize the design. Meanwhile, the unit has strong portability, and can be used in the UVM verification environment generated by the invention and other verification environments adopting the same Cache consistency protocol.
3. The invention discloses a simulation verification method and a verification device for consistency of a Cache of a multi-core processor. The method can effectively verify the Cache consistency protocol in the multi-state space of the multi-core processor, and judge whether the consistency processing flow of the design system conforms to the protocol regulation or not through a global checking tool. The verification device has the remarkable advantages that the verification environment which can be used can be rapidly generated, the debugging time of verification personnel to the environment is reduced, the verification efficiency is remarkably improved, and the verification convergence is accelerated.
Drawings
FIG. 1 is a flow chart of the verification method of the present invention in a specific application example.
Fig. 2 is a schematic structural diagram of an authentication device of the present invention in a specific application example.
FIG. 3 is a schematic diagram of a verification environment designed to be verified by a consistency maintenance node in an embodiment of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
The Cache consistency software simulation Verification method provided by the invention can be based on a Universal Verification Methodology (UVM) according to actual needs, a Verification environment generation tool and a Verification excitation generation tool are configured according to design and Verification requirements, a coverage rate collection and performance statistics tool is added, and whether the system carries out correct execution of a message flow and correct migration of a state according to protocol requirements is judged through a correctness checking tool. In addition, on the basis that the relevant state of the consistency protocol and the execution result of the message flow are verified, a correctness checking tool is further used for checking whether the global data consistency is correct or not.
As shown in fig. 1, the method for verifying Cache consistency simulation of a multi-core processor according to the present invention takes verifying a consistency maintenance node in a consistency protocol processing flow as an example, and the flow includes:
step S1: configuring a verification environment, configuring an excitation generating unit according to the number of request nodes to be configured, and generating corresponding basic test excitation and random test excitation; the address space needs to be configured when generating the stimulus.
The specific process is as follows: and setting the number of corresponding request nodes and the number of corresponding storage nodes according to the number of consistency maintenance nodes needing to be verified, wherein the address mapping mode and the memory attribute in the verification environment generation tool may need to be modified according to the verification requirement.
The address mapping mode relates to the address range managed by each consistency maintenance node, and the attribute relates to the memory attribute of the address field. In addition, hardware connection between the consistency protocol input/output interface and the access data input/output interface in the definite design is needed, and an interface module generation tool in the verification environment is modified.
Step S2: and completing construction and excitation preparation of a verification environment, and on the basis, filling a coverage rate table of a consistency protocol, including the type of the message to be verified, legal values of each domain section of the message, a migration path of a Cache state, illegal state determination and the like, to generate a coverage rate model.
Step S3: the generated verification environment is integrated with the generated test stimulus to initiate a pathway test.
Step S4: if the basic path test is passed, continue to execute step S5, otherwise check the test environment and execute step S1 again.
Step S5: and adding the random test excitation generated in the step S1, starting to perform a random pressure test, and opening a performance statistics and correctness checking tool. If the random pressure test passes, go to step S7, otherwise go to step S6.
Step S6: and if the random pressure test does not pass, searching the access transaction flow according to the error information reported by the correctness checking tool, determining error points, and after errors are eliminated, executing the step S5 again.
Step S7: the coverage model generated in step S2 is added to collect the coverage.
Step S8: and (4) counting the performance of the access transaction by adopting a performance counting post-processing tool, and determining the performance defect and the optimization direction.
Step S9: in general, after the execution of step S5 is finished, the coverage rate may not reach 100%, it is determined that the test stimulus needs to be added according to the coverage rate data collected in step S7, and after the test is passed, step S7 is repeatedly executed, and the iteration is continued until the coverage rate reaches 100%.
In a specific application example, a schematic diagram of the verification environment generated by the verification environment generation unit and the verification stimulus generation unit according to the present invention is shown in fig. 3, in which:
and the verification environment is a UVM framework, and a corresponding number of request nodes, consistency maintenance nodes and storage node models are set according to different configurations.
Taking the verification consistency maintenance node in the embodiment as an example, the request node model needs to simulate a request initiator of Cache consistency operation, a driver is needed to send test excitation to a design to be verified, and transaction feedback from the consistency maintenance node of the design to be verified is received to perform next access operation.
The storage node also needs to receive the access operation of the design consistency maintenance node to be verified, and needs to store the written data so that the next access operation can read out correct data.
Unlike the request node model and the storage node model, the consistency maintenance node model does not need to actively respond to the received consistency request operation, only needs to collect all message information of Cache consistency access and storage operation, generates potential correct response message information according to the collected consistency request message information, compares the potential correct response message information with the response given by the consistency maintenance node to be verified, and needs to perform error checking if an error occurs.
After the global data consistency check tool is added, the data collected by the consistency maintenance node model from the consistency interface needs to be compared with the data collected by the storage node model from the access data interface, so as to ensure the correctness of the data of the whole system.
Outside the UVM verification environment, a verification top layer exists, generated interface connection and test excitation are connected into the verification environment, and the whole verification structure is clearer.
As shown in fig. 2, based on the verification method of the present invention, the present invention further provides a device for verifying Cache consistency simulation of a multi-core processor, which includes:
and the verification environment generation unit is used for generating a complete verification environment comprising the UVM component and the interface connection according to the Cache, the storage and the interconnection structure of the processor core of the processor to be verified.
And the verification stimulus generating unit is used for generating required test stimulus according to the configured interconnection structure of the multi-core processor.
And the coverage rate generation unit is used for generating a coverage rate model, adding the generated coverage rate model to the verification environment and finishing the collection of the coverage rate of the consistency protocol.
And the global protocol correctness checking unit is used for checking the real-time correctness of the whole flow of the processing of the consistency protocol and the correctness of the processing result.
And the performance statistic unit is used for collecting information and carrying out performance statistics on the access transaction processing flow.
In a specific application example, the verification environment generation unit can simulate and realize interconnection structures of a plurality of processor cores, a plurality of Cache consistency maintenance units and a plurality of memories through the generated verification environment, so as to realize the verification of each component in the consistency protocol. Furthermore, transaction-level simulation verification of the protocol can be carried out, and the processing flow of the access behavior is recorded in the whole running process, including the real-time behaviors and states of transaction types and attributes, Cache state migration, access data information and the like.
In actual application, the components comprise a request node, a consistency maintenance node, a storage node and the like;
the UVM verification component has strong inheritability and configurable functions, and does not need to be rewritten along with the modification inside the design under the condition that the adopted consistency protocol is not changed. A plurality of function interfaces are reserved in the verification environment, and the verification environment can be conveniently and specifically adjusted according to requirements.
In a specific application example, the test stimulus comprises a basic test stimulus for path verification. The basic test excitation for path verification refers to that each request initiator sends read-after-write operation to a memory for verifying whether a data path is correct, and additionally comprises that each request initiator sends consistency request operation to the same address for verifying whether a consistency maintenance node can correctly send monitoring operation and verifying whether a monitoring path between a request node and a consistency maintenance node is correct.
In a specific application example, as a preferred scheme, the test stimulus further comprises a large number of random test stimuli, including random type access transactions of a plurality of request nodes to the same Cache address, random type access transactions to continuous Cache addresses, and random type access transactions to random Cache addresses; furthermore, fixed-type memory access transactions from a plurality of request nodes to the same Cache address, continuous Cache address and random Cache address can be included according to actual needs.
In a specific application example, the coverage rate generating unit first needs to fill in a coverage rate table according to a used consistency protocol, and describe in detail information such as a specific existing transaction type, legal attributes of each field segment of each transaction, a legal Cache state and migration, interface signals, bit width, and a hardware hierarchy. After the coverage rate table is completely filled, the coverage rate generation script completes generation of a coverage rate model and required hardware connection according to the filled table, and then the generated coverage rate model is added to a file list of a verification environment to complete collection of the coverage rate of the consistency protocol.
In a specific application example, the work flow of the global protocol correctness checking unit is as follows:
step S11: and collecting data packets of the protocol processing flow at the design interface, and comparing the data packets with data packets of the standard protocol model to judge whether the processing process is correct. Firstly, judging whether the request transaction type at the consistency interface is correct according to the Cache state read by a back door, ensuring that the sent request conforms to the protocol regulation, setting the legitimacy of the domain segment of each message in the transaction processing flow for checking, and recording and printing wrong transaction information when an illegal state is found.
Step S12: after the simulation is finished, the correctness checking tool checks a buffer queue in the design to be verified, after all things are correctly processed, the buffer queue in the design is empty, if not, the fact that the affairs which cannot be processed are existed is indicated, and related information of the unprocessed affairs is printed out for being analyzed by a verifier.
Step S13: and collecting data flow at the interface of the request node and data flow at the interface of the memory, comparing, checking whether input data and output data of the system are consistent, and verifying whether a path from the request node to the memory is correct. In general, the information such as address and ID is different between the time when data enters the design to be verified and is processed in a transaction and the time when the data is written into the memory, so that a callback function is needed to map the written information and the written information according to a certain rule, and the two are guaranteed to be data streams of the same transaction when data comparison is performed.
In a specific application example, the workflow of the performance statistics tool is as follows:
step S21: and recording and storing the initiation time of the transaction according to the ID of each memory access transaction and the ID of the request node, and recording and printing the end time of the transaction when the processing of the transaction is judged to be ended.
Step S22: by adopting a post-processing tool of performance statistics and collecting performance statistical data in the printing information, the starting and ending time, the processing time and the transaction type of each transaction can be output as a table, and the performance information such as bandwidth, delay, reading and writing speed and the like can be obtained by analysis.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (16)
1. A multi-core processor Cache consistency simulation verification method is characterized in that a verification environment and verification excitation are configured, and excitation test is carried out in the verification environment; and after the excitation test is finished, coverage rate collection and performance statistics are carried out, and whether the system carries out correct migration of the state according to the protocol requirements is judged through global protocol correctness check.
2. The multi-core processor Cache consistency simulation verification method according to claim 1, wherein on the basis that the consistency protocol related state and the message flow execution result are verified, whether the global data consistency meets the protocol requirement is checked.
3. The method for simulation verification of Cache consistency of a multi-core processor according to claim 1, wherein corresponding basic test stimuli and random test stimuli are generated according to the number of request nodes to be configured when a verification environment is configured.
4. The multi-core processor Cache consistency simulation verification method according to claim 1, wherein a coverage model is generated by filling in a coverage table of a consistency protocol; and after the excitation is finished, collecting the coverage rate, and continuously carrying out iterative tests according to the coverage rate data until the coverage rate reaches 100%.
5. The simulation verification method for Cache consistency of the multi-core processor according to claim 4, wherein the coverage rate table comprises message types to be verified, legal values of each domain segment of the message, migration paths of Cache states, and determination of illegal states.
6. The multi-core processor Cache consistency simulation verification method according to claim 1, characterized by performing random pressure testing and protocol processing flow correctness checking by means of generated random test excitation, wherein the correctness checking includes real-time and post-test checks, and results checking and performance statistics are performed on all requests after the test; and if the random pressure test does not pass, searching the access transaction flow according to the error reporting information of the correctness check, determining error points, and executing the random pressure test again after the errors are eliminated.
7. The multi-core processor Cache consistency simulation verification method as claimed in claim 1, wherein the performance of the memory access transaction is counted, and the performance defect and the optimization direction are determined.
8. The multi-core processor Cache consistency simulation verification method according to claim 1, wherein the flow of the global protocol correctness checking unit comprises:
step S11: collecting data packets processed by a protocol at a design interface, comparing the data packets with data packets of a standard protocol model, and judging whether the processing process is correct or not; firstly, judging whether a request transaction at an inlet is correct according to a Cache state read by a back door, ensuring that an issued request conforms to protocol regulations, setting validity of a domain segment of each message in a transaction processing flow to check, and recording and printing error transaction information when an illegal state is found;
step S12: after the simulation is finished, checking a buffer queue in the design to be verified, wherein the buffer queue in the design is empty after all things are correctly processed, and if not, indicating that an unfinished transaction exists, and forming related information of the unfinished transaction for analysis;
step S13: and collecting data flow at the interface of the request node and data flow at the interface of the memory, comparing, checking whether input data and output data of the system are consistent, and verifying whether a path from the request node to the memory is correct.
9. The method for simulation verification of Cache consistency of a multi-core processor according to claim 1, wherein the flow of performance statistics comprises:
step S21: recording and storing the initiation time of the transaction according to the ID of each memory access transaction and the ID of the request node, and recording and printing the end time of the transaction when the processing of the transaction is judged to be ended;
step S22: and performing post-processing of performance statistics, namely collecting performance statistical data in the printing information, outputting the starting and ending time, the processing time and the transaction type of each transaction as a table, and analyzing to obtain performance information such as bandwidth, delay, reading and writing speed and the like.
10. A multi-core processor Cache consistency simulation verification device is characterized by comprising:
the verification environment generation unit is used for generating a complete verification environment comprising a UVM component and an interface according to the interconnection structure of the Cache, the storage and the processor core of the processor to be verified;
the verification excitation generating unit is used for generating required test excitation according to the configured interconnection structure of the multi-core processor;
the coverage rate generation unit is used for generating a coverage rate model, adding the generated coverage rate model to a file list and finishing the collection of the coverage rate of the consistency protocol;
the global protocol correctness checking unit is used for checking the real-time correctness of the whole flow of the consistency protocol processing;
and the performance statistic unit is used for collecting information and carrying out performance statistics on the access transaction processing flow.
11. The device for performing Cache consistency simulation validation on a multi-core processor according to claim 10, wherein the validation environment generation unit is configured to implement, through simulation of the generated validation environment, an interconnection structure among the plurality of processor cores, the plurality of Cache consistency maintenance units, and the plurality of memories, and to implement validation on each component in the consistency protocol.
12. The device for performing Cache consistency simulation validation on a multi-core processor according to claim 11, wherein the validation environment generation unit performs transaction-level simulation validation on a protocol, and records a processing flow of memory access behaviors including real-time behaviors and states during running.
13. The multi-core processor Cache consistency simulation verification apparatus as claimed in claim 12, wherein the components comprise one or more of a request node, a consistency maintenance node, and a storage node.
14. The multi-core processor Cache consistency simulation verification device according to claim 10, wherein the test stimulus comprises a basic test stimulus for path verification; the basic test excitation for path verification refers to that each request initiator sends read-after-write operation to a memory for verifying whether a data path is correct, and additionally comprises that each request initiator sends consistency request operation to the same address for verifying whether a consistency maintenance node can correctly send monitoring operation and verifying whether a monitoring path between a request node and a consistency maintenance node is correct.
15. The multi-core processor Cache consistency simulation verification device according to claim 10, wherein the test stimulus further comprises a random test stimulus, and the random test stimulus comprises random type access transactions of a plurality of request nodes to the same Cache address, random type access transactions to a continuous Cache address, and random type access transactions to a random Cache address; the method also comprises fixed-type access transactions of a plurality of request nodes to the same Cache address, continuous Cache address and random Cache address.
16. The device for simulating and verifying the Cache consistency of the multi-core processor according to claim 10, wherein the coverage generating unit is configured to fill a coverage table according to the used consistency protocol, and describe in detail the existing transaction types and legal attributes, legal Cache states and transitions, interface signals, bit widths, and hardware hierarchies of each field segment of each transaction; after the coverage rate table is completely filled, the coverage rate generation script completes generation of a coverage rate model and required hardware connection according to the filled table, and then the generated coverage rate model is added to a verification environment to complete collection of the coverage rate of the consistency protocol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011109721.8A CN112199291A (en) | 2020-10-16 | 2020-10-16 | Multi-core processor Cache consistency simulation verification method and verification device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011109721.8A CN112199291A (en) | 2020-10-16 | 2020-10-16 | Multi-core processor Cache consistency simulation verification method and verification device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112199291A true CN112199291A (en) | 2021-01-08 |
Family
ID=74009853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011109721.8A Pending CN112199291A (en) | 2020-10-16 | 2020-10-16 | Multi-core processor Cache consistency simulation verification method and verification device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112199291A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112948200A (en) * | 2021-02-01 | 2021-06-11 | 湖南品腾电子科技有限公司 | MCU-based memory reusability verification system and method |
| CN113535499A (en) * | 2021-07-22 | 2021-10-22 | 无锡江南计算技术研究所 | Multi-type concurrent memory access flow verification method supporting multi-core shared access |
| CN113807046A (en) * | 2021-10-09 | 2021-12-17 | 中国人民解放军国防科技大学 | Test excitation optimization regression verification method, system and medium |
| CN114238004A (en) * | 2022-02-21 | 2022-03-25 | 北京燧原智能科技有限公司 | Method and device for checking data transmission correctness of interconnected circuit and electronic equipment |
| CN114580344A (en) * | 2022-04-24 | 2022-06-03 | 飞腾信息技术有限公司 | Test excitation generation method, verification system and related equipment |
| CN115130402A (en) * | 2022-08-30 | 2022-09-30 | 北京开源芯片研究院 | Cache verification method, system, electronic equipment and readable storage medium |
| CN116795728A (en) * | 2023-08-25 | 2023-09-22 | 中电科申泰信息科技有限公司 | Multi-core cache consistency verification module and method based on UVM |
| CN117687928A (en) * | 2024-01-29 | 2024-03-12 | 中电科申泰信息科技有限公司 | Multiprocessor core cache consistency verification module and method based on UVM |
| CN117762718A (en) * | 2024-02-21 | 2024-03-26 | 北京壁仞科技开发有限公司 | Instruction monitoring method, device, equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6332178B1 (en) * | 1997-11-26 | 2001-12-18 | Compaq Computer Corporation | Method for estimating statistics of properties of memory system transactions |
| CN102880537A (en) * | 2012-09-07 | 2013-01-16 | 浪潮电子信息产业股份有限公司 | Software simulation verification method based on Cache coherence protocol |
| CN103150264A (en) * | 2013-01-18 | 2013-06-12 | 浪潮电子信息产业股份有限公司 | Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method |
| CN103455364A (en) * | 2013-09-05 | 2013-12-18 | 北京航空航天大学 | System and method for online obtaining Cache performance of parallel program under multi-core environment |
| CN111611120A (en) * | 2020-06-28 | 2020-09-01 | 中国人民解放军国防科技大学 | Method, system and medium for verifying Cache consistency protocol of on-chip multi-core processor |
-
2020
- 2020-10-16 CN CN202011109721.8A patent/CN112199291A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6332178B1 (en) * | 1997-11-26 | 2001-12-18 | Compaq Computer Corporation | Method for estimating statistics of properties of memory system transactions |
| CN102880537A (en) * | 2012-09-07 | 2013-01-16 | 浪潮电子信息产业股份有限公司 | Software simulation verification method based on Cache coherence protocol |
| CN103150264A (en) * | 2013-01-18 | 2013-06-12 | 浪潮电子信息产业股份有限公司 | Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method |
| US20150095008A1 (en) * | 2013-01-18 | 2015-04-02 | Inspur Electronic Information Industry Co., Ltd | Extension cache coherence protocol-based multi-level coherency domain simulation verification and test method |
| CN103455364A (en) * | 2013-09-05 | 2013-12-18 | 北京航空航天大学 | System and method for online obtaining Cache performance of parallel program under multi-core environment |
| CN111611120A (en) * | 2020-06-28 | 2020-09-01 | 中国人民解放军国防科技大学 | Method, system and medium for verifying Cache consistency protocol of on-chip multi-core processor |
Non-Patent Citations (3)
| Title |
|---|
| 潘国腾: "CC-NUMA系统存储体系结构关键技术研究", 中国博士学文论文全文数据库 信息科技辑, 15 July 2009 (2009-07-15), pages 137 - 4 * |
| 王泽华: "基于UVM的Cache验证平台的设计与研究", 中国优秀硕士学位论文全文数据库 信息科技辑, 15 February 2020 (2020-02-15), pages 135 - 432 * |
| 范君健;晁张虎;杨庆娜;刘琪;朱红;单建旗;: "基于Cadence CHI和IVD VIP的多核SoC系统数据一致性验证", 电子技术应用, no. 08, 6 August 2020 (2020-08-06), pages 72 - 76 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112948200A (en) * | 2021-02-01 | 2021-06-11 | 湖南品腾电子科技有限公司 | MCU-based memory reusability verification system and method |
| CN113535499B (en) * | 2021-07-22 | 2023-10-27 | 无锡江南计算技术研究所 | Multi-type concurrent access memory stream verification method supporting multi-core shared access |
| CN113535499A (en) * | 2021-07-22 | 2021-10-22 | 无锡江南计算技术研究所 | Multi-type concurrent memory access flow verification method supporting multi-core shared access |
| CN113807046A (en) * | 2021-10-09 | 2021-12-17 | 中国人民解放军国防科技大学 | Test excitation optimization regression verification method, system and medium |
| CN113807046B (en) * | 2021-10-09 | 2024-05-31 | 中国人民解放军国防科技大学 | Test excitation optimization regression verification method, system and medium |
| CN114238004A (en) * | 2022-02-21 | 2022-03-25 | 北京燧原智能科技有限公司 | Method and device for checking data transmission correctness of interconnected circuit and electronic equipment |
| CN114238004B (en) * | 2022-02-21 | 2022-05-13 | 北京燧原智能科技有限公司 | Method and device for checking data transmission correctness of interconnected circuit and electronic equipment |
| CN114580344A (en) * | 2022-04-24 | 2022-06-03 | 飞腾信息技术有限公司 | Test excitation generation method, verification system and related equipment |
| CN115130402A (en) * | 2022-08-30 | 2022-09-30 | 北京开源芯片研究院 | Cache verification method, system, electronic equipment and readable storage medium |
| CN116795728A (en) * | 2023-08-25 | 2023-09-22 | 中电科申泰信息科技有限公司 | Multi-core cache consistency verification module and method based on UVM |
| CN116795728B (en) * | 2023-08-25 | 2023-10-27 | 中电科申泰信息科技有限公司 | Multi-core cache consistency verification module and method based on UVM |
| CN117687928A (en) * | 2024-01-29 | 2024-03-12 | 中电科申泰信息科技有限公司 | Multiprocessor core cache consistency verification module and method based on UVM |
| CN117687928B (en) * | 2024-01-29 | 2024-04-19 | 中电科申泰信息科技有限公司 | Multiprocessor core cache consistency verification module and method based on UVM |
| CN117762718A (en) * | 2024-02-21 | 2024-03-26 | 北京壁仞科技开发有限公司 | Instruction monitoring method, device, equipment and storage medium |
| CN117762718B (en) * | 2024-02-21 | 2024-04-26 | 北京壁仞科技开发有限公司 | Instruction monitoring method, device, equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112199291A (en) | Multi-core processor Cache consistency simulation verification method and verification device | |
| US8073820B2 (en) | Method and system for a database to monitor and analyze performance of an electronic design | |
| US7188061B2 (en) | Simulation monitors based on temporal formulas | |
| US8429457B2 (en) | Use of statistical representations of traffic flow in a data processing system | |
| CN109117518B (en) | System and method for verifying read-write access of register | |
| US20110307860A1 (en) | Simulation-based interface testing automation system and method for robot software components | |
| CN115130402B (en) | Cache verification method, system, electronic equipment and readable storage medium | |
| CN114528792B (en) | Chip verification method and device, electronic equipment and storage medium | |
| CN112417798B (en) | Time sequence testing method and device, electronic equipment and storage medium | |
| US8271252B2 (en) | Automatic verification of device models | |
| US6718521B1 (en) | Method and system for measuring and reporting test coverage of logic designs | |
| CN111832237A (en) | Intellectual property right verification method and system | |
| CN113887161A (en) | Verification method, device, equipment and medium for network-on-chip design example | |
| US8050902B2 (en) | Reporting temporal information regarding count events of a simulation | |
| Engels et al. | Model-based verification and validation of properties | |
| US6934656B2 (en) | Auto-linking of function logic state with testcase regression list | |
| CN111624475B (en) | Method and system for testing large-scale integrated circuit | |
| CN116663490A (en) | Verification method, platform, device and medium of asynchronous memory chip | |
| CN112463633B (en) | Method, device, equipment and medium for checking address decoding of on-chip memory | |
| US20230315964A1 (en) | Design aware adaptive mixed-signal simulation | |
| CN112632886B (en) | Method and apparatus for checking bus verification, electronic device and storage medium | |
| CN117313649B (en) | Chip simulation verification method and application device thereof | |
| CN117313650B (en) | Chip test verification method and application device thereof | |
| CN115630010A (en) | Serial design-oriented extensible form verification method and test method | |
| CN113806154A (en) | Test method, test system, test equipment and readable storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Fan Junjian Inventor after: Li Yujie Inventor after: Hu En Inventor after: Li Chen Inventor after: Chao Zhanghu Inventor after: Dai Meizhi Inventor after: Zhu Hong Inventor after: Bai Ying Inventor after: Yang Qingna Inventor after: Wang Zhongyi Inventor after: Jia Yaping Inventor after: Wang Hongling Inventor before: Fan Junjian Inventor before: Li Yujie Inventor before: Hu En Inventor before: Li Chen Inventor before: Chao Zhanghu Inventor before: Dai Meizhi Inventor before: Zhu Hong Inventor before: Bai Ying Inventor before: Yang Qingna Inventor before: Wang Zhongyi Inventor before: Jia Yaping Inventor before: Wang Hongling |
|
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 300452 Building 5, Xin'an pioneer Plaza, Binhai New Area marine high tech Development Zone, Tianjin Applicant after: Feiteng Information Technology Co.,Ltd. Address before: 300452 Building 5, Xin'an pioneer Plaza, Binhai New Area marine high tech Development Zone, Tianjin Applicant before: TIANJIN FEITENG INFORMATION TECHNOLOGY Co.,Ltd. |