CN106933750A - For data in multi-level buffer and the verification method and device of state - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
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Abstract
The invention discloses a kind of for data in multi-level buffer and the verification method and device of state, wherein the method includes：The first cache information for obtaining each cache lines in n-th grade of caching successively includes the first flag information and the first data message；The first physical address set that corresponding first physical address of each cache lines is constituted in being cached by n-th grade is obtained according to the first cache information；The second cache information for obtaining each cache lines in m grades of caching successively includes the second flag information and the second data message；The second physical address set that corresponding second physical address of each cache lines is constituted in being cached by m grades is obtained according to the second cache information；As the second physical address set contains the first physical address set, each cache lines in being cached to n-th grade are verified according to first, second cache information to the buffer status of Same Physical address.The method can not only verify the correctness of buffer status, moreover it is possible to improve the verification efficiency for verifying internuclear buffer consistency.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of verification method for data in multi-level buffer and state and
Device.
Background technology
Because the performance gap between processor and memory is increasing, it is possible to use the principle of locality of routine access is at place
Multi-level buffer is added between reason device and memory, therefore becomes weight for the checking of the multi-level buffer between processor and memory
Will.
In correlation technique, either carrying out whole-system verification to processor, or individually carrying out module level to storage system tests
Card, is all to apply excitation by input signal, detects output signal to judge the data correctness in multi-level buffer.
However, be only capable of realizing whether correctly verifying the data for caching by above-mentioned verification method, and in whole-system verification
When, specific scene can only be constructed by orienting test program, it is difficult to reach the requirement of Fast Convergent in verification process,
Cause to hide in the presence of undiscovered with performance-relevant BUG (failure), so as to cause processor performance to be lifted.
The content of the invention
The purpose of the present invention is intended at least solve to a certain extent one of technical problem in above-mentioned technology.
Therefore, first purpose of the invention be propose it is a kind of for data in multi-level buffer and the verification method of state, should
Method is able to verify that the correctness of buffer status, finds, by performance-relevant BUG caused by caching, to improve checking internuclear slow
Deposit the verification efficiency of uniformity.
Second object of the present invention be propose it is a kind of for data in multi-level buffer and the checking device of state.
It is that, up to above-mentioned purpose, first aspect present invention embodiment proposes the verification method for data in multi-level buffer and state,
Comprise the following steps：First cache information of each cache lines Cache_line in n-th grade of caching is obtained successively, wherein,
First cache information includes the first mark Tag information and the first data Data information, and n is positive integer；According to described
One cache information obtains the first physical address set of n-th grade of caching, wherein, first physical address set is by institute
State the first physical address composition corresponding to each cache lines Cache_line in n-th grade of caching；M grades of caching is obtained successively
In each cache lines Cache_line the second cache information, wherein, second cache information include second mark Tag
Information and the second data Data information, m is positive integer, and 0≤m-n≤1；According to second cache information is obtained
M grades caching the second physical address set, wherein, second physical address set by described m grade caching in each
The second physical address composition corresponding to cache lines Cache_line；Judge second physical address set whether comprising described
First physical address set；And if second physical address set includes the first physical address set, be then directed to
Each cache lines Cache_line in n-th grade of caching, according to first cache information and the second cache information to category
Buffer status in Same Physical address are verified.
It is according to embodiments of the present invention for data in multi-level buffer and the verification method of state, delay according to obtaining n-th grade successively
First cache information and corresponding first things of each cache lines Cache_line of each cache lines Cache_line in depositing
Reason address constitutes the first physical address set, according to obtain successively m grade cache in each cache lines Cache_line the
Two cache informations and corresponding second physical address of each cache lines Cache_line constitute the second physical address set, judge
Second physical address set includes the first physical address set, then each cache lines Cache_line in being cached for n-th grade,
The method can be verified to the buffer status for belonging to Same Physical address according to the first cache information and the second cache information
The correctness of buffer status is verified, finds, by performance-relevant BUG caused by caching, to improve the overall performance of processor,
And the checking effect for verifying internuclear buffer consistency can be improve by the state and data for checking internuclear visible buffer
Rate.
In one embodiment of the invention, it is described according to first cache information and the second cache information to belonging to same thing
Manage address buffer status verified, including：Determine the type for writing strategy of n-th grade of caching；If described n-th
The type for writing strategy of level caching is Write_through, then judged according to first cache information and the second cache information
Whether the buffer status for belonging to Same Physical address meet default design requirement；If it is described n-th grade caching write plan
Type slightly is Write_back, then determine whether the cache lines Cache_line belonged to corresponding to Same Physical address
In the state of Dirty whether be effective；If the cache lines Cache_line belonged to corresponding to Same Physical address
In the state of Dirty be effective, then belong to same according to first cache information and the second cache information judge
Whether the buffer status of physical address meet default design requirement；If the caching belonged to corresponding to Same Physical address
The state of Dirty in row Cache_line is invalid, then for the cache lines belonged to corresponding to Same Physical address
Cache_line, judges whether the first data Data information is consistent with the second data Data information；If described
First data Data information and the second data Data information are inconsistent, then judge data cached mistake in the multi-level buffer
By mistake；If the first data Data information is consistent with the second data Data information, according to the described first caching letter
Whether the buffer status for belonging to Same Physical address described in breath and the judgement of the second cache information meet default design requirement.
In one embodiment of the invention, first thing that n-th grade of caching is obtained according to first cache information
Reason address set, including：Each cache lines Cache_line in being cached for described n-th grade, according to the described first mark
Tag information is reduced the first physical address corresponding to each cache lines Cache_line in described n-th grade caching, is obtained
To described n-th grade the first physical address set of caching.
In one embodiment of the invention, second thing that the m grades of caching is obtained according to second cache information
Reason address set, including：Each cache lines Cache_line in being cached for described m grades, according to the described second mark
Tag information is reduced the second physical address corresponding to each cache lines Cache_line in described m grades caching, is obtained
To described m grades the second physical address set of caching.
In one embodiment of the invention, n-th grade of caching has instruction buffer and data buffer storage, when the instruction is slow
When depositing with the data source of data buffer storage as same (n+1)th grade caching, methods described also includes：The instruction is obtained respectively
The cache information of caching and data buffer storage；Cache information according to the instruction buffer and data buffer storage to the instruction buffer and
The state of data buffer storage is verified；If the state of the instruction buffer and data buffer storage is all effective and dirty, judge
The status error of the instruction buffer and data buffer storage.
It is that, up to above-mentioned purpose, second aspect present invention embodiment proposes a kind of checking for data in multi-level buffer and state
Device, including：First acquisition module, for obtaining each cache lines Cache_line in n-th grade of caching successively first
Cache information, wherein, first cache information includes the first mark Tag information and the first data Data information, and n is for just
Integer；Second acquisition module, the first physical address collection for obtaining n-th grade of caching according to first cache information
Close, wherein, first physical address set cached as described n-th grade in corresponding to each cache lines Cache_line the
One physical address is constituted；3rd acquisition module, for obtaining each cache lines Cache_line's in m grades of caching successively
Second cache information, wherein, second cache information includes the second mark Tag information and the second data Data information, m
It is positive integer, and 0≤m-n≤1；4th acquisition module, delays for obtaining described m grades according to second cache information
The the second physical address set deposited, wherein, second physical address set is by each cache lines in described m grades caching
The second physical address composition corresponding to Cache_line；Judge module, for whether judging second physical address set
Comprising the first physical address set；And authentication module, for judging second physical address in the judge module
When set is comprising the first physical address set, each cache lines Cache_line in being cached for described n-th grade, root
The buffer status for belonging to Same Physical address are verified according to first cache information and the second cache information.
It is according to embodiments of the present invention for data in multi-level buffer and the checking device of state, according to the first acquisition module successively
The first cache information and the second acquisition module for obtaining each cache lines Cache_line in n-th grade of caching delay according to each
Deposit corresponding first physical address of row Cache_line and constitute the first physical address set, the 3rd acquisition module according to obtaining successively
Second cache information and the 4th acquisition module of each cache lines Cache_line in m grades of caching are according to each cache lines
Corresponding second physical address of Cache_line constitutes the second physical address set, and judge module judges the second physical address set
Comprising the first physical address set, authentication module is directed to each cache lines Cache_line in n-th grade of caching, according to first
Cache information and the second cache information are verified to the buffer status for belonging to Same Physical address.The device is able to verify that caching
The correctness of state, finds, by performance-relevant BUG caused by caching, to improve the overall performance of processor, it is possible to logical
The state and data for checking internuclear visible buffer are crossed, the verification efficiency for verifying internuclear buffer consistency is improve.
In one embodiment of the invention, the authentication module includes：Determining unit, for determining n-th grade of caching
Write strategy type；Authentication unit, when the type for writing strategy for being cached at described n-th grade is Write_through,
Whether the buffer status for belonging to Same Physical address according to first cache information and the second cache information judge meet pre-
If design requirement；First judging unit, when the type for writing strategy for being cached at described n-th grade is Write_back,
Whether the state of Dirty in the cache lines Cache_line for belonging to corresponding to Same Physical address described in judging is effective；
The authentication unit is additionally operable to belonging to the cache lines corresponding to Same Physical address described in first judging unit judgement
The state of Dirty in Cache_line for it is effective when, institute is judged according to first cache information and the second cache information
State and belong to the buffer status of Same Physical address and whether meet default design requirement；Second judging unit, for described
One judging unit judge described in belong to corresponding to Same Physical address cache lines Cache_line in the state of Dirty be
When invalid, for the cache lines Cache_line belonged to corresponding to Same Physical address, the first data Data is judged
Whether information is consistent with the second data Data information；The authentication unit is additionally operable to judge institute in second judging unit
It is data cached in the judgement multi-level buffer when stating the first data Data information and inconsistent the second data Data information
Mistake, and judge that the first data Data information is consistent with the second data Data information in second judging unit
When, whether the buffer status for belonging to Same Physical address according to first cache information and the second cache information judge accord with
Close default design requirement.
In one embodiment of the invention, second acquisition module specifically for：It is every in being cached for described n-th grade
Individual cache lines Cache_line, each cache lines during described n-th grade is cached according to the described first mark Tag information
The first physical address corresponding to Cache_line is reduced, and obtains the first physical address set of n-th grade of caching.
In one embodiment of the invention, the 4th acquisition module specifically for：It is every in being cached for described m grades
Individual cache lines Cache_line, each cache lines during described m grades is cached according to the described second mark Tag information
The second physical address corresponding to Cache_line is reduced, and obtains the second physical address set of the m grades of caching.
In one embodiment of the invention, n-th grade of caching has instruction buffer and data buffer storage, when the instruction is slow
When depositing with the data source of data buffer storage as same (n+1)th grade caching, first acquisition module is additionally operable to：Obtain respectively
The cache information of the instruction buffer and data buffer storage；The authentication module is additionally operable to：It is slow according to the instruction buffer and data
The cache information deposited verifies to the state of the instruction buffer and data buffer storage, and in the instruction buffer and data buffer storage
State it is all effective and dirty, then judge the status error of the instruction buffer and data buffer storage.
The additional aspect of the present invention and advantage will be set forth in part in the description, and partly will from the following description become bright
It is aobvious, or recognized by practice of the invention.
Brief description of the drawings
The above-mentioned and/or additional aspect of the present invention and advantage will be apparent from the following description of the accompanying drawings of embodiments
Be readily appreciated that, wherein：
Fig. 1 is according to an embodiment of the invention for data in multi-level buffer and the flow chart of the verification method of state；
Fig. 2 is in accordance with another embodiment of the present invention for data in multi-level buffer and the flow chart of the verification method of state；
Fig. 3 is for data in multi-level buffer and the flow chart of the verification method of state according to another embodiment of the invention；
Fig. 4 is for data in multi-level buffer and the flow of the verification method of state according to one specific embodiment of the present invention
Figure；
Fig. 5 is the 1 of intel i7 according to embodiments of the present invention, the checking schematic diagram of level 2 cache memory structure；
Fig. 6 is the structural representation for data in multi-level buffer and the checking device of state according to an embodiment of the invention
Figure；
Fig. 7 is the structural representation of authentication module according to an embodiment of the invention.
Specific embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein identical from start to finish
Or similar label represents same or similar element or the element with same or like function.Retouched below with reference to accompanying drawing
The embodiment stated is exemplary, it is intended to for explaining the present invention, and be not considered as limiting the invention.
It should be noted that main thought of the invention is：Higher level caching that necessarily lower level time is cached
Collection, then also the inevitable buffer status with lower level time are consistent higher level buffer status.Therefore, using this
Characteristic, the present invention proposes a kind of verification method and device for data in multi-level buffer and state to realize according to be measured
The state of itself is designed to carry out self checking to the current state for caching.Specifically, the present invention is below with reference to the accompanying drawings described to implement
Example for data in multi-level buffer and the verification method and device of state.
Fig. 1 is for data in multi-level buffer and the flow chart of the verification method of state according to one embodiment of the invention.
As shown in figure 1, the verification method for being used for data and state in multi-level buffer can include：
S11, obtains first cache information of each cache lines Cache_line in n-th grade of caching successively, wherein, first
Cache information includes the first mark Tag information and the first data Data information, and n is positive integer.
S12, n-th grade of first physical address set of caching is obtained according to the first cache information, wherein, the first physical address collection
The first physical address in being cached by n-th grade corresponding to each cache lines Cache_line is closed to constitute.
Specifically, n-th grade of first physical address set of caching is obtained according to the first cache information, is specifically included：For
Each cache lines Cache_line in n-th grade of caching, each caching during n-th grade is cached according to the first mark Tag information
The first physical address corresponding to row Cache_line is reduced, and obtains n-th grade of first physical address set of caching.
S13, obtains second cache information of each cache lines Cache_line in m grades of caching successively, wherein, second
Cache information includes the second mark Tag information and the second data Data information, and m is positive integer, and 0≤m-n≤1.
S14, m grades of the second physical address set of caching is obtained according to the second cache information, wherein, the second physical address collection
The second physical address in being cached by m grades corresponding to each cache lines Cache_line is closed to constitute.
Specifically, m grades of the second physical address set of caching is obtained according to the second cache information, including：For m
Each cache lines Cache_line in level caching, each cache lines during m grades is cached according to the second mark Tag information
The second physical address corresponding to Cache_line is reduced, and obtains m grades of the second physical address set of caching.
Whether S15, judge the second physical address set comprising the first physical address set.
S16, if the second physical address set includes the first physical address set, each caching in being cached for n-th grade
The buffer status for belonging to Same Physical address are tested by row Cache_line according to the first cache information and the second cache information
Card.
Specifically, the buffer status for belonging to Same Physical address are tested according to the first cache information and the second cache information
Card, as shown in Fig. 2 including：
S161, determines n-th grade of type for writing strategy of caching.
Specifically, pre-defined design manual can be obtained, and determines that this n-th grade is delayed according to the pre-defined design manual
That deposits writes the type of strategy.
S162, if n-th grade of type for writing strategy of caching is for Write_through, according to the first cache information and the
Two cache informations judge whether the buffer status for belonging to Same Physical address meet default design requirement.
S163, if the type for writing strategy of n-th grade of caching is Write_back, determines whether to belong to Same Physical ground
Whether the state of Dirty in cache lines Cache_line corresponding to location is effective.
S164, if the state for belonging to Dirty in the cache lines Cache_line corresponding to Same Physical address is effective,
Then judge whether the buffer status for belonging to Same Physical address meet default setting according to the first cache information and the second cache information
Meter is required.
S165, if the state for belonging to Dirty in the cache lines Cache_line corresponding to Same Physical address is invalid,
Then for the cache lines Cache_line belonged to corresponding to Same Physical address, the first data Data information and the second number are judged
It is whether consistent according to Data information.
S166, if the first data Data information and the second data Data information are inconsistent, judges to be cached in multi-level buffer
Error in data.
S167, if the first data Data information is consistent with the second data Data information, according to the first cache information and
Two cache informations judge whether the buffer status for belonging to Same Physical address meet default design requirement.
That is, whether will with default design for the buffer status of Same Physical address in more adjacent two-level cache
The state asked meets, wherein, can first determine n-th grade of type for writing strategy of caching, entered according to the type for writing strategy afterwards
The different verification operation of row.For example, being write back in n-th grade of caching, strategy is Write_back and its state is effective and non-dirty
In the case of, then needing to compare n-th grade of caching and the m grades of data message of the corresponding cache_line of caching, data must be consistent,
Until the cache_line information of all of n-th grade caching compares completion.It is corresponding with m grades of caching in n-th grade of caching
The data message of cache_line compares after completion, and some design engineers are self-defined or optional slow in also checking caching
Attribute is deposited, the state of these attributes has to consistent, the lock functions such as under MIPS ISA of being described with design manual.
Regulation caching can be addition lock functions in MIPS handbooks, for the improving performance under special scenes.When this
When the lock states of cache_line are 1, the cache_line can not also have the cache_line of other non-lock in the set
In the case of be replaced away.Detect that whether correct the state situation of the function be as follows：As n-th grade of cache_line of caching
During for lock states, physical address relative m grades state of caching also necessarily lock therewith.In these and performance
The related check post unrelated with function cannot be authenticated in accidental validation.
To sum up, the verification method of the embodiment of the present invention is mainly what the caching between adjacent two-stage was verified, and every level
Caching is not required to compare, and such as m grades of caching need not carry out state vs with m+2 grades of caching.Comparative sequence should be from the superlative degree
It is cached to lowermost level caching successively to compare, it is ensured that per adjacent two-level cache data with state consistency.
If it should be noted that n-th grade is cached with multiple cachings, and data source in these cachings is from same the
N+1 grades of caching, then be also required to compare the state of the two cachings.As a kind of example, when n-th grade of caching has instruction slow
Deposit and data buffer storage, when the data source of instruction buffer and data buffer storage is for same (n+1)th grade caching, as shown in figure 3,
The method also includes：
S31, obtains the cache information of instruction buffer and data buffer storage respectively.
S32, the cache information according to instruction buffer and data buffer storage is verified to the state of instruction buffer and data buffer storage.
S33, if the state of instruction buffer and data buffer storage is all effective and dirty, decision instruction is cached and data buffer storage
Status error.
That is, caching at the same level is also required to be checked that is, instruction buffer is also required to be contrasted with data buffer storage：First
Obtain the information of instruction buffer and data buffer storage respectively, after obtaining instruction and the information of data buffer storage, with wherein any one
Physical address in caching is index, goes another to be searched in caching, if the state of two cachings is all effective and dirty,
Illustrate the status error of instruction buffer and data buffer storage.It is appreciated that the content of the checking of the embodiment of the present invention can be according to be measured
The specific definition of design is defined.
It is according to embodiments of the present invention for data in multi-level buffer and the verification method of state, delay according to obtaining n-th grade successively
First cache information and corresponding first things of each cache lines Cache_line of each cache lines Cache_line in depositing
Reason address constitutes the first physical address set, according to obtain successively m grade cache in each cache lines Cache_line the
Two cache informations and corresponding second physical address of each cache lines Cache_line constitute the second physical address set, judge
Second physical address set includes the first physical address set, then each cache lines Cache_line in being cached for n-th grade,
The method can be verified to the buffer status for belonging to Same Physical address according to the first cache information and the second cache information
The correctness of buffer status is verified, finds, by performance-relevant BUG caused by caching, to improve the overall performance of processor,
And the checking effect for verifying internuclear buffer consistency can be improve by the state and data for checking internuclear visible buffer
Rate.
In order that obtaining those skilled in the art can clearly understand the present invention, it is slow for multistage with the embodiment of the present invention
Deposit as a example by the verification method of data and state verifies to the 1 of intel i7, level 2 cache memory, and combine Fig. 4 and Fig. 5
The present invention is described in further detail.Fig. 4 be according to one specific embodiment of the present invention for data in multi-level buffer and
The flow chart of the verification method of state.Fig. 5 is testing for the 1 of intel i7 according to embodiments of the present invention, level 2 cache memory structure
Card schematic diagram.Wherein, as shown in figure 5, instruction buffer (icache) is 1 grade of caching with data buffer storage (dcache),
Second caching (scache) is L2 cache, writes back strategy and is write_back.Virtual address is 48bit, physically
Location is 36bit, and cache_line sizes are 512bit.The mapping mode of instruction buffer is 4 tunnel group phases, data buffer storage and two
The mapping mode of level caching is connected for 8 tunnel groups.Level cache is 32KB, and L2 cache is 256KB.Level cache is virtual
Index, physical label；L2 cache is indexed for physics, physical label.
As shown in figure 4, the verification method may include：
Obtain first of each cache lines Cache_line in the 1st grade of caching in intel i7 successively by S401 first
Cache information, tag the and data information in icache is taken out, and S402 calculates the Cache_line in icache
Corresponding effective physical address, and the state and data message of icache are put into Icache_info as shown in Figure 5 move
In state array, each cache lines Cache_line in the level 2 cache memory in intel i7 is then obtained successively by S403
The second cache information, by scache tag and data information take out, S404 calculate scache in Cache_line
Corresponding effective physical address, and the state and data message of scache are put into Scache_info as shown in Figure 5 move
In state array.Afterwards, S405, as index, is looked into using effective physical address in Icache_info in Scache_info
Ask, if not inquiring corresponding informance, illustrate buffer status mistake.Then, S406 is examined to icache states
Test, because the strategy that writes back of the level cache of intel i7 is write_back, so in having to detection buffer status
Dirty, for example, judge whether Dirty in the Icache_info corresponding to effective physical address be 1, if
It is not 1, then needs to compare the data message of the two-level cache corresponding to the physical address, if data are inconsistent, illustrates
Data cached mistake；If data are consistent, in addition it is also necessary to which S407 checks the customized buffer status information of design.When all of slow
When the state for depositing the description of state and design documentation is consistent, S408 carries out in next instruction caching effective physical address again
Compare, until effective physical address is completeer in all instruction buffers, and obtain assay result1 as shown in Figure 5,
After the status checkout of instruction buffer and L2 cache passes through, in addition it is also necessary to which data buffer storage is checked with the state of L2 cache,
Its comparison process is consistent with the control methods of instruction buffer and L2 cache, obtains assay result2 as shown in Figure 5.
It is corresponding with the verification method for data in multi-level buffer and state that above-mentioned several embodiments are provided, of the invention one
Kind of embodiment also provides a kind of for data in multi-level buffer and the checking device of state, due to use provided in an embodiment of the present invention
The testing for data in multi-level buffer and state that the checking device of data and state and above-described embodiment are provided in multi-level buffer
Card method is corresponding, therefore the implementation method of the verification method of data and state is also applied for this in multi-level buffer is previously used for
Embodiment provide for data in multi-level buffer and the checking device of state, be not described in detail in the present embodiment.Fig. 6
It is for data in multi-level buffer and the structural representation of the checking device of state according to one embodiment of the invention.Such as Fig. 6
Shown, the device can include：First acquisition module 100, the second acquisition module 200, the 3rd acquisition module the 300, the 4th
Acquisition module 404, judge module 500 and authentication module 600.
Wherein, the first acquisition module 100 is used to obtain successively first of each cache lines Cache_line in n-th grade of caching
Cache information, wherein, the first cache information includes the first mark Tag information and the first data Data information, and n is positive integer.
Second acquisition module 200 is used to obtain n-th grade of first physical address set of caching according to the first cache information, wherein,
First physical address of the first physical address set corresponding to each cache lines Cache_line in n-th grade of caching is constituted.
Specifically, the second acquisition module 200 specifically for：Each cache lines Cache_line in being cached for n-th grade,
The first physical address during described n-th grade is cached according to the first mark Tag information corresponding to each cache lines Cache_line
Reduced, obtained n-th grade of first physical address set of caching.
The second caching letter of each cache lines Cache_line that the 3rd acquisition module 300 is used to obtain successively in m grades of caching
Breath, wherein, the second cache information includes the second mark Tag information and the second data Data information, and m is positive integer, and 0
≤m-n≤1。
4th acquisition module 400 is used to obtain m grades of the second physical address set of caching according to the second cache information, wherein,
Second physical address of the second physical address set corresponding to each cache lines Cache_line in m grades of caching is constituted.
Specifically, the 4th acquisition module 400 specifically for：Each cache lines Cache_line in being cached for m grades,
The second physical address during m grades is cached according to the second mark Tag information corresponding to each cache lines Cache_line is carried out
Reduction, obtains m grades of the second physical address set of caching.
Whether judge module 500 is used to judge the second physical address set comprising the first physical address set.
Authentication module 600 is used for when judge module 500 judges that the second physical address set includes the first physical address set,
Each cache lines Cache_line in being cached for n-th grade, according to the first cache information and the second cache information to belonging to same
The buffer status of one physical address are verified.
Specifically, in one embodiment of the invention, as shown in fig. 7, the authentication module 600 can include：It is determined that
Unit 601, authentication unit 602, the first judging unit 603 and the second judging unit 604.
Specifically, it is determined that unit 601 is used to determine n-th grade of type for writing strategy of caching.
Authentication unit 602 is used for when the type for writing strategy of n-th grade of caching is Write_through, according to the first caching
Information and the second cache information judge whether the buffer status for belonging to Same Physical address meet default design requirement.
First judging unit 603 is used for when the type for writing strategy of n-th grade of caching is Write_back, and judgement belongs to same
Whether the state of Dirty in cache lines Cache_line corresponding to physical address is effective.
Authentication unit 602 is additionally operable to judge to belong to the cache lines corresponding to Same Physical address in the first judging unit 603
The state of Dirty in Cache_line for it is effective when, judge to belong to same according to the first cache information and the second cache information
Whether the buffer status of one physical address meet default design requirement.
Second judging unit 604 is used to judge to belong to the cache lines corresponding to Same Physical address in the first judging unit 603
The state of Dirty in Cache_line for it is invalid when, for the cache lines belonged to corresponding to Same Physical address
Cache_line, judges whether the first data Data information is consistent with the second data Data information.
Authentication unit 602 is additionally operable to judge the first data Data information and the second data Data letters in the second judging unit 604
When ceasing inconsistent, data cached mistake in multi-level buffer is judged, and judge that the first data Data believes in the second judging unit 604
When breath is consistent with the second data Data information, judge to belong to Same Physical address according to the first cache information and the second cache information
Buffer status whether meet default design requirement.
Wherein, in one embodiment of the invention, n-th grade of caching has instruction buffer and data buffer storage, works as instruction buffer
During with the data source of data buffer storage for same (n+1)th grade caching, the first acquisition module 100 is additionally operable to：Obtain respectively and refer to
The cache information of order caching and data buffer storage.Authentication module 600 is additionally operable to the cache information according to instruction buffer and data buffer storage
State to instruction buffer and data buffer storage verifies, and all effective and dirty in the state of instruction buffer and data buffer storage,
Then decision instruction caches the status error with data buffer storage.
It is according to embodiments of the present invention for data in multi-level buffer and the checking device of state, according to the first acquisition module successively
The first cache information and the second acquisition module for obtaining each cache lines Cache_line in n-th grade of caching delay according to each
Deposit corresponding first physical address of row Cache_line and constitute the first physical address set, the 3rd acquisition module according to obtaining successively
Second cache information and the 4th acquisition module of each cache lines Cache_line in m grades of caching are according to each cache lines
Corresponding second physical address of Cache_line constitutes the second physical address set, and judge module judges the second physical address set
Comprising the first physical address set, authentication module is directed to each cache lines Cache_line in n-th grade of caching, according to first
Cache information and the second cache information verify that the method is able to verify that caching to the buffer status for belonging to Same Physical address
The correctness of state, finds, by performance-relevant BUG caused by caching, to improve the overall performance of processor, it is possible to logical
The state and data for checking internuclear visible buffer are crossed, the verification efficiency for verifying internuclear buffer consistency is improve.
In the description of the invention, it is to be understood that term " first ", " second " are only used for describing purpose, and can not
It is interpreted as indicating or implying relative importance or the implicit quantity for indicating indicated technical characteristic.Thus, define " the
One ", at least one this feature can be expressed or be implicitly included to the feature of " second ".In the description of the invention, " multiple "
It is meant that at least two, such as two, three etc., unless otherwise expressly limited specifically.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specific example ",
Or the description of " some examples " etc. means to combine specific features, structure, material or feature that the embodiment or example are described
It is contained at least one embodiment of the invention or example.In this manual, the schematic representation to above-mentioned term need not
Identical embodiment or example must be directed to.And, the specific features of description, structure, material or feature can be with office
Combined in an appropriate manner in one or more embodiments or example.Additionally, in the case of not conflicting, this area
Technical staff can be tied the feature of the different embodiments or example described in this specification and different embodiments or example
Close and combine.
Any process described otherwise above or method description in flow chart or herein is construed as, and expression includes one
Or more for the module of code of executable instruction the step of realizing specific logical function or process, fragment or part,
And the scope of the preferred embodiment of the present invention includes other realization, wherein order that is shown or discussing can not be pressed,
Including the function involved by basis by it is basic simultaneously in the way of or in the opposite order, carry out perform function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
Represent in flow charts or logic and/or step described otherwise above herein, for example, being considered for reality
The order list of the executable instruction of existing logic function, in may be embodied in any computer-readable medium, for instruction
Execution system, device or equipment (such as computer based system, including the system of processor or other can be performed from instruction
The system of system, device or equipment instruction fetch and execute instruction) use, or with reference to these instruction execution systems, device or set
It is standby and use.For the purpose of this specification, " computer-readable medium " can any can be included, store, communicating, propagating
Or transmission procedure is used for instruction execution system, device or equipment or with reference to these instruction execution systems, device or equipment
Device.The more specifically example (non-exhaustive list) of computer-readable medium includes following：With one or more cloth
The electrical connection section (electronic installation) of line, portable computer diskette box (magnetic device), random access memory (RAM) is read-only
Memory (ROM), erasable edit read-only storage (EPROM or flash memory), fiber device, and it is portable
Compact disc read-only memory (CDROM).In addition, computer-readable medium can even is that the paper that can thereon print described program
Or other suitable media, because optical scanner for example can be carried out by paper or other media, then enter edlin, solution
Translate or if necessary processed with other suitable methods and electronically obtain described program, be then stored in computer
In memory.
It should be appreciated that each several part of the invention can be realized with hardware, software, firmware or combinations thereof.In above-mentioned reality
In applying mode, software that multiple steps or method can in memory and by suitable instruction execution system be performed with storage or
Firmware is realized.If for example, realized with hardware, and in another embodiment, can be with well known in the art
Any one of row technology or their combination are realized：With the logic gates for realizing logic function to data-signal
Discrete logic, the application specific integrated circuit with suitable combinational logic gate circuit, programmable gate array (PGA) is existing
Field programmable gate array (FPGA) etc..
Those skilled in the art be appreciated that to realize all or part of step that above-described embodiment method is carried is can
Completed with the hardware that correlation is instructed by program, described program can be stored in a kind of computer-readable recording medium,
The program upon execution, including one or a combination set of the step of embodiment of the method.
Additionally, during each functional unit in each embodiment of the invention can be integrated in a processing module, or each
Individual unit is individually physically present, it is also possible to which two or more units are integrated in a module.Above-mentioned integrated module was both
Can be realized in the form of hardware, it would however also be possible to employ the form of software function module is realized.If the integrated module with
The form of software function module is realized and as independent production marketing or when using, it is also possible to which storage is in a computer-readable
In taking storage medium.
Storage medium mentioned above can be read-only storage, disk or CD etc..Although having been shown and described above
Embodiments of the invention, it is to be understood that above-described embodiment is exemplary, it is impossible to be interpreted as limitation of the present invention,
One of ordinary skill in the art can be changed to above-described embodiment, change, replacing and modification within the scope of the invention.
Claims (10)
1. it is a kind of for data in multi-level buffer and the verification method of state, it is characterised in that to comprise the following steps：
First cache information of each cache lines Cache_line in n-th grade of caching is obtained successively, wherein, described first delays
Depositing information includes the first mark Tag information and the first data Data information, and n is positive integer；
The first physical address set of n-th grade of caching is obtained according to first cache information, wherein, first thing
First physical address of the reason address set corresponding to each cache lines Cache_line in described n-th grade caching is constituted；
Second cache information of each cache lines Cache_line in m grades of caching is obtained successively, wherein, described second delays
Depositing information includes the second mark Tag information and the second data Data information, and m is positive integer, and 0≤m-n≤1；
The second physical address set of the m grades of caching is obtained according to second cache information, wherein, second thing
Second physical address of the reason address set corresponding to each cache lines Cache_line in described m grades caching is constituted；
Judge second physical address set whether comprising the first physical address set；And
If second physical address set includes the first physical address set, in being cached for described n-th grade
Each cache lines Cache_line, delays according to first cache information and the second cache information to belonging to Same Physical address
The state of depositing is verified.
2. the verification method of data and state in multi-level buffer is used for as claimed in claim 1, it is characterised in that described
The buffer status for belonging to Same Physical address are verified according to first cache information and the second cache information, including：
Determine the type for writing strategy of n-th grade of caching；
If the type for writing strategy of n-th grade of caching is for Write_through, according to first cache information and
Whether the buffer status for belonging to Same Physical address described in the judgement of the second cache information meet default design requirement；
If the type for writing strategy of n-th grade of caching is for Write_back, determine whether described to belong to Same Physical
Whether the state of Dirty in cache lines Cache_line corresponding to address is effective；
If the state of Dirty in the cache lines Cache_line belonged to corresponding to Same Physical address is effective,
Whether the buffer status for then belonging to Same Physical address according to first cache information and the second cache information judge meet
Default design requirement；
If the state of Dirty in the cache lines Cache_line belonged to corresponding to Same Physical address is invalid,
Then for the cache lines Cache_line belonged to corresponding to Same Physical address, the first data Data information is judged
It is whether consistent with the second data Data information；
If the first data Data information and the second data Data information are inconsistent, the multi-level buffer is judged
In data cached mistake；
If the first data Data information is consistent with the second data Data information, according to the described first caching letter
Whether the buffer status for belonging to Same Physical address described in breath and the judgement of the second cache information meet default design requirement.
3. the verification method of data and state in multi-level buffer is used for as claimed in claim 1, it is characterised in that described
The first physical address set of n-th grade of caching is obtained according to first cache information, including：
Each cache lines Cache_line in being cached for described n-th grade, according to the described first mark Tag information by described in
The first physical address in n-th grade of caching corresponding to each cache lines Cache_line is reduced, and is obtained described n-th grade and is delayed
The the first physical address set deposited.
4. the verification method of data and state in multi-level buffer is used for as claimed in claim 1, it is characterised in that described
The second physical address set of the m grades of caching is obtained according to second cache information, including：
Each cache lines Cache_line in being cached for described m grades, according to the described second mark Tag information by described in
The second physical address in m grades of caching corresponding to each cache lines Cache_line is reduced, and is obtained described m grades and is delayed
The the second physical address set deposited.
5. the verification method of data and state in multi-level buffer is used for as claimed in claim 1, it is characterised in that wherein,
N-th grade of caching has instruction buffer and data buffer storage, when the data source of the instruction buffer and data buffer storage is same
During individual (n+1)th grade of caching, methods described also includes：
The cache information of the instruction buffer and data buffer storage is obtained respectively；
Cache information according to the instruction buffer and data buffer storage is tested the state of the instruction buffer and data buffer storage
Card；
If the state of the instruction buffer and data buffer storage is all effective and dirty, judge that the instruction buffer and data are slow
The status error deposited.
6. a kind of for data in multi-level buffer and the checking device of state, it is characterised in that including：
First acquisition module, the first cache information for obtaining each cache lines Cache_line in n-th grade of caching successively,
Wherein, first cache information includes the first mark Tag information and the first data Data information, and n is positive integer；
Second acquisition module, the first physical address set for obtaining n-th grade of caching according to first cache information,
Wherein, the first thing during first physical address set is cached as described n-th grade corresponding to each cache lines Cache_line
Reason address composition；
3rd acquisition module, the second cache information for obtaining each cache lines Cache_line in m grades of caching successively,
Wherein, second cache information includes the second mark Tag information and the second data Data information, and m is positive integer, and 0
≤m-n≤1；
4th acquisition module, the second physical address set for obtaining the m grades of caching according to second cache information,
Wherein, the second thing during second physical address set is cached as described m grades corresponding to each cache lines Cache_line
Reason address composition；
Judge module, for judging second physical address set whether comprising the first physical address set；And
Authentication module, for judging that second physical address set includes the first physical address collection in the judge module
During conjunction, each cache lines Cache_line in being cached for described n-th grade is slow according to first cache information and second
Information is deposited to verify the buffer status for belonging to Same Physical address.
7. the checking device of data and state in multi-level buffer is used for as claimed in claim 6, it is characterised in that described to test
Card module includes：
Determining unit, the type for writing strategy for determining n-th grade of caching；
When authentication unit for the type for writing strategy in described n-th grade caching is Write_through, according to described the
One cache information and the second cache information judge whether the buffer status for belonging to Same Physical address meet default design and want
Ask；
First judging unit, for when the described n-th grade type for writing strategy of caching is for Write_back, judging the category
Whether the state of Dirty in the cache lines Cache_line corresponding to Same Physical address is effective；
The authentication unit is additionally operable to belonging to the cache lines corresponding to Same Physical address described in first judging unit judgement
The state of Dirty in Cache_line for it is effective when, institute is judged according to first cache information and the second cache information
State and belong to the buffer status of Same Physical address and whether meet default design requirement；
Second judging unit, for belonging to the cache lines corresponding to Same Physical address described in first judging unit judgement
The state of Dirty in Cache_line for it is invalid when, for the cache lines belonged to corresponding to Same Physical address
Cache_line, judges whether the first data Data information is consistent with the second data Data information；
The authentication unit is additionally operable to judge the first data Data information and second number in second judging unit
According to Data information it is inconsistent when, judge data cached mistake in the multi-level buffer, and judge institute in second judging unit
State the first data Data information it is consistent with the second data Data information when, it is slow according to first cache information and second
Deposit information judge described in belong to the buffer status of Same Physical address and whether meet default design requirement.
8. the as claimed in claim 6 checking device for being used for data and state in multi-level buffer, it is characterised in that described the
Two acquisition modules specifically for：
Each cache lines Cache_line in being cached for described n-th grade, according to the described first mark Tag information by described in
The first physical address in n-th grade of caching corresponding to each cache lines Cache_line is reduced, and is obtained described n-th grade and is delayed
The the first physical address set deposited.
9. the as claimed in claim 6 checking device for being used for data and state in multi-level buffer, it is characterised in that described the
Four acquisition modules specifically for：
Each cache lines Cache_line in being cached for described m grades, according to the described second mark Tag information by described in
The second physical address in m grades of caching corresponding to each cache lines Cache_line is reduced, and is obtained described m grades and is delayed
The the second physical address set deposited.
10. the checking device of data and state in multi-level buffer is used for as claimed in claim 6, it is characterised in that wherein,
N-th grade of caching has instruction buffer and data buffer storage, when the data source of the instruction buffer and data buffer storage is same
During individual (n+1)th grade of caching,
First acquisition module is additionally operable to：The cache information of the instruction buffer and data buffer storage is obtained respectively；
The authentication module is additionally operable to：Cache information according to the instruction buffer and data buffer storage is to the instruction buffer sum
Verified according to the state of caching, and it is all effective and dirty in the state of the instruction buffer and data buffer storage, then judge institute
State the status error of instruction buffer and data buffer storage.
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