CN101859281A - Method for embedded multi-core buffer consistency based on centralized directory - Google Patents
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Abstract
The invention discloses a method for embedded multi-core buffer consistency based on a centralized directory. In the invention, partial state conversion is optimized according to the detail contents of hardware implementation, and the buffer consistency based on the centralized directory is realized by two strategies of a write-back method and a write-allocate method. The invention has the main functions of sharing a plurality of processor cores in a secondary buffer and ensuring the copy consistency of the same data block in private buffers of the processor cores. By adopting directional message transmission, bandwidth pressure brought by a broadcast mechanism is lightened, and the interference on the normal operation of irrelevant processors is avoided. The invention has favorable extendibility and is suitable for embedded multi-core system processors.
Description
Technical field
The present invention relates to polycaryon processor system field, relate in particular to a kind of method for embedded multi-core buffer consistency based on centralized directory.
Background technology
Following microprocessor chip structure is more and more emphasized the stratification of structure, the modularization and the distribution of functional part, makes each functional part all relatively simple, and components interior keeps the locality of line as far as possible.In the case, the chip multi-core structure of higher degree of parallelism is arisen at the historic moment.Chip multi-core processor CMP (Chip Multi-Processor) is a kind of architecture Design that occurs in the nineties in 20th century, be researchist's proposition at first by Stanford Univ USA, its thought is to utilize the abundant a plurality of processor cores of transistor resources integration on single chip, develops degree of parallelisms at all levels such as instruction-level, thread-level by the mode of multi-core parallel concurrent execution and improves performance.
The CMP structure is one of important exploration that utilizes by magnanimity integrated level structure novel high-performance processor, with the extensively good and acceptance of advantages such as its good extensibility, reusability, low-power consumption and tolerance wire delay, become the development trend of present high-performance microprocessor architecture by industry.After entering 21 century, main microprocessor manufacturer develops the multi-core CPU based on CMP successively,, as the Power6[12 of IBM], the OpenSparcT1[13 of Sun], the Montecito[14 of Intel] etc.At the microprocessor of specific area, design as IBM and Sony, Toshiba's cooperation, be used for the Cell processor [15] of graphics workstation and PS3 game machine, and mainly also released the polycaryon processor framework towards MIPS, the ARM microprocessor of built-in field.
Memory hierarchy always is the key factor of restriction processor performance, and the performance of operational performance depends on the efficient provision of memory access subsystem to operational data in very big degree.In the multi-core CPU environment, the multithreading that a plurality of processors move is simultaneously competed storage resources such as the limited buffer memory of single-chip, bandwidth, cause memory access conflict aggravation, traditional memory access bottleneck will become more outstanding, and storage system is one of key factor of decision polycaryon processor performance.
In multi-core CPU, each processor all has own privately owned buffer memory, and shares in L2 cache, three grades of buffer memorys or main memory rank.Yet,, when improving the memory access performance, can produce the buffer consistency problem because the copy of same data block in the privately owned buffer memory of a plurality of processors is inconsistent.For cache coherence,, think that then this accumulator system is consistent if an accumulator system satisfies following three conditions:
1) for processor P X is carried out write operation read request afterwards, if there is not other processor that x is carried out write operation after the write operation of P, what return so is the value that processor P is write.
2) after processor Q carried out write operation to x, processor P was carried out read request to x, if between these two operations enough intervals are arranged, and did not have other write operation between the two, and what return to P so is the value that Q writes.
3) write operation to same address is that serial is carried out, and that is to say that any two processors all have identical order to two write operations of same address at all processors.
From hardware point of view, multi-core CPU is introduced the consistance of cache coherent protocol maintenance memory system.In supporting the multi-core CPU of cache coherence, the shared data local cache of can moving into conducts interviews, thereby has effectively reduced the delay of visiting long-range shared data, and then reduces the bandwidth requirement to shared buffer memory.Simultaneously because local cache is that the shared data that reads has been done backup, so the warfare can reduce access delay and read shared data during these copies of conforming cache access the time.
According to the processing mode difference of write operation, the buffer consistency agreement can be divided into write invalidate (WriteInvalidate) and write renewal (Write Update) two classes.Realize that the key of buffer consistency agreement is to follow the tracks of the state of all shared data pieces.Present widely used two quasi-protocols that have, they adopt different Technical Follow-Up shared data.The one, the catalogue formula leaves the effective status of physical storage block in the three unities, is referred to as catalogue.The 2nd, the monitoring formula, each high-speed cache that contains data block copy in the physical storage also will keep the copy of this data block effective status, but concentrated area preservation state not.High-speed cache is placed on usually to be shared on the memory bus, and all director caches are monitored bus, determine whether they contain the copy of the data block of asking on the bus.
Summary of the invention
The objective of the invention is to be to propose under the polycaryon processor environment cache coherence method based on centralized directory.
The technical scheme that the present invention solves its technical matters employing is as follows:
Each processor is metadata cache and an Instructions Cache of at first searching processor core inside to the access process of memory hierarchy, check wherein whether there are the data that to visit, metadata cache sends request according to the state of corresponding data cache blocks to the catalog control device, and the catalog control device is according to the content control metadata cache of directory entry and the data communication of shared buffer memory.If the data that discovery will be visited still not in shared buffer memory, start the visit of shared buffer memory to main memory.No matter in which rank of memory hierarchy, found the unit of wanting addressing, after target access, all to be provided with and revise the conforming flag of service data so that in the processing procedure of back, make amendment or reading of data according to appropriate sign.
1) state of cache blocks is divided
In the catalogue consistency protocol, each data cache controller receives the input of two aspects: the message that read-write requests that processor sends and catalog control device are sent.As the response of these inputs, the state that director cache may upgrade this piece according to the current state and the state transition graph of respective caches piece, and also carry out some actions possibly.Such as, as the response of the read request that processor is sent, director cache produces a message of issuing the catalog control device possibly and obtains data, and returns to processor.
The state of metadata cache piece is divided into three kinds among the present invention, i.e. disarmed state, effective status and correction state.If certain metadata cache piece is in disarmed state, then native processor does not hit the read request or the write request of this piece.If certain metadata cache piece is in effective status, show that the processor that may also have other holds effective copy of this piece.If certain cache blocks is in the correction state, show that this piece is unique effective copy of corresponding shared buffer memory piece, native processor all hits at metadata cache the read request or the write request of this piece.
2) state of directory entry is divided
The present invention adopts full mapping catalogue, and each shared buffer memory piece has three kinds of directory states, i.e. disarmed state, effective status and correction state.If certain catalogue is in disarmed state, show not effective copy of this cache blocks of shared buffer memory.If certain catalogue is in effective status, show that the metadata cache of one or more processors has the copy of this cache blocks, and the data of shared buffer memory also are up-to-date (consistent with the copy in all metadata caches), as long as contain the copy of this piece in the metadata cache of processor, the corresponding position in sharer's set just puts 1.If certain catalogue is in proprietary state, show that the metadata cache that has only a processor has the copy of this cache blocks and this piece was carried out write operation, therefore the cache blocks in this copy and the shared buffer memory is inconsistent, is gathered by the sharer and indicates the processor that has this piece copy.
The present invention compares with background technology, and the beneficial effect that has is:
This method is applicable to embedded multi-core system processor, distributes write-back the advantage of two kinds of strategies to combine with writing, and has realized the buffer consistency based on centralized directory.Than monitoring protocols, directory protocol adopts the directed message transmission to reduce the pressure of broadcast mechanism to bandwidth, has avoided the interference to the normal operation of irrelevant processor, has extensibility preferably.
Description of drawings
Fig. 1 is the memory hierarchy RTL illustraton of model of multi-core CPU; It comprises four processor cores, and is interconnected by bus and shared buffer memory, and each processor core contains privately owned metadata cache and Instructions Cache, and carries out communication by catalog control device and shared buffer memory.
Fig. 2 is the state transition graph of metadata cache piece;
Fig. 3 is the directory states transition diagram;
Alphabetical meaning in the state transition graph is:
On behalf of catalog control device notification data buffer memory, CBS request msg is passed to shared buffer memory, and the state of requested data block is changed into effectively.
RDD represents the data of catalog control device notification data buffer memory reception shared buffer memory, and the cache blocks state is changed into effectively
RDM represents the data of catalog control device notification data buffer memory reception shared buffer memory, and the cache blocks state is changed into correction
On behalf of catalog control device notification data buffer memory, CBI data are write shared buffer memory and put this piece is invalid
It is invalid that on behalf of catalog control device notification data buffer memory, INV data place piece is put, and do not write back
STM represent catalog control device notification data buffer memory data place bulk state by effectively changing correction into
ADS represents receiveing the response that catalog control device notification data buffer memory sends
RDMS representative data buffer memory is sent out to the catalog control device and is read disappearance
WTHT representative data buffer memory is sent out to the catalog control device and is write hit message
WTMS representative data buffer memory is sent out to the catalog control device and is write the disappearance signal,
The response that AKD representative data buffer memory sends to the catalog control device
The RDS representative: catalog control device notice shared buffer memory receives the data of metadata cache
On behalf of catalog control device notice shared buffer memory, WTS send data to metadata cache
On behalf of catalog control device notice shared buffer memory, WTM write back data to main memory
On behalf of catalog control device notice shared buffer memory, RDM read in the data of main memory
On behalf of shared buffer memory, AKS beam back response to the catalog control device
On behalf of processor, RDP send reading request to metadata cache
RDPR representative data buffer memory is beamed back the concurrent response of processor to data
On behalf of processor, WTP send write operation requests to metadata cache
WTPR representative data buffer memory is sent out write operation requests to processor and is responded
On behalf of shared buffer memory, RDSM send out the read operation request to main memory
On behalf of shared buffer memory, WTSM send out write operation requests to main memory
On behalf of main memory, AKM beam back response to shared buffer memory
Fig. 4 is an overview flow chart.
Embodiment
The specific embodiment of the present invention is:
1) sends reading request RDP to metadata cache when processor, if hit then metadata cache data are beamed back concurrent responses of processor RDPR and modification LRU position, otherwise read miss request RDMS to the transmission of catalog control device, the catalog control device is received the catalogue of reading to search after the miss request data block correspondence, takes following operation according to different conditions:
If I. the directory states of access block correspondence is effectively in the catalog control device, the catalog control device sends the WTS request to shared buffer memory, receives that responding the back sends out the RDD request to metadata cache, and the processor that request is read is added sharer's set.
If II. the directory states of access block correspondence is correction in the catalog control device, then the processor of catalog control device in sharer's set sends the CBS request, directory entry changes busy condition over to, after receiving the processor response of sharer in gathering, send the RDS request to shared buffer memory, receive that the processor that request is read in the response back adds sharer's set, the directory states that access block is set simultaneously is effectively.
If III. the directory states of access block correspondence is invalid in the catalog control device, the catalog control device will be checked the directory states for the treatment of replace block in same group of the access block.If the correction state, the catalog control device is sent out the CBI request to the metadata cache for the treatment of the replace block place, receives that the response back is sent out the RDS request and put this piece modification position to shared buffer memory is 1, and it is invalid simultaneously the directory states of this piece to be changed into.If effective status, the catalog control device is sent out the INV order to the processor for the treatment of the replace block place, and it is invalid simultaneously the directory states of this piece to be changed into.If disarmed state, the state of position is revised in the inspection of catalog control device, as be 1 and send out WTM order to shared buffer memory, receive that responding the back resets revising the position, sending out the RDM order to shared buffer memory notifies it to read in access block from main memory, the sign of access block is write replace block, finish and replace and the directory states of access block is changed into effectively.
2) when processor when metadata cache sends write operation requests WTP, metadata cache is checked the state of data place cache blocks.If revise then and send out WTPR response, the data that receiving processor is write to processor.If effectively, metadata cache is sent out WTHT message to the catalog control device, the catalog control device is checked sharer's set of this piece, then change correction into as if having only the visitor to share this piece, order and it is removed from the sharer gathers if there is this cache blocks of a plurality of processors sharing then to send out INV to non-visitor to its WTM order and the directory states of this piece.If invalid, metadata cache is sent out the WTMS signal to the catalog control device, and the catalog control device is searched the directory states with data block, makes following different operating:
If I. the directory states of access block correspondence is effectively in the catalog control device, the non-visitor of catalog control device in sharer's set sends out the INV signal and it removed from sharer's set, sends out the WTS order to shared buffer memory simultaneously.When sharer set for complete 0 the time, the catalog control device is sent out the WTS order to shared buffer memory, receives that responding the back sends out the RDM order to metadata cache, the visitor is added in sharer's set and the directory states of this piece to change correction into simultaneously.
If II. the directory states of access block correspondence is to revise in the catalog control device, if current accessed person is at this piece of visit, then the catalog control device is failure to actuate, otherwise the catalog control device is sent out the CBI order to the owner of this cache blocks, send out the RDS order to shared buffer memory, receive that responding the back gathers the sharer clear 0, puts this piece to revise the position be 1 and the directory states of this piece changed into effectively.
If III. the directory states of access block correspondence is invalid in the catalog control device, the catalog control device will be checked the directory states for the treatment of replace block in same group of the access block.If the correction state, the catalog control device is sent out the CBI request to the metadata cache for the treatment of the replace block place, receives that the response back is sent out the RDS request and put this piece modification position to shared buffer memory is 1, and it is invalid simultaneously the directory states of this piece to be changed into.If effective status, the catalog control device is sent out the INV order to the processor for the treatment of the replace block place, and it is invalid simultaneously the directory states of this piece to be changed into.If disarmed state, the state of position is revised in the inspection of catalog control device, as be 1 and send out WTM order to shared buffer memory, receive that responding the back resets revising the position, sending out the RDM order to shared buffer memory notifies it to read in access block from main memory, the sign of access block is write replace block, finish and replace and the directory states of access block is changed into effectively.
Claims (1)
1. method for embedded multi-core buffer consistency based on centralized directory is characterized in that:
1) state of cache blocks is divided
In the catalogue consistency protocol, each data cache controller receives the input of two aspects: the message that read-write requests that processor sends and catalog control device are sent.As the response of these inputs, the state that director cache may upgrade this piece according to the current state and the state transition graph of respective caches piece, and also carry out some actions possibly.Such as, as the response of the read request that processor is sent, director cache produces a message of issuing the catalog control device possibly and obtains data, and returns to processor.
The state of metadata cache piece is divided into three kinds among the present invention, i.e. disarmed state, effective status and correction state.If certain metadata cache piece is in disarmed state, then native processor does not hit the read request or the write request of this piece.If certain metadata cache piece is in effective status, show that the processor that may also have other holds effective copy of this piece.If certain cache blocks is in the correction state, show that this piece is unique effective copy of corresponding shared buffer memory piece, native processor all hits at metadata cache the read request or the write request of this piece.
2) state of directory entry is divided
The present invention adopts full mapping catalogue, and each shared buffer memory piece has three kinds of directory states, i.e. disarmed state, effective status and correction state.If certain catalogue is in disarmed state, show not effective copy of this cache blocks of shared buffer memory.If certain catalogue is in effective status, show that the metadata cache of one or more processors has the copy of this cache blocks, and the data of shared buffer memory also are up-to-date (consistent with the copy in all metadata caches), as long as contain the copy of this piece in the metadata cache of processor, the corresponding position in sharer's set just puts 1.If certain catalogue is in proprietary state, show that the metadata cache that has only a processor has the copy of this cache blocks and this piece was carried out write operation, therefore the cache blocks in this copy and the shared buffer memory is inconsistent, is gathered by the sharer and indicates the processor that has this piece copy.
The cache blocks of processor core visit data buffer memory causes cache blocks and the variation of directory entry between three states, and the incident that triggers state transformation is divided into read operation and write operation:
1) sends reading request RDP to metadata cache when processor, if hit then metadata cache data are beamed back concurrent responses of processor RDPR and modification LRU position, otherwise read miss request RDMS to the transmission of catalog control device, the catalog control device is received the catalogue of reading to search after the miss request data block correspondence, takes following operation according to different conditions:
If I. the directory states of access block correspondence is effectively in the catalog control device, the catalog control device sends the WTS request to shared buffer memory, receives that responding the back sends out the RDD request to metadata cache, and the processor that request is read is added sharer's set.
If II. the directory states of access block correspondence is correction in the catalog control device, then the processor of catalog control device in sharer's set sends the CBS request, directory entry changes busy condition over to, after receiving the processor response of sharer in gathering, send the RDS request to shared buffer memory, receive that the processor that request is read in the response back adds sharer's set, the directory states that access block is set simultaneously is effectively.
If III. the directory states of access block correspondence is invalid in the catalog control device, the catalog control device will be checked the directory states for the treatment of replace block in same group of the access block.
2) when processor when metadata cache sends write operation requests WTP, metadata cache is checked the state of data place cache blocks.If revise then and send out WTPR response, the data that receiving processor is write to processor.If effectively, metadata cache is sent out WTHT message to the catalog control device, the catalog control device is checked sharer's set of this piece, then change correction into as if having only the visitor to share this piece, order and it is removed from the sharer gathers if there is this cache blocks of a plurality of processors sharing then to send out INV to non-visitor to its WTM order and the directory states of this piece.If invalid, metadata cache is sent out the WTMS signal to the catalog control device, and the catalog control device is searched the directory states with data block, makes following different operating:
If I. the directory states of access block correspondence is effectively in the catalog control device, the non-visitor of catalog control device in sharer's set sends out the INV signal and it removed from sharer's set, sends out the WTS order to shared buffer memory simultaneously.When sharer set for complete 0 the time, the catalog control device is sent out the WTS order to shared buffer memory, receives that responding the back sends out the RDM order to metadata cache, the visitor is added in sharer's set and the directory states of this piece to change correction into simultaneously.
If II. the directory states of access block correspondence is to revise in the catalog control device, if current accessed person is at this piece of visit, then the catalog control device is failure to actuate, otherwise the catalog control device is sent out the CBI order to the owner of this cache blocks, send out the RDS order to shared buffer memory, receive that responding the back gathers the sharer clear 0, puts this piece to revise the position be 1 and the directory states of this piece changed into effectively.
If III. the directory states of access block correspondence is invalid in the catalog control device, the catalog control device will be checked the directory states for the treatment of replace block in same group of the access block.If the correction state, the catalog control device is sent out the CBI request to the metadata cache for the treatment of the replace block place, receives that the response back is sent out the RDS request and put this piece modification position to shared buffer memory is 1, and it is invalid simultaneously the directory states of this piece to be changed into.If effective status, the catalog control device is sent out the INV order to the processor for the treatment of the replace block place, and it is invalid simultaneously the directory states of this piece to be changed into.If disarmed state, the state of position is revised in the inspection of catalog control device, as be 1 and send out WTM order to shared buffer memory, receive that responding the back resets revising the position, sending out the RDM order to shared buffer memory notifies it to read in access block from main memory, the sign of access block is write replace block, finish and replace and the directory states of access block is changed into effectively.
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