WO2023133830A1

WO2023133830A1 - Shared storage system and apparatus, and method for invalidating cache data

Info

Publication number: WO2023133830A1
Application number: PCT/CN2022/072102
Authority: WO
Inventors: 何涛; 于东浩; 李瑛�
Original assignee: 华为技术有限公司
Priority date: 2022-01-14
Filing date: 2022-01-14
Publication date: 2023-07-20
Also published as: CN117529899A

Abstract

Embodiments of the present application provide a shared storage system and a method for invalidating cache data. The shared storage system comprises a memory manager, a plurality of processors, and a shared memory; a first processor in the plurality of processors is used for sending a request to the memory manager, the request indicating rewriting data in a first address, and the first address being an address in the shared memory; the memory manager sends a first signal to a second processor in the plurality of processors on the basis of the request, the first signal indicating invalidating first data stored in the second processor, the first data being a copy of data in a first address space in the shared memory, and the first address being located in the first address space; the second processor invalidates the first data on the basis of the first signal. According to the shared storage system and the method for invalidating cache data provided by the embodiments of the present application, the performance of the shared storage system can be improved.

Description

Shared storage system, device and method for invalidating cached data

technical field

The embodiments of the present application relate to the field of computer security, and in particular to a shared storage system, device and method for invalidating cached data.

Background technique

In shared memory technology, memory space is shared between multiple processors. That is to say, any processor connected to the shared memory system can issue a request to access any address. Since the multiple processors share the memory space, multiple processors that issue a request to access the same address will get a copy of the same data. However, after one of the processors rewrites the copy, the copy stored by other processors in the address is different from the rewritten copy, that is, there is a cache coherence problem.

In order to ensure the cache consistency between multiple copies and original data in the same address, in traditional technology, when one of the processors writes to a certain address, the memory manager responsible for maintaining the shared address space is usually based on The snoopy protocol sends information to other processors that have saved the data in the address to notify other processors that the data in the address is invalid. However, as the processor speed increases, the processor processes more and more data in a clock cycle, and copies of the same large amount of data (that is, data in multiple addresses) are cached in multiple processors. In the snoopy protocol, when one of the processors rewrites the large amount of data, the memory manager needs to send multiple addresses corresponding to the large amount of data to other processors respectively. Assuming that the large amount of data is located in ten addresses, the memory manager needs to send the ten addresses to other processors one by one, seriously occupying the bandwidth of the communication network in the shared memory system. In addition, if multiple addresses are sent to other processors one by one, it may take multiple clock cycles for other processors to obtain information indicating that the stored copy is invalid, that is, there is a time delay problem. To sum up, in a shared storage system, when multiple processors store copies of the same large amount of data, when one of the processors rewrites the copy, how to effectively invalidate the copies saved by other processors to improve The performance of the shared storage system becomes a problem that needs to be solved.

Contents of the invention

The shared storage system, device and method for invalidating cached data provided by the present application can efficiently invalidate copies cached by other processors when a certain processor rewrites data in a certain address. In order to achieve the above purpose, the present application adopts the following technical solutions.

In the first aspect, the embodiment of the present application provides a shared storage system, the shared storage system includes: a memory manager, a plurality of processors, and a shared memory; the first processor in the plurality of processors is configured to provide The memory manager sends a request, and the request indicates to rewrite the data in the first address, and the first address is an address in the shared memory; the memory manager, based on the request, sends to the plurality of processes The second processor in the memory device sends a first signal, the first signal indicates that the first data stored by the second processor is invalid, and the first data is the data in the first address space in the shared memory a copy, the first address is located in the first address space; the second processor, based on the first signal, invalidates the first data.

The memory manager can be a dedicated processor, or it can be integrated with the core in the central processing unit. The memory manager may be, for example, the memory manager 21 , the memory manager 22 , the memory manager 23 or the memory manager 24 shown in FIG. 1 . The multiple processors are, for example, processor 01 , processor 02 , processor 03 , or processor 04 shown in FIG. 1 . The shared memory is, for example, the memory 11 , the memory 12 , the memory 13 or the memory 14 shown in FIG. 1 . The memory manager is used to manage the memory of its said coupling. For example, in FIG. 1 , the memory manager 21 manages the memory 11 , the memory manager 22 manages the memory 12 , the memory manager 23 manages the memory 13 , and the memory manager 24 manages the memory 14 . The management here can refer to which processors save the data in each address space, and before one of the processors rewrites the data in a certain address space, invalidate the data in the address space saved in other processors .

There may be multiple first addresses, and the multiple first addresses are all located in the first address space. The first address space may be pre-divided by the memory manager, and may also be called a declared space area. In an optional implementation manner, the size of the first address space may be dynamically adjusted. For example, the memory manager may first recover all the address spaces allocated to each processor, readjust the size of the address space of the shared memory, and broadcast the adjusted size of the address space and the identifier corresponding to the address space to each processor.

The first signal may include various implementations. In the first possible implementation manner, the first signal may include the address range of the first address space; in the second possible implementation manner, the first address space may map a preset identifier, and the first signal may include The default identification can be included.

The first address space includes a plurality of addresses. In the traditional technology, if the memory manager used to manage the shared memory needs to invalidate the data copy in the first address space stored in the first processor, it needs to send multiple signals to the first processor, and one signal indicates invalid data at one address; this severely consumes the bandwidth of the interconnection network. The memory manager provided by the embodiment of the present application can invalidate the copy of data in the first address space stored in the first processor by sending the first signal to the first processor. It increases the network bandwidth and improves bandwidth utilization, thereby improving the performance of the shared storage system.

Based on the first aspect, in a possible implementation manner, the second processor is specifically configured to: decompose the first address space into multiple addresses based on the first signal and the size of a preset data segment range, to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment; and invalidate the multiple data segments.

Optionally, the second processor may invalidate multiple data segments at the same time, or invalidate the multiple data segments in a time-sharing manner.

In a traditional storage protocol (such as the snoopy protocol), data is stored in the cache in the form of a data segment, such as a cache line. The processor performs data operations in units of data segments, such as modifying the state of data, storing data, or reading data. A data segment usually corresponds to an address range. The first address space includes multiple address ranges, that is, multiple data segments are stored. After the second processor receives the information indicating to invalidate the copy of data in the first address space, by decomposing the first address space into a plurality of address ranges to obtain a plurality of data segments, and then invalidating the plurality of data segments, such that , a traditional storage protocol (such as the snoopy protocol) can be used to invalidate multiple data segments, and then invalidate the first address space, without spending additional overhead on the second processor used to perform invalidation of the data in the first address space Hardware improvement is beneficial to save design cost.

Based on the first aspect, in a possible implementation manner, the second processor is specifically configured to: when the state of some data segments among the plurality of data segments is one of a shared state and an exclusive state, Modifying the state of the at least some of the data segments to an invalid state.

Based on the first aspect, in a possible implementation manner, the second processor includes a cache manager and an invalidation manager; the invalidation manager generates multiple invalidation signals based on the multiple address ranges, one The address range corresponds to one invalidation signal; and transmitting the plurality of invalidation signals to the buffer manager in time division; the buffer manager invalidates the plurality of data segments based on the plurality of invalidation signals.

Both the cache manager and the invalidation manager can be implemented by hardware circuits. Operations on the cached data in the second processor (such as obtaining data from the memory for caching, writing data into the memory, and modifying the state of the cached data) are all implemented by the cache manager. The cache manager operates on data in units of data segments. In the traditional technology, no invalidation manager is set, and the memory manager provides multiple invalidation signals corresponding to multiple address ranges to the cache manager in time-sharing, which seriously occupies bandwidth; in the embodiment of the present application, by setting the invalidation manager, The memory manager is replaced by the invalidation manager, and multiple invalidation signals are generated and provided to the cache manager. Since the invalidation manager and the cache manager are set in the same processor, compared with the prior art, it is not necessary to occupy the off-chip processor The bandwidth of the interconnection network, and has an efficient transmission rate. In addition, for the cache manager, there is no need to make any changes to the structure of the cache manager, and it can still receive signals according to the traditional storage protocol and operate on data in units of data segments, saving design costs.

Based on the first aspect, in a possible implementation manner, the invalidation manager is further configured to decompose the first address space into multiple address ranges based on the first signal and a size of a preset data segment.

Based on the first aspect, in a possible implementation manner, the cache manager is further configured to send multiple responses to the multiple signals to the invalidation manager, where one response corresponds to one data segment, The first response in the plurality of responses indicates that the first data segment in the plurality of data segments has not been rewritten; the invalidation manager is further configured to transmit to the memory manager based on the plurality of responses a second signal indicating completion of invalidation of the first data.

In the traditional technology, no invalidation manager is provided, and the cache manager needs to transmit multiple response signals to the memory manager, occupying the bandwidth of the communication network. In the embodiment of the present application, when the invalidation manager receives multiple responses, and the multiple responses indicate that the corresponding data segment has not been rewritten, it transmits a signal to the memory manager indicating that the invalidation of the first data is completed, that is, the invalidation management Only one signal needs to be transmitted from the controller to the memory manager. Compared with the transmission of multiple response signals in the prior art, the bandwidth of the communication network can be reduced and the utilization rate of the bandwidth can be improved.

Based on the first aspect, in a possible implementation manner, the second response in the multiple responses includes the second data segment in the multiple data segments; the invalidation manager is further configured to convert the The second data segment is written back to the corresponding address range in the shared memory.

In the embodiment of the present application, the data in the second data segment is rewritten, and the cache manager needs to write the rewritten data back to the memory. The cache manager transmits the second response carrying the second data segment to the invalidation manager, so that the invalidation manager writes the second data segment back to the memory.

Based on the first aspect, in a possible implementation manner, the first invalid signal among the plurality of invalid signals indicates that the first data segment is invalid; and the buffer manager is specifically configured to: upon receiving the Before the first invalid signal, write the first data segment back to the shared memory; in response to the third signal sent by the memory manager, the third signal indicates that the storage of the first data segment is complete, and write the first data segment to the shared memory. The invalidation manager sends the first response.

Based on the first aspect, in a possible implementation manner, the memory manager is further configured to: send a fourth signal to the first processor, where the fourth signal indicates that the first processor is allowed to rewrite the the data in the first address.

Based on the first aspect, in a possible implementation manner, the third processor among the multiple processors is configured to send a request to the memory manager, where the request indicates to rewrite the data in the second address, The second address is an address in the shared memory; the memory manager, based on the request, sends a fifth signal to the cache manager, and the fifth signal indicates invalidation of the memory stored by the cache manager the second data in the second address, the second data is a copy of the data in the second address; the cache controller, based on the fifth signal, sends a second response to the memory manager, the second The response indicates that the second data is modified or not modified.

In this implementation, if the second address is outside the first address range, or the amount of data corresponding to the second address is exactly one data segment, the memory manager can directly transmit a signal indicating that the data copy in the second address is invalid To the cache controller, there is no need to decompose the address range through the invalidation manager at this time, which can improve the signal transmission speed and the working efficiency of the shared memory system.

In a second aspect, an embodiment of the present application provides a device, the device includes a memory manager, and the memory manager is configured to: receive a first request from a first processor, and the first request indicates to rewrite the data in the first address , the first address is an address in a shared memory, the shared memory is managed by the memory manager; based on the first request, a first signal is sent to the second processor, the first signal indicates invalid The first data saved by the second processor, the first data is a copy of the data in the first address space in the shared memory, the first address is located in the first address space, wherein the A shared memory is managed by the memory manager, and an address space in the shared memory is allowed to be accessed by the first processor and the second processor.

The device provided in the embodiment of the present application may only be provided with a memory manager dedicated to managing shared memory. Optionally, the device provided in this embodiment of the present application may be a processor, and the processor may include, for example, a processor core in addition to a memory manager.

Based on the second aspect, in a possible implementation manner, the memory manager is further configured to: receive a second signal from the second processor, the second signal indicating completion of invalidation of the first data ; based on the second signal, sending a third signal to the first processor, the third signal indicating that the first processor is allowed to rewrite the data in the first address.

Based on the second aspect, in a possible implementation manner, the memory manager is further configured to: monitor that the second processor stores a first data segment in the shared memory, and the first data segment is the A piece of data in the first data; in response to the completion of storage of the first data section, sending a fourth signal to the second processor, where the fourth signal indicates that the storage of the first data section is complete.

Based on the second aspect, in a possible implementation manner, the memory manager is further configured to: receive a second request from a third processor, where the second request indicates to rewrite the data in the second address, and the first The second address is an address in the shared memory; based on the second request, a fifth signal is sent to the second processor, the fifth signal indicates that the second data is invalid, and the second data is the second data. A copy of the data at the second address mentioned above.

In a third aspect, an embodiment of the present application provides a device, the device includes a processor, the processor is configured to: receive a first signal from a memory manager, the first signal is used to indicate that the saved first data is invalid, The first data is a copy of data in a first address space in a shared memory, the first address is located in the first address space, and the shared memory is managed by the memory manager; based on the first signal , invalidate the first data.

Based on the third aspect, in a possible implementation manner, the processor is specifically configured to: decompose the first address space into multiple address ranges based on the first signal and the size of a preset data segment, Obtaining multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment; invalidating the multiple data segments.

Based on the third aspect, in a possible implementation manner, the processor is specifically configured to: when the state of at least some of the data segments in the multiple data segments is one of the shared state or the exclusive state, set The state of the at least some data segments is modified to an invalid state.

Based on the third aspect, in a possible implementation manner, the processor includes a cache manager and an invalidation manager; the invalidation manager generates multiple invalidation signals based on the multiple address ranges, one address range corresponding to one invalidation signal; and transmitting the plurality of invalidation signals to the buffer manager in time division; the buffer manager invalidates the plurality of data segments based on the plurality of invalidation signals.

Based on the third aspect, in a possible implementation manner, the cache manager is further configured to send multiple responses to the multiple invalidation signals to the invalidation manager, where one response corresponds to one data segment , the first response in the plurality of responses indicates that the first data segment in the plurality of data segments has not been rewritten; the invalid manager is further configured to send the memory manager to the memory manager based on the plurality of responses Transmitting a second signal indicating completion of invalidation of the first data.

Based on the third aspect, in a possible implementation manner, the second response among the multiple responses carries the second data segment among the multiple data segments, and the status of the second data segment is Rewrite state; the invalidation manager is further configured to write the second data segment back into the corresponding address range in the shared memory when the state of the second data segment is in the rewritten state.

Based on the third aspect, in a possible implementation manner, the first invalid signal among the plurality of invalid signals indicates that the first data segment is invalid; and the cache manager is specifically configured to: upon receiving the Before the first invalidation signal, write the first data segment back to the shared memory; in response to the fourth signal sent by the memory manager, send the first response to the invalidation manager, and the fourth A signal indicates that the storage of the first data segment is complete.

Based on the third aspect, in a possible implementation manner, the cache controller is further configured to: receive a fifth signal from the memory manager, the fifth signal indicating invalidation of the first Two data, the second data is a copy of the data in the second address; in response to the fifth signal, sending a third response to the memory manager, the third response indicates that the second data is modified or unmodified.

In a fourth aspect, an embodiment of the present application provides a method for invalidating cached data, the method for invalidating cached data includes: receiving a first request from a first processor, the first request indicating rewriting the first address in data, the first address is an address in the shared memory; based on the first request, a first signal is sent to the second processor, and the first signal indicates invalidation of the first stored by the second processor data, the first data is a copy of data in a first address space in the shared memory, and the first address is located in the first address space.

Based on the fourth aspect, in a possible implementation manner, the method further includes: receiving a second signal from the second processor, the second signal indicating completion of invalidation of the first data; the second signal, and send a third signal to the first processor, where the third signal indicates that the first processor is allowed to rewrite the data in the first address.

In the fifth aspect, the embodiment of the present application provides a method for invalidating cached data, the method for invalidating cached data includes: receiving a first signal from the memory manager, the first signal is used to indicate invalidation of the stored first data, where the first data is a copy of data in a first address space in the shared memory, and the first address is located in the first address space; based on the first signal, the first data is invalidated.

Based on the fifth aspect, in a possible implementation manner, the invalidating the first data based on the first signal includes: based on the first signal and the size of a preset data segment, converting the first data to Decomposing an address space into multiple address ranges to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment; invalidating the multiple data segments.

Based on the fifth aspect, in a possible implementation manner, the invalidating the plurality of data segments includes: when the state of at least some of the data segments in the plurality of data segments is one of a shared state or an exclusive state , modify the state of the at least some data segments to an invalid state.

Based on the fifth aspect, in a possible implementation manner, the method further includes: when the state of each data segment in the plurality of data segments is an invalid state, transmitting a second signal to the memory manager , the second signal indicates completion of invalidation of the first data.

Based on the fifth aspect, in a possible implementation manner, before transmitting the second signal to the memory manager, the method further includes: when the state of the first data segment among the plurality of data segments is When the state is rewritten, write the second data segment back into the corresponding address range in the shared memory.

It should be understood that the technical solutions of the second to fifth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects obtained by the various aspects and the corresponding feasible implementation modes are similar, so details are not repeated here.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application , for those skilled in the art, other drawings can also be obtained according to these drawings without paying creative labor.

FIG. 1 is a schematic diagram of a hardware structure of a shared storage system provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of the mapping relationship between the memory and the global address space provided by the embodiment of the present application;

FIG. 3 is a schematic diagram of multiple address ranges divided by the address space of the memory 11 provided by the embodiment of the present application;

FIG. 4 is a flow chart of the interaction between components in the shared storage system provided by the embodiment of the present application;

Fig. 5 is another schematic diagram of the hardware structure of the shared storage system provided by the embodiment of the present application;

FIG. 6 is a flowchart of the interaction between components in the shared storage system shown in FIG. 5 provided by the embodiment of the present application;

Fig. 7 is another flow chart of interaction between components in the shared storage system shown in Fig. 5 provided by the embodiment of the present application;

Fig. 8 is another flow chart of interaction between components in the shared storage system shown in Fig. 5 provided by the embodiment of the present application;

FIG. 9 is a flowchart of a method for invalidating cached data provided by an embodiment of the present application;

FIG. 10 is another flow chart of the method for invalidating cached data provided by the embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

"First", "second" and similar words mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a" or "one" do not denote a limitation in number, but indicate that there is at least one. "Connection" and similar words are not limited to physical or mechanical connection, but may include electrical connection, no matter it is direct or indirect, which is equivalent to communication in a broad sense.

In the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more. For example, multiple processors refers to two or more processors.

The shared storage system 100 described in the embodiment of the present application may be a symmetric multiprocessor (symmetrical mulit-processing, SMP) system. The shared storage system 100 includes multiple processors, for example, 2, 3, etc., which is not specifically limited in this embodiment of the present application. The plurality of processors may be a central processing unit (CPU, central processing unit) or a dedicated processor (such as an image signal processor, an artificial intelligence processor or a neural network processor, etc.), and the embodiment of the present application does not change the form of the processor. Be specific. Components (such as processors and memory) connected to the shared storage system 100 may communicate through an interconnection network, and the interconnection network may include, but is not limited to, one of the following: a single bus, multiple buses, or a crossbar. In addition, the shared storage system 100 also includes a memory, such as but not limited to SDRAM, DDR, and the like. The memory can be independently set and managed by a dedicated memory manager, or it can be coupled to one of the processors and managed by the processor, or it can be divided into multiple parts and distributed and coupled to multiple processors, each part is controlled by it. Coupled processor management. The memory forms a globally unified address space, which is shared by all processors in the shared storage system 100 , and each processor can initiate a request to access any address space. The access to any address space mentioned here refers to reading instructions or data from the accessed address space, or writing data to the accessed address space. Processors that issue requests to read the same address space will get the same data. The above-mentioned memory management refers to recording which processors store data in each address space, and before one of the processors rewrites data in a certain address space, invalidates the data in the address space stored in other processors. In this embodiment of the present application, the shared storage system 100 includes four processors as an example, and each processor is mounted with a memory case as an example. With reference to FIG. 1 , the shared storage system 100 provided by the embodiment of the present application is described in detail.

Please refer to FIG. 1 , which is a schematic diagram of a hardware structure of a shared storage system 100 provided in an embodiment of the present application. In FIG. 1 , a shared storage system 100 includes four processors, namely a processor 01 , a processor 02 , a processor 03 and a processor 04 . The four processors are connected through an interconnection network. It should be noted that the processor 01 to the processor 04 may be respectively integrated into one or more chips. For example, processor 01 to processor 04 may be integrated into different chips; for another example, processor 01 to processor 04 may also be integrated into one chip. In the embodiment of the present application, the processor 01 to the processor 04 are respectively independent processors and are respectively integrated into different chips for description, but this is not used to limit the solution.

Each processor has a memory attached to it. That is to say, the processor 01 is coupled to the memory 11 , the processor 02 is coupled to the memory 12 , the processor 03 is coupled to the memory 13 , and the processor 04 is coupled to the memory 14 . Each memory can also optionally be integrated into the same chip as the processor coupled to it. The memory 11 - the memory 14 form the global address space of the shared memory system 100, which is shared by the processors 01 - 04. Memory 11 to memory 14 are respectively mapped to a certain block in the global address space. As shown in FIG. 2 , FIG. 2 schematically shows a mapping relationship between each memory and the global address space. In Figure 2, the storage space of memory 11 is mapped to 0x0000~0x4000 in the global address space, the storage space of memory 12 is mapped to 0x4001~0x8000 in the global address space, and the storage space of memory 13 is mapped to the global address space 0x8000-0x1201 in the memory, the storage space of memory 14 is mapped to 0x1200-0x1600 in the global address space.

Each processor is provided with one or more processor cores (cores), and the processor cores are used to obtain instructions and data from the global address space to complete various tasks that need to be processed. As shown schematically in Figure 1, one core is set in processor 01, one core c2 is set in processor 02, one core c3 is set in processor 03, and one core c4 is set in processor 04 a kernel.

Each processor is also integrated with a memory manager, which can also be called a local agent (home agent), wherein the processor 01 is integrated with a memory manager 21, and the processor 02 is integrated with a memory manager 22, A memory manager 23 is integrated in the processor 03 , and a memory manager 24 is integrated in the processor 04 . Each memory manager can be implemented by a hardware circuit. Each memory manager is used to manage the memory to which it is coupled. Taking the memory manager 21 as an example, the memory manager 21 is used to record which processors the data in the address space 0x0000～0x4000 shown in Figure 2 are saved by, and which processors in the processor 02～processor 04 rewrite a certain Before the data in an address space, invalidate the data in the address space held by other processors. Assume that processor 02 and processor 03 both store data at address 0x3800. The processor 02 needs to rewrite the data in the address 0x3800. Before the processor 02 rewrites the data in the address 0x3800, the processor 01 transmits to the processor 03 a signal for indicating invalid data in the address 0x3800. Therefore, cache consistency in the shared storage system 100 can be guaranteed. It should be noted that each memory manager can communicate with other processors (or components set in the processor, such as processor core, data invalidation manager and cache manager described below) through an interconnection network Direct communication, directly communicates with components in the internal processor (such as processor core, cache manager and data invalidation manager, etc.) through the internal bus.

Further, in the embodiment of the present application, each memory manager may further divide the space area it manages into multiple address spaces in advance, and the address space may be divided into page (page) granularity, for example. At least some of the address spaces in the plurality of address spaces are declarative address spaces. That is to say, when the processor needs to read data in a certain address (or multiple addresses) in the declared address space, the memory manager provides all the data in the address space corresponding to the declared address space to the processing In addition, when a processor needs to rewrite the data in a certain address (or multiple addresses) in the declared address space, if other processors have a copy of the data in the declared address space, other processors need to copy the data in the declared address space. All the saved data in the declaration address space are invalid. Taking the address space mapped by the memory 11 shown in FIG. 2 as an example, the multiple address spaces divided by the address space will be described in conjunction with FIG. 3 . The address space 0x0000˜0x4000 mapped by the memory 11 shown in FIG. 2 can be further divided into four address spaces. The four address spaces may be, for example, address spaces 0x0000-0x1000, address spaces 0x1001-0x2000, address spaces 0x2001-0x3000, and address spaces 0x3001-0x4000. Among them, the address space 0x0000-0x1000, the address space 0x1001-0x2000 and the address space 0x2001-0x3000 are declared address spaces, respectively recorded as address space p1, address space p2, and address space p3. Assuming that the processor 02 sends a signal to the memory manager 21 to read the data in addresses 0x0000-0x0800, and the processor 03 sends a signal to the memory manager 21 to read the data in the address 0x3000-0x0900, then the memory manager 21 will All data in address space p1 are provided to processor 02 and processor 03 respectively. Based on the four address spaces divided by the memory 11 shown in Figure 3, taking the processor 02 further sending a request to the memory manager 21 to rewrite the data in addresses 0x0000-0x0800 as an example, combined with the interaction process shown in Figure 4, the memory The manner in which the manager 21 invalidates the copy stored in the processor 03 will be described.

Step 401 , the processor 02 sends a request q1 to the memory manager 21 . The request q1 is used to request to rewrite the data in addresses 0x0000˜0x0800.

Step 402, the memory manager 21 sends a signal s1 to the processor 03 based on the request q1. Specifically, after receiving the request q1, the memory manager 21 first finds out that addresses 0x0000-0x0800 are located in the address space p1. Then, the memory manager 21 can query and find out that the processor 03 has saved a copy of the data in the address space p1. Finally, the memory manager 21 sends a signal s1 to the processor 03 indicating that the processor 03 invalidates the copy of the data in the address space p1. In an optional implementation manner, the memory manager 21 may directly send the address range 0x0000-0x1000 corresponding to the address space to the processor 03 . In another possible implementation, each declared address space can be mapped to a preset identifier, and each processor can store the mapping relationship between the declared address space and the preset identifier, such as address space p1, address The preset identifiers corresponding to the space p2 and the address space p3 are page1, page2 and page3 respectively; the memory manager 21 may send the preset identifier page1 corresponding to the address space p1 to the processor 03.

In step 403, the processor 03 invalidates the saved copy of the data in the address space p1 based on the signal s1. Generally, the copy of the data in the address space p1 saved by the processor 03 may include multiple data segments, and one data segment may be, for example, a cache line (cache line). Each data segment is provided with status information indicating the status of the data segment, such status information includes but not limited to the following items: modified (modity), unique (exclusive), shared (shared) and invalid (Invalid). The copy of the data in the address space p1 that is invalidated as mentioned above may mean that when the status information of a certain data segment is one of modified, unique and shared, the processor 03 modifies the status information to be invalid .

Based on the structure of the shared storage system 100 shown in FIG. 1 , in the traditional shared storage system 100 , the processors communicate with each other based on the snoopy protocol. In the snoopy protocol, the processor usually operates data at the granularity of data segments (eg, reads data, writes data, or modifies identification bits corresponding to data). That is to say, assume that the processor 03 stores data in addresses 0x3000-0x0800, and the granularity of the data that can be manipulated each time is 0x0100. When the processor 02 writes the data in the address 0x0000～0x0800, the memory manager 21 decomposes the address 0x0000～0x0800 with 0x0100 as the granularity to obtain eight address ranges based on the snoopy protocol. . Then, the memory manager 21 transmits to the processor 03 a signal indicating that data in an address range is invalid each time, that is, the memory manager 21 needs to transmit signals to the processor 03 eight times, seriously occupying the bandwidth of the interconnection network. In addition, if the eight address ranges are sent to the processor 03 one by one, the processor 03 may obtain a signal indicating that the data in a certain address range is invalid after several clock cycles, and there is a time delay problem. In the embodiment of the present application, by setting the declaration address space in advance, when a large amount of data in the declaration address space needs to be invalidated, the memory manager used to manage the range of the declaration space can set the The copy signal is provided to other processors that store the copy. Compared with the memory manager that needs to send multiple signals, the embodiment of the present application can send a signal once to invalidate a large amount of data, releasing the bandwidth of the interconnection network. Helps improve bandwidth utilization.

Based on the structure of the shared storage system 100 shown in FIG. 1 and the interaction process 400 shown in FIG. 4 , please continue to refer to FIG. 5 , which is a more detailed structural diagram of the shared storage system 100 provided by the embodiment of the present application. On the basis of the shared memory system 100 shown in FIG. 1 , each processor in the shared memory system 100 shown in FIG. 5 further includes a cache manager. A cache manager can also be called a cache agent. A cache and a cache controller are provided in the cache manager. The cache can be based on the control of the cache controller, from the global address space in the shared storage system 100, obtain instructions and data required for the operation of the processor core for storage; and write data to any address space in the global address space, the The data is dirty (dirty) data that is pre-stored in the cache and generated by the operation of the processor. That is, if a processor has a copy that needs to be invalidated, that copy is kept in the cache manager. Fig. 1 schematically shows that a cache manager 31 is set in the processor 01, a cache manager 32 is set in the processor 02, a cache manager 33 is set in the processor 03, and a cache management is set in the processor 04 device 34. Each cache manager can be implemented by a hardware circuit. Usually, the cache manager operates on data at the granularity of data segments based on the snoopy protocol. In an optional implementation manner, the cache management manager performs an invalidation operation on multiple data segments included in the copy to be invalidated at a data segment granularity. The invalid operation mentioned here refers to modifying the status of the data segment to invalid when the status of the data segment is one of modified, unique and shared.

As shown in FIG. 5 , each processor may also be provided with an invalidation manager, and the invalidation manager may also be called a flush engine (flush engine). An invalidation manager 41 is set in the processor 01 , an invalidation manager 42 is set in the processor 02 , an invalidation manager 43 is set in the processor 03 , and an invalidation manager 44 is set in the processor 04 . Each invalidation manager may be a hardware circuit. The invalidation manager is used to obtain a signal from the memory manager, which indicates invalidation of a copy of data in a declared address space; based on the signal, the invalidation manager will The address space of a statement to be invalidated is decomposed into multiple address ranges, and one address range corresponds to one data segment; the invalidation manager provides the multiple address ranges to the cache manager respectively. For example, assume that the invalidation manager 43 receives a signal from the memory manager 21 indicating that the data in the address space p1 is invalidated; assuming that the granularity for storing data in the cache manager is 0x0100, the invalidation manager 43 based on the received signal, decompose the addresses in the address space p1 into 10 addresses, namely address 0x0000-0x0100, address 0x0101-0x0200, ... address 0x0901-0x1000, and then provide the ten addresses to the cache manager 33 in time-sharing. So that the cache manager 33 invalidates the data in the ten addresses.

In the embodiment of the present application, by setting an invalidation manager, when a large amount of data in a certain address space is invalidated, the memory manager used to manage the address space can provide a signal indicating invalidation of the data in the address space to the invalidation management The invalidation manager further decomposes the address region corresponding to the address space, and provides multiple decomposed address ranges to the on-chip cache manager. Therefore, compared with the traditional technology where the memory manager needs to send multiple signals to the cache manager, the embodiment of the present application can send a signal once to invalidate a large amount of data, which releases the bandwidth of the interconnection network and is conducive to improving the bandwidth. utilization rate. In addition, since the invalidation manager and the cache manager are located in the same processor, the address range is decomposed by the invalidation manager, and multiple address ranges are provided to the cache manager through the invalidation manager, and the memory manager needs to provide off-chip The buffer manager can reduce the signal transmission delay compared with transmitting multiple signals. To sum up, the shared storage system 100 provided by the embodiment of the present application can improve the bandwidth utilization rate of the interconnection network and reduce signal delay, thereby improving the performance of the shared storage system 100 .

In the embodiment of the present application, when a data copy stored in a certain processor is invalidated, if the data is dirty (dirty) data, the cache manager of the processor needs to write the dirty data back into the memory. Based on this, in an optional implementation manner of the embodiment of the present application, when the data to be invalidated is dirty data, the cache manager may also be used to transmit the dirty data to the invalidation manager in the chip. An invalid manager writes dirty data back into memory. It should be noted that after the memory manager initiates invalidation of the data copy of a certain address space stored in a processor and before the processor returns to the memory manager information indicating that the invalidation is completed, the memory manager invalidates the data copy of the address space. Locked, that is, no other processor can access the address space.

In the shared storage system 100 described in FIG. 5 , when the memory manager needs to invalidate a large amount of data in a declared address space stored in the cache manager, a signal indicating invalidation of the declared air data copy is transmitted to the cache manager. In an optional implementation of the embodiment of the present application, if the memory manager needs to store invalid data outside the declared address space (for example, the memory manager 21 needs to invalidate the data in addresses 0x3100-0x3200 shown in FIG. 3 ), or when the number of data to be invalidated is the number stipulated in the snoopy protocol (such as the data of a data segment), the memory manager can directly transmit a signal indicating invalid data in a certain address range to the cache manager. In addition, if the cache manager detects that dirty data is stored in the address range based on the signal, it can directly write the dirty data back into the corresponding address range in the memory.

Based on the shared storage system 100 shown in FIG. 5 , the mapping relationship between the memory and the global address space shown in FIG. 2 , and the address space of the memory 11 shown in FIG. 3 , both the cache manager 32 and the cache manager 33 cache Taking the address space p1 in the memory 11 and the cache manager 32 requesting to rewrite the data in the address space p1 as an example, the interaction process between the components in the shared storage system 100 shown in FIG. 5 will be described. Please refer to FIG. 6. FIG. 6 is an interaction process 600 between components in the shared storage system 100 shown in FIG. 5. The interaction process includes the following steps:

Step 601 , the cache manager 32 sends a request q2 to the memory manager 21 , the request q2 instructs to rewrite the data in the address range A.

In step 602, the memory manager 21 sends a signal s2 to the invalidation manager 43 based on the request q2. Specifically, after receiving the request q2, the memory manager 21 first finds out that the address range R is located in the address space p1. Then, the memory manager 21 can query and find out that the cache manager 32 stores a copy of the data in the address space p2. Finally, the memory manager 21 sends a signal s2 to the invalidation manager 43 indicating a copy of the data in the invalidation address space p1.

In step 603, the invalidation manager 43 generates an invalidation signal i1, an invalidation signal i2 and an invalidation signal i3 based on the signal s2, the preset size of the data segment and the address space p1. In step 604, the invalidation manager 43 provides the invalidation signal i1, the invalidation signal i2 and the invalidation signal i3 to the cache manager in time division. Specifically, the invalidation manager 43 divides the address space p1 into three address ranges of address range a1, address range a2, and address range a3 based on the size of the preset data segment, wherein the amount of data in each address range is one data part. The data segment is the cache manager's granularity for data operations. Invalid signal il indicates a copy of data in invalid address range al, invalid signal i2 indicates a copy of data in invalid address range a2, and invalid signal i3 indicates a copy of data in invalid address range a3. It should be noted that FIG. 6 shows that the invalidation manager 43 transmits three signals to the cache manager. It can be understood that this embodiment of the present application is limited to this. In a specific scenario, it can be based on the size of the address space and The size of the data segment to adjust the number of divided address ranges and the number of generated signals.

Step 605, the cache manager 33 detects that the data segment in the address range a1 has not been rewritten based on the signal i1 (that is, the state information of the data segment is one of unique, shared and invalid), and transmits a response to the invalid manager 43 r1, the response r1 indicates that the data segment in the address range a1 has not been rewritten; the cache manager 33 detects that the data segment in the address range a2 has not been rewritten based on the signal i2, and transmits a response r2 to the invalidation manager 43, and the response r2 indicates the address The data segment in the range a2 has not been rewritten; the cache manager 33 detects that the data segment in the address range a3 has not been rewritten based on the signal i3, and transmits a response r3 to the invalidation manager 43, and the response r3 indicates the data segment in the address range a3 Not overwritten. It should be noted that, if the status information of the data segment in the address range a1-address range a3 is one or shared, the cache manager 33 needs to modify the status information "unique" or "shared" to the status before transmitting the response The message is "invalid".

It should be noted that the above step 604 and step 605 are not used to limit the sequence of time. For example, in the first clock cycle, the invalidation manager 43 sends an invalidation signal i1 to the cache manager 33; in the second clock cycle, the invalidation manager 43 sends an invalidation signal i2 to the cache manager 33, and the cache manager 33 based on the invalidation Signal i1 generates a response r1 and transmits it to the invalidation manager 43; in the third clock cycle, the invalidation manager 43 sends an invalidation signal i3 to the cache manager 33, and the cache manager 33 generates a response r2 based on the invalidation signal i2 and transmits it to the invalidation manager 43 : In the fourth clock cycle, the cache manager 33 generates a response r3 based on the invalidation signal i3 and transmits it to the invalidation manager 43 .

In step 606, the invalidation manager 43 transmits a signal s3 to the memory manager 21 based on the response r1, the response r2 and the response r3, and the signal s3 indicates that the invalidation of the data copy in the address space p1 is completed. In this step, the invalidation manager 43 transmits a signal s3 to the memory manager 21 when all responses are received and each response indicates that the data segment in the address range has not been rewritten.

Step 607, the memory manager 21 sends a signal s4 to the cache manager 32, the signal s4 is used to indicate that the cache manager 32 is allowed to rewrite the data in the address range A.

In step 605 of the interaction process 600 shown in FIG. 6 , the cache manager 33 detects that the status information of the data in the address range a1 - address range a3 is one of unique, shared and invalid. In a possible implementation of the embodiment of the present application, the state information of the data segments in at least part of the address ranges in the address range a1-address range a3 is modified (modity), that is, in the address range a1-address range an Dirty data exists in at least part of the address range of . When there is dirty data, it is also necessary to write the dirty data back into the memory 11 . The following describes in detail through the interaction process 700 shown in FIG. 7 .

In FIG. 7 , steps 701 to 704 are the same as steps 601 to 604 shown in FIG. 6 . For details, refer to related descriptions of steps 601 to 604 in FIG. 6 , and details are not repeated here.

Step 705, the cache manager 33 detects that the data segment in the address range a1 has not been rewritten based on the signal i1, and transmits a response r4 to the invalidation manager 43, and the response r4 indicates that the data segment in the address range a1 has not been rewritten; the cache manager 33 detects that the data segment in the address range a2 has not been rewritten based on the signal i2, and transmits a response r2 to the invalidation manager 43, and the response r2 indicates that the data segment in the address range a2 has not been rewritten; the cache manager 33 detects that the data segment in the address range a2 is not rewritten based on the signal i3 If the state information of the data segment in the address range a3 is modified, a response signal r3 is transmitted to the invalidation manager 43, and the response signal r3 includes the data segment D1 in the address range an.

Step 706 , the invalidation manager 43 writes the data segment D1 back into the address range an in the memory 11 .

Step 707, the memory manager 21 detects that the data segment D1 has been stored in the memory 11, and sends a signal S5 to the invalidation manager 43, and the signal S5 indicates that the storage of the data segment D1 is completed.

Steps 708 to 709 are the same as steps 606 to 607 shown in FIG. 6 . For details, refer to related descriptions of steps 606 to 607 in FIG. 6 , and details are not repeated here.

Based on the interaction process shown in FIG. 6 and FIG. 7, in one scenario, before step 601 shown in FIG. 6 (or step 701 shown in FIG. 7), cache manager 33 will is transmitted to the memory 11, and when the cache manager 33 receives the invalid signal i1 in step 605, the data in the address range a1 has not been transmitted yet. Based on this scenario, please refer to FIG. 8 , which is another interaction process 800 of the shared storage system 100 provided by the embodiment of the present application. The interaction process 800 includes the following steps:

Step 801 , the cache manager 33 writes the data segment D2 in the address range a1 to the memory 11 .

Steps 802 to 805 are the same as steps 601 to 604 shown in FIG. 6 . For details, refer to related descriptions of steps 601 to 604 in FIG. 6 , and details are not repeated here.

Step 806, the cache manager 33 detects that the data segment in the address range a2 has not been rewritten based on the signal i2, and transmits a response r2 to the invalidation manager 43, and the response r2 indicates that the data segment in the address range a2 has not been rewritten; the cache manager 33 detects that the data segment in the address range a3 has not been rewritten based on the signal i3, and transmits a response r3 to the invalidation manager 43, which indicates that the data segment in the address range a3 has not been rewritten.

Step 807, the memory manager 21 transmits a signal S6 to the cache manager 33, and the signal S6 indicates that the storage of the data segment D2 is completed.

Step 808 , the cache manager 33 transmits a response r1 to the invalidation manager 43 based on the signal i1 and the signal S6 , and the response r1 indicates that the data segment in the address range a1 has not been rewritten.

Steps 809 to 810 are the same as steps 606 to 607 shown in FIG. 6 . For details, refer to related descriptions of steps 606 to 607 in FIG. 6 , and details are not repeated here.

Based on the same inventive concept, the embodiment of the present application also provides a method for invalidating cached data, and the method for invalidating cached data can be applied to any memory manager as shown in FIG. 1 . Please continue to refer to FIG. 9 , which shows a process 900 of the method for invalidating cached data provided by the embodiment of the present application. The method comprises the following steps: step 901, receiving a first request from a first processor, the first request indicating rewriting data in a first address, the first address being an address in a shared memory; step 902, based on The first request sends a first signal to the second processor, the first signal indicates invalidation of the first data stored by the second processor, and the first data is a first address in the shared memory A copy of the data in the space in which the first address is located.

It should be noted that, the memory manager executing the process 900 may be set in any processor shown in FIG. 1 , and the memory manager executing the process 900 is denoted as a third processor. The above-mentioned first processor, the second processor and the third processor are all different processors. For example, in FIG. 1, the first processor is processor 01, the second processor is processor 02, and the third processor is processor 03, wherein the third processor 03 is provided with a memory manager 33, and the memory management The device 33 is used to execute the process 900 shown in FIG. 9 .

In a possible implementation manner, the method further includes: receiving a second signal from the second processor, the second signal indicating completion of invalidation of the first data; based on the second signal, sending a third signal to the first processor, the third signal indicating that the first processor is allowed to rewrite the data in the first address.

Based on the same inventive concept, an embodiment of the present application also provides a method for invalidating cached data, and the method for invalidating cached data can be applied to any processor shown in FIG. 1 . Please continue to refer to FIG. 10 , which shows a process 1000 of the method for invalidating cached data provided by the embodiment of the present application. Including the following steps: Step 1001, receiving a first signal from the memory manager, the first signal is used to indicate the invalidation of the saved first data, the first data is the data of the first address space in the shared memory , the first address is located in the first address space; Step 1002 invalidates the first data based on the first signal.

In a possible implementation manner, the invalidating the first data based on the first signal includes: decomposing the first address space into A plurality of address ranges, obtaining a plurality of data segments corresponding to the first data, wherein one address range corresponds to a data segment; invalidating the plurality of data segments.

In a possible implementation manner, the invalidating the plurality of data segments includes: when the state of at least some of the data segments in the plurality of data segments is one of the shared state or the exclusive state, setting the The state of at least some of the data segments is modified to an invalid state.

In a possible implementation manner, the method further includes: when the state of each data segment in the plurality of data segments is an invalid state, transmitting a second signal to the memory manager, the second Signaling completion of invalidation of the first data.

In a possible implementation manner, before the transmitting the second signal to the memory manager, the method further includes: when the state of the first data segment among the plurality of data segments is a rewritten state, Writing the second data segment back into the corresponding address range in the shared memory.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present application. scope.

Claims

A shared storage system, characterized in that it includes a memory manager, a plurality of processors and shared memory;

The first processor among the plurality of processors is configured to send a first request to the memory manager, the first request indicates to rewrite data in a first address, and the first address is the shared memory address in

The memory manager, based on the first request, sends a first signal to a second processor among the plurality of processors, the first signal indicating invalidation of the first data stored by the second processor , the first data is a copy of data in a first address space in the shared memory, and the first address is located in the first address space;

The second processor invalidates the first data based on the first signal.
The shared storage system according to claim 1, wherein the second processor is specifically configured to:

Based on the first signal and the size of the preset data segment, decomposing the first address space into multiple address ranges to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment ;

The plurality of data segments are invalidated.
The shared storage system according to claim 2, wherein the second processor is specifically configured to:

When the state of at least some of the data segments in the plurality of data segments is one of the shared state or the exclusive state, modify the state of the at least some of the data segments to an invalid state.
The shared storage system according to claim 2 or 3, wherein the second processor includes a cache manager and an invalidation manager;

The invalidation manager generates multiple invalidation signals based on the multiple address ranges, one address range corresponds to one invalidation signal; and transmits the multiple invalidation signals to the cache manager in time-sharing;

The cache manager invalidates the plurality of data segments based on the plurality of invalidation signals.
The shared storage system according to claim 4, wherein:

The cache manager is further configured to send multiple responses to the invalidation manager for the multiple invalidation signals, wherein one response corresponds to one data segment, and the first response in the multiple responses indicates the A first data segment of the plurality of data segments has not been rewritten;

The invalidation manager is further configured to transmit a second signal to the memory manager based on the plurality of responses, the second signal indicating completion of the invalidation of the first data.
The shared storage system according to claim 5, wherein the second response in the plurality of responses carries a second data segment in the plurality of data segments, and the state of the second data segment is overwritten state;

The invalidation manager is further configured to write the second data segment back into the corresponding address range in the shared memory.
The shared storage system according to claim 5, wherein the first invalidation signal in the plurality of invalidation signals indicates that the first data segment is invalid; and the cache manager is specifically used for:

Before receiving the first invalidation signal, writing the first data segment back to the shared memory;

The first response is sent to the invalidation manager in response to a third signal sent by the memory manager, the third signal indicating that the storage of the first data segment is complete.
The shared storage system according to claim 5, wherein the memory manager is also used for:

A fourth signal is sent to the first processor based on the second signal, the fourth signal indicating that the first processor is allowed to rewrite data in the first address.
The shared storage system according to any one of claims 4-8, wherein,

A third processor among the plurality of processors is configured to send a second request to the memory manager, the second request indicates to rewrite data in a second address, and the second address is the shared memory address in

The memory manager, based on the second request, sends a fifth signal to the cache manager, the fifth signal indicating invalidation of the second data stored by the cache manager, the second data being the a copy of the data in the second address;

The cache controller, in response to the fifth signal, sends a third response to the memory manager, the third response indicating that the second data is modified or not modified.
A device, characterized in that it includes a memory manager, the memory manager is used for:

receiving a first request from a first processor, the first request indicating rewriting data in a first address, where the first address is an address in a shared memory;

Based on the first request, send a first signal to the second processor, the first signal indicates invalidation of the first data stored by the second processor, the first data is the first data in the shared memory a copy of the data of the address space in which the first address is located;

Wherein, the shared memory is managed by the memory manager, and the address space in the shared memory is allowed to be accessed by the first processor and the second processor.
The device according to claim 10, wherein the memory manager is also used for:

receiving a second signal from the second processor indicating completion of the invalidation of the first data;

Based on the second signal, a third signal is sent to the first processor, the third signal indicating that the first processor is allowed to rewrite data in the first address.
The device according to claim 10 or 11, wherein the memory manager is also used for:

monitoring that the second processor stores a first data segment in the shared memory, where the first data segment is a segment of data in the first data;

In response to the completion of storage of the first data segment, a fourth signal is sent to the second processor, where the fourth signal indicates that the storage of the first data segment is complete.
An apparatus, characterized by comprising a processor configured to:

Receive a first signal from the memory manager, the first signal is used to indicate that the saved first data is invalid, the first data is a copy of data in a first address space in the shared memory, and the first address is located at the In the first address space, the shared memory is managed by the memory manager;

Based on the first signal, the first data is invalidated.
The device according to claim 13, wherein the processor is specifically configured to:

Based on the first signal and the size of the preset data segment, decomposing the first address space into multiple address ranges to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment ;

The plurality of data segments are invalidated.
The device according to claim 14, wherein the processor is specifically configured to:

When the state of at least some of the data segments in the plurality of data segments is one of the shared state or the exclusive state, modify the state of the at least some of the data segments to an invalid state.
The apparatus according to claim 14 or 15, wherein the processor comprises a cache manager and an invalidation manager;

The invalidation manager generates a plurality of invalidation signals based on the plurality of address ranges, one address range corresponds to one invalidation signal; and transmits the plurality of invalidation signals to the cache manager in time-sharing;

The cache manager invalidates the plurality of data segments based on the plurality of invalidation signals.
The device according to claim 16, characterized in that,

The cache manager is further configured to send multiple responses to the invalidation manager for the multiple invalidation signals, wherein one response corresponds to one data segment, and the first response in the multiple responses indicates the A first data segment of the plurality of data segments has not been rewritten;

The invalidation manager is further configured to transmit a second signal to the memory manager based on the plurality of responses, the second signal indicating completion of the invalidation of the first data.
The device according to claim 17, wherein the second response in the plurality of responses carries the second data segment in the plurality of data segments, and the status of the second data segment is rewritten state;

The invalidation manager is further configured to write the second data segment back into the corresponding address range in the shared memory when the state of the second data segment is in a rewritten state.
The device according to claim 17 or 18, wherein a first invalidation signal among the plurality of invalidation signals indicates that the first data segment is invalid; and the cache manager is specifically used for:

Before receiving the first invalidation signal, writing the first data segment back to the shared memory;

The first response is sent to the invalidation manager in response to a fourth signal sent by the memory manager, the fourth signal indicating that the storage of the first data segment is complete.
A method for invalidating cached data, comprising:

receiving a first request from a first processor, the first request indicating rewriting data in a first address, where the first address is an address in a shared memory;

Based on the first request, send a first signal to the second processor, the first signal indicates invalidation of the first data stored by the second processor, the first data is the first data in the shared memory A copy of the data of the address space in which the first address is located.
The method according to claim 20, further comprising:

receiving a second signal from the second processor indicating completion of the invalidation of the first data;

Based on the second signal, a third signal is sent to the first processor, the third signal indicating that the first processor is allowed to rewrite data in the first address.
A method for invalidating cached data, comprising:

Receive a first signal from the memory manager, the first signal is used to indicate that the saved first data is invalid, the first data is a copy of data in a first address space in the shared memory, and the first address is located at the in the first address space;

Based on the first signal, the first data is invalidated.
The method according to claim 22, wherein said invalidating said first data based on said first signal comprises:

Based on the first signal and the size of the preset data segment, decomposing the first address space into multiple address ranges to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment ;

The plurality of data segments are invalidated.
The method according to claim 22, wherein said invalidating said plurality of data segments comprises:

When the state of at least some of the data segments in the plurality of data segments is one of the shared state or the exclusive state, modify the state of the at least some of the data segments to an invalid state.
The method according to claim 23 or 24, wherein the method further comprises:

When the state of each data segment in the plurality of data segments is an invalid state, a second signal is transmitted to the memory manager, the second signal indicating completion of invalidation of the first data.
The method according to claim 25, wherein before transmitting the second signal to the memory manager, the method further comprises:

When the state of the first data segment among the plurality of data segments is the rewritten state, write the first data segment back into the corresponding address range in the shared memory.