WO2018059497A1

WO2018059497A1 - Cache consistency processing method and device

Info

Publication number: WO2018059497A1
Application number: PCT/CN2017/104021
Authority: WO
Inventors: 崔晓松; 陈云; 蔡毅; 黄勤业
Original assignee: 华为技术有限公司
Priority date: 2016-09-30
Filing date: 2017-09-28
Publication date: 2018-04-05
Also published as: CN107894914A

Abstract

A cache consistency method comprises: a first router (220) receives a consistency preserving request sent by a first processor core which is directly connected to the first router (220), the consistency preserving request carrying an identifier of the first processor core; inquire about a preset consistency preserving table entry according to the identifier of the first processor core, and generate a consistency preserving command for the consistency region according to the consistency preserving table entry; and send the consistency preserving command to other processor cores in the consistency region by means of a network on chip. While the cache consistency is effectively preserved within a certain region, problems of communication and area overhead of a multi-core processor on chip can also be alleviated.

Description

Cache consistency processing method and device

Technical field

The present invention relates to the field of cloud computing technologies, and in particular, to a cache coherency processing technique in an on-chip multi-core processor.

Background technique

The on-chip multi-processors (English: Chip Multi-processors, CMPs) architecture has become the mainstream architecture of processor design. It consists of many processor cores (Core) through a router (English: Router) on-chip network (English: Network on Chip, abbreviation: NoC) connection structure. The cache in the chip is designed according to the hierarchy. The L1 cache (English: Level-1 cache) is a private cache. It is designed inside the processor core, and the stored data block can only be used by the processor core. Access; L2 cache (English: Level-2cache) is a shared cache, in which the stored data blocks are shared data blocks, which can be accessed by multiple processor cores, and can generally be designed outside the processor core in a centralized manner, or Distributedly designed in the vicinity of each processor core, that is, physically distributed near each processor core and interconnected by an on-chip network, can be logically shared.

In an on-chip multi-core processor application, there are scenes where some data blocks are accessed by one or more processor cores in the processor. For this scenario, the data block is typically stored in a shared cache for access by one or more processor cores. To speed up access to the data block, a copy of the data block is created in a private cache of one or more processor cores that have accessed the data block, such that when a core accessing the data block needs to revisit the data block It only needs to read the data block into the core's private cache. Because a copy of the data block is stored in the private cache of the one or more processor cores being accessed, it is necessary to maintain consistency between the copies of the data block in the private cache of the plurality of cores, and to resolve the consistency between the copies. Sexual issues are known as Cache Coherence issues. The basic principle for solving the cache coherency problem is that when a copy of the data block is modified in a certain core, other processor cores storing the copy of the data block need to perform a consistency operation (ie, updating the data block in other cores). Copying or deleting a copy of the data block in other cores requires determining which of the cores in the multi-core processor have copies of the data block.

The specific ways to solve the cache consistency include: a directory-based consistency protocol and a snooping-based consistency protocol. The directory-based coherence protocol uses a directory to record which processor cores the data block is accessed by. When consistency maintenance is required, the processor core storing the copy of the data block is determined by querying the table entry. And then performing consistency operations on the data block in the corresponding processor core; the interception-based consistency protocol is a method in which all processor cores listen to the bus, that is, when a processor core modifies its private cache. After a certain data block, the consistency maintenance message is broadcasted on the bus, so that other processor cores storing the copy of the data block perform a consistency operation.

With the development of cloud computing, the concept of resource pool came into being. The original server resources (processor, memory, network IO port, etc.) were assigned to one or more virtual machines. Through resource management software, it can be virtual. These resources are allocated by the machine. In a cloud computing scenario, how processor resources allocated to virtual machines achieve cache coherency is a problem facing the industry.

Summary of the invention

This paper describes a cache coherency processing method and apparatus to achieve cache coherency processing and communication of on-chip multi-core processors and balance of area overhead.

In one aspect, an embodiment of the present application provides a cache coherency processing method. The method is applied to an on-chip multi-core processor, comprising: a first router receiving a consistency maintenance request sent by a first processor core directly connected thereto, the consistency maintenance request carrying an identifier of a first processor core; Identifying a preset consistency maintenance entry, and generating a consistency maintenance command for the consistency area to which the first processor core belongs; sending the generated consistency maintenance command to the other processor in the consistent area through the on-chip network nuclear. In the above manner, consistency maintenance can be completed only in the consistent area where the cache data block write operation occurs, thereby avoiding the overhead caused by global consistency maintenance.

In a possible design, the first router queries the preset consistency maintenance entry according to the identifier of the first processor core, acquires the identifier of the consistency area to which the first processor core belongs, and is located in the An identifier of another processor core in the consistency region; and the first router generates an identifier for the consistency according to the identifier of the consistency region where the first processor core is located and the identifier of another processor core located in the consistency region Consistency maintenance commands for sexual areas.

In a possible design, the first router determines at least one route transmission path according to the on-chip network topology state and the identifiers of other processor cores in the consistent area, wherein each route transmission path is within the consistency zone The routers of the other processor cores are configured; for each routing transmission path, the first router reconfigures the consistency maintenance command to generate a consistency maintenance command for the routing path; and uses each routing transmission path. A consistency maintenance command for the route transmission path is sent to the processor core on the route transmission path. By adopting such a route-oriented transmission mode, the risk of broadcast storms existing in the on-chip network caused by the broadcast mode can be avoided, and the pressure of the routers included in the on-chip network can be effectively reduced.

In a possible design, the first router determines the identifier of the router connected to other processor cores in the consistency region according to the identifiers of other processor cores in the consistency region; and according to other processing in the consistency region The identifier of the router connected to the core and the topology state of the on-chip network. The first router performs route discovery according to the XY routing algorithm and determines at least one route transmission path. The above route discovery process conveniently and quickly determines the route transmission path included in the consistency area.

In another possible design, the preset consistency maintenance entry may be generated by: the resource manager receiving a processor resource allocation request sent by the virtual machine, and the processor resource allocation request for requesting the resource management Configuring a virtual machine to allocate at least two processors including a first processor core; the resource manager generates a consistency maintenance entry for the virtual machine according to the processor resource allocation request, where the consistency maintenance entry includes : The identity of the consistency zone and the identity of the processor core included in the consistency zone.

In another possible design, after the resource manager generates a consistency maintenance entry for the virtual machine according to the processor resource allocation request, the method further includes: the resource manager receiving the processor resource adjustment request sent by the virtual machine, and processing The resource adjustment request is used to request the resource manager to adjust the processor core allocated to the virtual machine; the resource manager adjusts the consistency maintenance entry for the virtual machine according to the processor resource adjustment request.

Wherein, when the processor resource adjustment is to reduce the processor core, the resource manager needs to write the cache data in the processor core to be reduced back into the memory, and then clear the data of the processor core to be reduced, and The identifier of the processor core to be reduced is deleted in the foregoing consistency maintenance entry; and when the processor resource adjustment is to increase the processor core, the resource manager records the identifier of the processor core to be added in the consistency maintenance. In the table entry.

In another aspect, an embodiment of the present invention provides a processor chip, where the processor chip includes: a plurality of processor cores, including a first processor core; and an on-chip network, which is composed of a plurality of routers, wherein the first a router, the first router and the first processor core are directly connected; wherein the first router comprises: a processor core connection port for connecting with the first processor core; at least one output port, and The at least one router of the on-chip network is connected to the server; the cache module is configured to store a preset consistency maintenance entry; and the processing module is configured to receive, by using the processor core connection port, the consistency sent by the first processor core a maintenance request, the consistency maintenance request carrying the identifier of the first processor core, querying the consistency maintenance entry stored in the buffer according to the identifier of the first processor core, and according to the consistency The maintenance maintenance entry generates a consistency maintenance command for the consistency area, and sends the consistency maintenance command to the consistency area by using the output port. Other processor cores.

In a possible design, the processing module is further configured to: query the consistency maintenance entry stored by the cache module according to the identifier of the first processor core, and obtain the identifier of the consistency region to which the first processor core belongs And an identifier of the other processor cores located in the consistency area; and generating an identifier for the identifier of the consistency area of the first processor core and the identifiers of other processor cores located in the consistency area A consistency maintenance command for the consistency zone.

In a possible design, the processing module is further configured to: according to the on-chip network topology state, and the identifiers of other processor cores in the consistency region, the first path determines at least one route transmission path, where each The routing transmission path is composed of routers connected to other processor cores in the consistency area; for each of the routing transmission paths, the consistency maintenance command is reconstructed and generated, and the routing transmission is generated for the routing a consistency maintenance command of the path; using each of the routing transmission paths, a consistency maintenance command for the routing transmission path is sent to the processor core on the routing transmission path through the output port.

In a possible design, the processing module is further configured to: determine, according to the identifiers of other processor cores in the consistency region, identifiers of routers connected to other processor cores in the consistency region; according to other processor cores in the consistency region The identifier of the connected router and the topology state of the on-chip network, route discovery according to the XY routing algorithm, and determine at least one route transmission path.

In another aspect, an embodiment of the present invention provides a computer system, including the processor chip disclosed in the foregoing aspect, and a resource manager, configured to receive a processor resource allocation request sent by the virtual machine, where the processor The resource allocation request is used to request the resource manager to allocate at least two processors to the virtual machine; and generate a consistency maintenance entry for the virtual machine according to the processor resource allocation request, where the consistency maintenance entry includes: The identity of the sexual area and the identity of the processor core included in the consistent area. The function of the resource manager can be implemented in hardware or in hardware by executing the corresponding software. The hardware or software includes one or more modules corresponding to the functions described above. The modules can be software and/or hardware.

In a possible design, the resource manager is further configured to: receive a processor resource adjustment request sent by the virtual machine, where The processor resource adjustment request is used to request the resource manager to adjust the processor core allocated to the virtual machine; and adjust the consistency maintenance table for the virtual machine according to the processor resource adjustment request.

In another possible design, the resource manager is further configured to: when the processor resource adjustment request includes a decrease in processor resources, the resource manager needs to write the cache data in the processor core to be reduced back to the memory in advance. Then, the data of the processor core to be reduced is cleared, and the identifier of the processor core to be reduced is deleted in the consistency maintenance table item.

In another possible design, the resource manager is further configured to: when the processor resource adjustment is to increase a processor core, record the identifier of the processor core to be added in the consistency maintenance table entry. .

In still another aspect, an embodiment of the present invention provides a computer storage medium for storing computer software instructions for use in the router, including a program designed to perform the above aspects.

In still another aspect, an embodiment of the present invention provides a computer storage medium for storing computer software instructions for use by the resource manager, including a program designed to execute the above aspects.

Compared with the prior art, the solution provided by the present invention can more flexibly manage the consistency maintenance area to achieve cache coherency processing and communication of on-chip multi-core processors and balance of area overhead.

DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS The drawings to be used in the embodiments or the description of the prior art will be briefly described below.

1 is a schematic diagram of a cloud computing architecture applied to the present invention;

2 is a schematic diagram of a processor chip of the present invention;

FIG. 3 is a schematic flowchart of a cache consistency processing method according to an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of a router module according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly described below with reference to the accompanying drawings.

The system architecture and the service scenario described in the embodiments of the present invention are for the purpose of more clearly illustrating the technical solutions of the embodiments of the present invention, and do not constitute a limitation of the technical solutions provided by the embodiments of the present invention. The technical solutions provided by the embodiments of the present invention are equally applicable to similar technical problems.

As shown in FIG. 1 , the cloud computing architecture applied in this application is divided into four levels from top to bottom, namely:

Application Layer 100, which runs various applications (English: Application) to provide users with corresponding services.

The operating system layer (Operating System Layer) 200, which includes an operating system (English: Operating System, abbreviation: OS), is responsible for allocating hardware resources (processor, memory, and network IO) for various types of applications running thereon. The operating system and the application running on it constitute a software architecture of a virtual machine (English: Virtual Machine, VM for short). An operating system belonging to a virtual machine allocates hardware resources (eg, processor, memory, network IO, etc.) to applications running thereon within the scope of hardware resources owned by the virtual machine. Taking FIG. 1 as an example, Two virtual machines, wherein the virtual machine 1 includes an operating system 1 and an application 1 and an application 2, the virtual machine 2 including an operating system 2 and an application 3 and an application 4.

Resource Management Layer 300, which runs a resource manager (English: Resource Manager, RM for short). In a cloud computing system, multiple virtual machines are created on a physical machine (English: Physical Machine, PM). When a virtual machine is created, it needs to allocate hardware resources to the virtual machine to be created through the resource manager. These hardware resources include: processor, memory, network IO, and so on. In practical applications, the resource manager is also referred to as a virtual machine monitor (English: Virtual Machine Monitor, referred to as: VMM) or a hypervisor.

The processor layer 400 includes hardware resources that the resource management layer 300 can manage. By way of example, FIG. 1 shows a processor, a memory, a network IO, and the like.

As an example of a processor, FIG. 2 shows an on-chip multi-core processor composed of 16 processor cores (abbreviation: core, English: Core) through an on-chip network connection of 16 routers. Each core is directly connected to a router, and an inter-core network formed by a router can implement inter-core communication. It should be noted that the core and the router can be connected by wire (electrical connection, such as copper wire connection; optical connection, such as fiber connection), or wireless connection.

The embodiment of the invention is directed to a solution to the cache consistency problem in a cloud computing scenario. In a cloud computing scenario, at least two virtual machines are created on a single server. When a virtual machine is created, the resource manager is required to allocate hardware resources for it. The resource manager allocates a certain number of processor cores to the virtual machine as processing resources of the virtual machine. The hardware resources owned by any two virtual machines are logically completely isolated. Based on this application scenario, in the process of cache coherency operation of the on-chip multi-core processor, there is no need to adopt a "global consistency" method for all processor core cache coherency processing, but only local consistency is required. Just handle it.

Specifically, as shown in FIG. 2, the on-chip multi-core processor includes 16 processor cores, and it is assumed that the on-chip multi-core processor is allocated to two virtual machines by the resource manager. Wherein processor cores 0-9 and 12-13 are assigned to virtual machine 1, processor cores 10-11 and 14-15 are assigned to virtual machine 2, since processor cores assigned to different virtual machines are logically isolated Therefore, the processor core in Figure 2 is divided into two consistent regions, as shown in Table 1:

一致性区域编号Consistent area number	所包含的处理器核Included processor core

一致性区域1Consistency area 1	核0-9，及核12-13Core 0-9, and core 12-13
一致性区域2 Consistency area 2	核10-11，及核14-15Nuclear 10-11, and nuclear 14-15

Table I

For the virtual machine 1, taking the processor core 1 as an example, after the core 1 writes a certain cache data block of the private cache in the core, it needs to be in the consistency area 1 where the processor core 1 is located, for the cache. The data block performs consistency maintenance operations, and the processing procedure is as follows:

Step 310: The first router receives a consistency maintenance request sent by the first processor core, where the consistency maintenance request carries an identifier of the first processor core.

As an example of the implementation process, referring to FIG. 2, the consistency maintenance request is a processor core that has completed the data block write operation. The cache controller sent by 1 carries the identifier of the processor core 1 in the consistency operation request. The identifier of the processor core may be the number of the processor core of the system.

Step 320: The first router queries the preset consistency maintenance entry according to the identifier of the first processor core, and obtains an identifier of the consistency area to which the first processor core belongs, and an identifier of another processor core located in the consistency area. .

The consistency maintenance entry is generated according to the processor resource allocation request after the virtual machine is created by the resource manager after receiving the processor resource allocation request sent by the virtual machine. The processor resource allocation request is used to request the resource manager to allocate at least two processors to the virtual machine. As an example, the consistency maintenance entry structure includes: a valid bit (Valid), a coherence domain identifier (CD: ID), and a core ID of the coherent area, where The valid bit is used to indicate whether the entry is valid; the consistency zone identifier is used to indicate the identity of the consistency zone; the core identity of the consistency zone is in the form of a bit mask, from right to left. Indicates whether the corresponding processor core belongs to the consistency region (where the bit is 1, indicating that it belongs to the consistency region, and if the bit is 0, it indicates that the consistency region is not included). Taking the consistency area 1 and the consistency area 2 in FIG. 2 as an example, the maintenance table item of the consistency area is represented as follows, wherein the on-chip multi-core processor shown in FIG. 2 includes 16 cores and is composed of 16 bits. The vector is used to represent (from right to left, sequentially representing the core 0-core 15), as shown in Table 2:

Table II

After the resource manager creates the consistency maintenance entry, it sends the consistency maintenance entry to the router in the corresponding consistency zone. By way of example, referring to FIG. 2, the resource manager sends the consistency maintenance entry of the consistency zone 1 to the router included in the consistency zone 1, and the router can store the consistency maintenance entry in its own cache or router. In the register.

In this step, the first router queries the consistency maintenance entry according to the identifier of the first processor core, and may specifically: query the core attribution of the consistency region of the consistency maintenance entry by using the number of the first processor core. An identifier that determines an identity of a coherency zone to which the first processor core belongs, and an identity of other processor cores located within the coherency zone.

Step 330: The first router generates a consistency maintenance command for the consistency area according to the identifier of the consistency area where the first processor core is located, and the identifiers of other processor cores located in the consistency area.

In this step, the first router generates a consistency maintenance command for the consistency zone according to the identifiers of other processor cores located in the consistency zone. As an example, the consistency maintenance command adds fields such as the CDID field and the Core IDs field based on the routing packet structure. The meaning of each domain is shown in Table 3:

Flit TypeFlit Type	Src AddrSrc Addr	Dst AddrDst Addr	CDIDCDID	Core IDsCore IDs	PayloadPayload
0x990x99	11	--	11	00110011111111110011001111111111	Set a＝2Set a=2

Table 3

Flit Type: defines the consistency command type, such as: 0x99;

Src Addr: The source address, in this scenario, refers to the identifier of the Core that initiates the consistency maintenance request. (In this embodiment, the initiator consistency maintenance request is processor core 1, whose number is 1);

Dst Addr: destination address (reserved here);

CDID: the consistency area identifier in the consistency maintenance entry (in the example of this embodiment, the consistency area identifier is 1);

Core IDs are the cores of the consistency zone in the consistency maintenance table. In this example, the processor cores corresponding to the core identity of the consistency zone are cores 0-9 and 12-13.

Payload: refers to the consistency operation content specifically included in the consistency maintenance command (for example, updating the data of a variable to a certain value. In the example of this embodiment, setting the value of the variable a to 2) .

Step 340: The first router sends the consistency maintenance command to the other processor cores of the consistency area through the on-chip network.

In this step, there are two implementations:

Method 1: Adopting the broadcast method

By way of example, in FIG. 2, the router 1 broadcasts the generated consistency maintenance command to other processor cores in the coherency area (ie, cores 0-9 and cores 12-13) through the on-chip network, router 1 The consistency maintenance command is sent to other processor cores (core 0, and core 2-15) on the on-chip multi-core processor through other routers (router 0, and router 2-15) in the on-chip network, each receiving The processor core of the consistency maintenance command compares its own identifier with the Core Ids field of the consistency maintenance command. When the bit corresponding to the Core IDs is 1, the processor core belongs to the consistent area. Consistency processing is required according to the consistency maintenance command. When the bit corresponding to the Core IDs is 0, the processor core does not belong to the consistency zone. The consistency maintenance command is discarded and no processing is performed.

Method 2: Adopt route-oriented sending method

By way of example, in FIG. 2, the router 1 acquires the topology state of the on-chip network and the identifiers of other processor cores in the consistency region, and determines at least one route transmission path according to the obtained information. Specifically, the router 1 can sense the topology state of the on-chip network, calculate the possible next hop mode, and confirm the next hop node, that is, the router (0, 2, 5). For example, in a 2D mesh network, according to the XY routing method, (x+1, y), (x-1, y), (x, y+1), (x, y-1) are respectively calculated, and the router 1 is determined. The first hop node is the router (0, 2, 5). Router 1 obtains the identifier of the other processor cores in the consistency area according to the consistency maintenance entry, and determines that the processor core connected to the router (0, 2, 5) belongs to the consistency area 1; then proceeds to the next manner in a similar manner. The selection of the hop node, the second hop node of the router 1 is the router (3, 4, 6, 9), and the router (3, 4, 6, 9) is determined according to the identifier of the other processor cores in the consistency area 1 is obtained. The connected processor core also belongs to the consistency area 1; the judgment is continued until the traversal judgment of the routing node in the consistency area 1 is completed; thus, three routing transmission paths can be obtained, namely: 1→0 →4→8→12 (westward route), 1→5→9→13 (route to the south), 1→2→3(6)→7 (route to the east).

For each route transmission path, the first router reconfigures the consistency maintenance command to generate a consistency maintenance command for the route transmission path, that is, generates a route directional transmission command according to the consistency maintenance command, Shown as follows:

(1) Routing Directional Sending Instructions (westbound routing) are shown in Table 4:

Flit TypeFlit Type	Src AddrSrc Addr	Dst AddrDst Addr	CDIDCDID	Core IDsCore IDs	PayloadPayload
0x990x99	11	--	11	00010001000100010001000100010001	Set a＝2Set a=2

Table 4

(2) Routing Directional Sending Instructions (Etherward Routing) are shown in Table 5:

Flit TypeFlit Type	Src AddrSrc Addr	Dst AddrDst Addr	CDIDCDID	Core IDsCore IDs	PayloadPayload
0x990x99	11	--	11	00000000110011000000000011001100	Set a＝2Set a=2

Table 5

(3) The route-oriented sending instruction (route to the south) is as shown in Table 6:

Flit TypeFlit Type	Src AddrSrc Addr	Dst AddrDst Addr	CDIDCDID	Core IDsCore IDs	PayloadPayload
0x990x99	11	--	11	00100010001000000010001000100000	Set a＝2Set a=2

Table 6

It should be noted that when the route-oriented sending instruction of the east route is sent to the router 2, the routing of the eastbound route is performed on the router 2 because there are two branches of 1→2→3→7 and 1→2→6. The send instruction can be further broken down into the following two:

(4) 2→3→7 route directional sending instructions, as shown in Table 7:

Flit TypeFlit Type	Src AddrSrc Addr	Dst AddrDst Addr	CDIDCDID	Core IDsCore IDs	PayloadPayload
0x990x99	11	--	11	000000010001000000000010001000	Set a＝2Set a=2

Table 7

(5) 2→6 route directional sending instructions, as shown in Table 8:

Flit TypeFlit Type	Src AddrSrc Addr	Dst AddrDst Addr	CDIDCDID	Core IDsCore IDs	PayloadPayload
0x990x99	11	--	11	00000000010000000000000001000000	Set a＝2Set a=2

Table eight

After the routing instruction is sent to the routing transmission path, the consistency maintenance command for the routing transmission path is sent to the processor core on the routing transmission path by using each routing transmission path.

By adopting such a route-oriented transmission method, the risk of broadcast storms existing on the on-chip network can be avoided, and the packet forwarding pressure of each routing node of the on-chip network is effectively reduced.

As an extension of the foregoing embodiment, after the resource manager receives the processor resource adjustment request sent by the virtual machine, the processor resource adjustment request is used to request the resource manager to adjust the processor core allocated to the virtual machine; resource management The device adjusts the consistency maintenance entry for the virtual machine according to the processor resource adjustment request.

The above adjustment requests include two types:

(1) increase of processor core

When the processor resource adjustment request includes an increase in processor resources, the resource manager needs to write the cache data in the added processor core to the memory (also referred to as main memory) in advance, and then the processor to be added. The data in the core is cleared, and the identifier of the processor core to be added is recorded in the above consistency maintenance table.

(2) processor core reduction

When the processor resource adjustment request includes reducing the processor resources, the resource manager needs to write the cache data in the processor core to be reduced back into the memory, and then clear the data of the processor core to be reduced, and The identifier of the processor core to be reduced is deleted in the above consistency maintenance entry.

FIG. 2 shows a block diagram of a design of a processor chip 200 involved in the above embodiment (limited to size, only a portion of the processor chip is shown). The processor chip 200 includes:

a plurality of processor cores, including a first processor core 210 (by way of example, core 1 as a first processor core);

The on-chip network is composed of a plurality of router connections, wherein the first router 220 is included, and the first router 220 is directly connected to the first processor core 210;

The first router 220 includes:

a processor core connection port 221 for connecting to the first processor core 210;

At least one output port 222 for connecting to at least one router of the network on the chip;

The cache module 223 is configured to store a preset consistency maintenance entry.

The processing module 224 is configured to receive, by the processor core connection port 221, a consistency maintenance request sent by the first processor core 210, where the consistency maintenance request carries an identifier of the first processor core 210; according to the identifier of the first processor core Querying the consistency maintenance table stored by the cache module 223, obtaining an identifier of a consistency area to which the first processor core 210 belongs, and an identifier of another processor core located in the consistency area; An identifier of the consistency area of the processor core 210, and an identifier of another processor core located in the consistency area, generating a consistency maintenance command for the consistency area; and passing the consistency maintenance command to the output port 222 Other processor cores sent to this coherency zone.

Figure 1 also shows a computer system comprising: a resource manager, a virtual machine running on the resource manager, and a processor chip as provided in the previous embodiment.

The resource manager is configured to receive an allocation request of a processor resource sent by the virtual machine, where the processor resource allocation request is used to request the resource manager to allocate at least two processors to the virtual machine; a processor resource allocation request, generating a consistency maintenance entry for the virtual machine, where the consistency maintenance entry includes: an identifier of the consistency area, and an identifier of a processor core included in the consistency area .

Further, the resource manager is further configured to: receive a processor resource adjustment request sent by the virtual machine, where the processor resource adjustment request is used to request the resource manager to allocate a processor core to the virtual machine Make adjustments; And adjusting, according to the processor resource adjustment request, a consistency maintenance entry for the virtual machine.

Further, the resource manager is further configured to: when the processor resource adjustment request is to reduce the processor core, the resource manager writes the cache data in the processor core to be reduced back into the memory, and then the processing to be reduced The data of the core of the kernel is cleared, and the identifier of the processor core to be reduced is deleted in the consistency maintenance entry;

When the processor resource adjustment is to increase the processor core, the identifier of the processor core to be added is recorded in the consistency maintenance table entry.

The resource manager can be implemented by software or by hardware + software. When implemented in hardware, the above-mentioned resource manager for executing the present invention is a central processing unit (English: Central Process ing Uni t, abbreviated: CPU), a general-purpose processor, and a digital signal processor (English: Digital Signal Processor, abbreviation) :DSP), application-specific integrated circuit (English: Application-specific integrated circuit, abbreviation: ASIC), Field Programmable Gate Array (English: Field Programmable Gate Array, abbreviation: FPGA) or other programmable logic devices, transistor logic devices, hardware A component or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.

The steps of a method or algorithm described in connection with the present disclosure may be implemented in a hardware, or may be implemented by a processor executing software instructions. The software instructions may be composed of corresponding software modules, which may be stored in a RAM (Random Access Memory) memory, a flash memory, a ROM (Read-Only Memory) memory, and an EPROM (Erasable Programmable Read- Only Memory, EEPROM (Electrically-Erasable Programmable Read-Only Memory) memory, registers, hard disk, mobile hard disk, CD-ROM or well known in the art Any other form of storage medium. An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC. Additionally, the ASIC can be located in the user equipment. Of course, the processor and the storage medium may also reside as discrete components in the user equipment.

Those skilled in the art will appreciate that in one or more examples described above, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. The scope of the protection, any modifications, equivalent substitutions, improvements, etc., which are made on the basis of the technical solutions of the present invention, are included in the scope of the present invention.

Claims

A cache coherency processing method is applied to an on-chip multi-core processor, and the method includes:

The first router receives a consistency maintenance request sent by the first processor core directly connected thereto, where the consistency maintenance request carries an identifier of the first processor core;

The first router queries a preset consistency maintenance entry according to the identifier of the first processor core, and generates a consistency maintenance command for the consistency area according to the consistency maintenance entry.

The first router sends the consistency maintenance command to the other processor cores of the consistency area through the on-chip network.
The method according to claim 1, wherein the first router queries a preset consistency maintenance entry according to the identifier of the first processor core, and generates a target according to the consistency maintenance entry. The consistency maintenance commands for the consistency zone include:

The first router queries the preset consistency maintenance entry according to the identifier of the first processor core, acquires the identifier of the consistency area to which the first processor core belongs, and performs other processing in the consistency area. Identification of the core;

The first router generates a consistency maintenance command for the consistency area according to the identifier of the consistency area where the first processor core is located and the identifiers of other processor cores located in the consistency area.
The method according to claim 1 or 2, wherein the first router sends the consistency maintenance command to the other processor cores of the consistency area by using the on-chip network, including:

Determining, by the first router, at least one route transmission path according to the on-chip network topology state and an identifier of another processor core in the consistency region, wherein each of the route transmission paths is associated with the consistent region a router connected to other processor cores;

And the first router reconfigures the consistency maintenance command to generate a consistency maintenance command for the route transmission path;

Using each of the routing transmission paths, a consistency maintenance command for the routing transmission path is sent to the processor core on the routing transmission path.
The method according to claim 3, wherein said first router determines at least one route transmission path according to said on-chip network topology state and an identifier of another processor core in said consistency region, including :

Determining, by the first router, an identifier of a router connected to another processor core in the consistency region according to an identifier of another processor core in the consistency region;

The first router performs route discovery according to the XY routing algorithm according to the identifier of the router connected to the other processor cores in the consistency area, and the topology state of the on-chip network, and determines the at least one route transmission path.
The method according to any one of claims 1-4, wherein before the first router queries the preset consistency maintenance entry according to the identifier of the first processor core, the method further includes:

The resource manager receives a processor resource allocation request sent by the virtual machine, where the processor resource allocation request is used to request the resource manager to allocate at least two processors including the first processor core to the virtual machine;

And the resource manager generates a consistency maintenance entry for the virtual machine according to the processor resource allocation request, where the consistency maintenance entry includes: an identifier of the consistency area, and the consistency area Included processor Nuclear identification.
The method according to claim 5, wherein after the resource manager generates a consistency maintenance entry for the virtual machine according to the processor resource allocation request, the method further includes:

The resource manager receives a processor resource adjustment request sent by the virtual machine, where the processor resource adjustment request is used to request the resource manager to adjust a processor core allocated to the virtual machine;

And the resource manager adjusts the consistency maintenance entry for the virtual machine according to the processor resource adjustment request.
The method according to claim 6, wherein the processor resource management unit adjusts the consistency maintenance entry for the virtual machine according to the processor resource adjustment request, including:

When the processor resource adjustment is to reduce the processor core, the resource manager writes the cache data in the processor core to be reduced back into the memory, and then clears the data of the processor core to be reduced, and The identifier of the processor core to be reduced is deleted in the consistency maintenance entry.
A processor chip, comprising:

a plurality of processor cores, including a first processor core;

An on-chip network, which is composed of a plurality of router connections, wherein the first router includes a first router, and the first router and the first processor core are directly connected;

The first router includes:

a processor core connection port for connecting to the first processor core;

At least one output port for connecting to at least one router of the on-chip network;

a cache module, configured to store a preset consistency maintenance entry;

a processing module, configured to receive, by the processor core connection port, a consistency maintenance request sent by the first processor core, where the consistency maintenance request carries an identifier of the first processor core; Querying, by the identifier of the processor core, the consistency maintenance entry that is stored in the buffer, and generating a consistency maintenance command for the consistency area according to the consistency maintenance entry; The output port is sent to other processor cores of the coherency area.
The processor chip according to claim 8, wherein the processing module is further configured to:

Querying, according to the identifier of the first processor core, the consistency maintenance entry stored by the cache module, obtaining an identifier of a consistency area to which the first processor core belongs, and other processor cores located in the consistency area Identification;

And generating a consistency maintenance command for the consistency area according to the identifier of the consistency area where the first processor core is located, and the identifiers of other processor cores located in the consistency area.
The processor chip according to claim 8 or 9, wherein the processing module is further configured to:

Determining, according to the on-chip network topology state, and identifiers of other processor cores in the consistency region, the first path determining at least one route transmission path, wherein each of the route transmission paths is associated with the consistent region a router connected to other processor cores;

Reconstructing the consistency maintenance command for each of the routing transmission paths, and generating a route for the routing Consistency maintenance command for the transmission path;

Using each of the routing transmission paths, a consistency maintenance command for the routing transmission path is sent to the processor core on the routing transmission path through the output port.
The processor chip according to claim 10, wherein the processing module is further configured to:

Determining an identifier of a router connected to another processor core in the consistency region according to an identifier of another processor core in the consistency region;

And performing route discovery according to the XY routing algorithm according to the identifier of the router connected to the other processor cores in the consistency area and the topology state of the on-chip network, and determining the at least one route transmission path.
A computer system, characterized in that the system comprises:

a resource manager, configured to receive an allocation request of a processor resource sent by the virtual machine, where the processor resource allocation request is used to request the resource manager to allocate at least two processors to the virtual machine; and according to the processing a resource allocation request, generating a consistency maintenance entry for the virtual machine, where the consistency maintenance entry includes: an identifier of the consistency area, and an identifier of a processor core included in the consistency area; A processor chip as claimed in any of claims 7-9.
The computer system according to claim 12, wherein the resource manager is further configured to: receive a processor resource adjustment request sent by the virtual machine, where the processor resource adjustment request is used to request the resource The manager adjusts a processor core allocated to the virtual machine; and adjusts a consistency maintenance entry for the virtual machine according to the processor resource adjustment request.
The computer system according to claim 13, wherein the resource manager is further configured to: when the processor resource adjustment request is to reduce a processor core, the resource manager is to be reduced by a processor The cached data in the core is written back into the memory, and then the data of the processor core to be reduced is cleared, and the identifier of the processor core to be reduced is deleted in the consistency maintenance table entry.