WO2015051488A1

WO2015051488A1 - Memory sharing method, device and system in aggregation virtualization

Info

Publication number: WO2015051488A1
Application number: PCT/CN2013/084821
Authority: WO
Inventors: 陈立钢; 郑伟; 卢广
Original assignee: 华为技术有限公司
Priority date: 2013-10-08
Filing date: 2013-10-08
Publication date: 2015-04-16
Also published as: CN103858111A; CN103858111B

Abstract

An embodiment of the present invention discloses a memory sharing method in aggregation virtualization. The method comprises: a cache coherence processor receiving a memory processing command sent by a virtual machine manager of a host; if the memory processing command is cache state update information, the cache coherence processor updating a local cache coherence catalog according to the cache state update information; or, if the memory processing command is a memory access request of a virtual machine on the host, the cache coherence processor performing cache coherence processing and accessing a memory corresponding to memory address information in the memory access request. A memory processing command is sent to a cache coherence processor through a virtual machine manager of a host, and the cache coherence processing is performed by the cache coherence processor, thereby improving system processing performance, and shortening the memory access time. Embodiments of the present invention also disclose a memory sharing device and system in aggregation virtualization.

Description

Method, device and system for realizing memory sharing in aggregate virtualization

Embodiments of the present invention relate to the field of computers, and in particular, to a method, device, and system for implementing memory sharing in aggregate virtualization.

Background Art Currently, aggregation virtualization technology is generally applied to applications of large servers. Multiple independent servers are interconnected through physical connections, and aggregated virtualization technology is used to make multiple servers appear as one server. After the aggregation virtualization technology is used, resources such as a central processing unit (CPU), a memory (Mem), and an output output (10) can be formed into a resource pool. External presentation, used for high performance computing and cloud computing infrastructure.

In the virtualized application scenario, the hypervisor software runs on each server, and the hypervisor is the cornerstone of virtualization. DomainO is a special virtual machine (Virtual Machine) on top of the Hypervisor. This virtual machine is used to complete the interaction of each virtual machine and some peripheral analog and peripheral access functions. In the aggregation virtualization solution, an Inf iniband (IB) card or an Ethernet card is installed on multiple servers, and these servers are interconnected through an Inf iniband switch or an Ethernet switch, and Hypervi sor runs on each server. The aggregation virtualization software is included. The aggregation virtualization software implements the Cache Coherent (CC) processing through the software itself, and accesses the memory on other servers through the Inf iniband switch or the Ethernet switch after the CC processing is completed. In this way, the memory sharing of each server in the aggregation virtualization is realized, and the aggregation virtualization software realizes the memory aggregation of a server externally presented by one server.

In the existing aggregation virtualization solution, the aggregation virtualization software is used for CC transaction processing to solve the cache consistency conflict caused by the memory sharing, and the CC transaction processing takes up more processor resources. If the system is large, CC transaction processing will become a system performance bottleneck. Aggregate virtualization single-time memory access operation delay is about 100 microseconds (us) level, and even at some time it is millisecond (ms) level, and Converged virtualization software for CC processing takes up most of the time. Therefore, the method of memory sharing in the existing aggregation virtualization scheme leads to system performance degradation. SUMMARY OF THE INVENTION In view of this, embodiments of the present invention provide a method, a device, and a system for implementing memory sharing in an aggregated virtualization, which can improve system processing performance and thereby shorten memory access time.

In a first aspect, an embodiment of the present invention provides a method for memory sharing in an aggregate virtualization, including:

The cache coherency processor receives the memory processing command sent by the virtual machine manager of the host; if the memory processing command is the cache status update information, the cache coherency processor updates the local cache coherency according to the cache status update information. The directory is updated, and the cache status update information includes memory block address information and cache status information;

Alternatively, the memory processing command is a memory access request of the virtual machine on the host, and the cache coherency processor performs cache coherency processing to access a memory corresponding to the memory address information in the memory access request.

In a first possible implementation manner of the first aspect, the cache coherency processor updates the local cache coherency directory according to the cache status update information, specifically:

Determining, by the cache coherency processor, a record of a memory block corresponding to the memory block address information in the local cache coherency directory according to the memory block address information;

Updating cache state information in the record of the memory block according to the cache state information in the cache state update information;

And determining, according to the current copy information in the record of the memory block, another host that stores the copy of the memory block, and notifying the cache coherency processor corresponding to the other host to update the local cache coherency directory.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner, the cache coherency processor performs cache coherency processing, and accesses a memory address in the memory access request The memory corresponding to the information is specifically:

If the memory corresponding to the memory address information is the memory on the host, the cache coherency processor performs cache coherency processing to access the memory of the host; Or the memory corresponding to the memory address information is a memory on a host other than the host, and the cache coherency processor performs cache coherency processing, and accesses the other host corresponding to the memory address information by using a switching network. Memory on.

In conjunction with the second possible implementation of the first aspect, in a third possible implementation, the cache coherency processor accesses the memory on the other host corresponding to the memory address information by using a switching network, specifically For:

The cache coherency processor communicates with the cache coherency processor of the other host connection corresponding to the memory address information by the switching network, and accesses memory on the other host corresponding to the memory address information.

In combination with the second or third possible implementation of the first aspect, in a fourth possible implementation manner, the method further includes:

And if the memory access request is a read memory instruction, the cache coherency processor sends the memory access result to the virtual machine manager of the host.

With reference to the first aspect, or any one of the first to fourth possible implementation manners of the first aspect, in a fifth possible implementation, the cache coherency processor receives the memory sent by the virtual machine manager of the host Before processing the command, it also includes:

The virtual machine manager of the host obtains the memory access request of the virtual machine; the virtual machine manager of the host determines, according to the memory address information in the memory access request, whether the memory that the memory access request needs to access is Is the memory on the host, if it is the memory on the host, accessing the memory on the host according to the memory access request, and sending the cache status update information to the cache consistency processor; If not the memory on the host, the memory access request is sent to the cache coherency processor.

In a second aspect, an embodiment of the present invention provides a method for memory sharing in an aggregate virtualization, including:

The virtual machine manager of the host obtains a memory access request of the virtual machine;

The virtual machine manager of the host determines, according to the memory address information in the memory access request, whether the memory that the memory access request needs to access is the memory on the host, and if it is the memory on the host, The memory access request accesses the memory on the host, and sends the cache status update information to the cache coherency processor when the memory access request is a memory write instruction. So that the cache coherency processor updates the cache state information corresponding to the memory block in the cache coherency directory in the cache coherency directory; if the memory access request is a read command, And the memory access request is sent to the cache coherency processor, so that the cache coherency processor performs cache coherency processing and accesses memory corresponding to the memory address information in the memory access request;

Or the virtual machine manager of the host sends the memory access request to the cache coherency processor, so that the cache coherency processor performs cache coherency processing and accesses a memory address in the memory access request. The memory corresponding to the information.

In a first possible implementation manner of the second aspect, if the memory access request is a read instruction, after the virtual machine manager of the host sends the memory access request to the cache coherency processor, Also includes:

The virtual machine manager of the host receives the memory access result returned by the cache coherency processor.

In a third aspect, an embodiment of the present invention provides a cache coherency processor, including: an input and output unit, configured to receive a memory processing command sent by a virtual machine manager of a host; a cache coherency processing unit, if the memory processing The command is a cache status update information, configured to send a cache consistent directory update command to the directory management unit according to the cache status update information, or the memory processing command is a memory access request of the virtual machine on the host, And performing cache coherency processing, accessing memory corresponding to the memory address information in the memory access request, where the cache state update information includes memory block address information and cache state information;

The directory management unit is configured to update a local cache coherency directory according to the cache coherency directory update instruction.

In a first possible implementation manner of the third aspect, the directory management unit is configured to update a local cache consistency directory according to the cache consistency directory update instruction, specifically:

The directory management unit is configured to determine, according to the memory block address information, a record of a memory block corresponding to the memory block address information in the local cache coherency directory, and update a cache status according to the cache status update information. The information is updated with the cache state information in the record of the memory block, and according to the current copy information in the record of the memory block, another host that saves the copy of the memory block is determined, and the cache corresponding to the other host is notified to be consistent. Scaling processors update their local caches Consistent directory.

With reference to the third aspect, or the first possible implementation manner of the third aspect, in a second possible implementation, the cache coherency processing unit is configured to perform cache coherency processing, and access the memory access request. The memory corresponding to the memory address information is specifically:

The cache coherency processing unit, if the memory corresponding to the memory address information is a memory on the host, is used for performing cache coherency processing, and accessing the memory of the host, if the memory address information corresponds to The memory is the memory on the host other than the host, and the cache coherency processing unit is configured to perform cache coherency processing, and the network interface unit accesses the other host corresponding to the memory address information via the switching network. RAM;

The cache coherency processor further includes:

The network interface unit is configured to provide communication between the cache coherency processing unit and the other host, and send information of the cache coherency processing unit to the other host through the switching network, The information of the other host received by the switching network is passed to the cache coherency processing unit.

With reference to the second possible implementation of the third aspect, in a third possible implementation, the cache coherency processing unit is configured to perform cache coherency processing, and access the memory address by using a network interface unit through a switching network. The memory on the other host corresponding to the information is specifically:

The cache coherency processing unit is configured to perform cache coherency processing, and the network interface unit communicates with the cache coherency processor connected to the other host corresponding to the memory address information through the switching network. The memory on the other host corresponding to the memory address information.

In combination with the second or third possible implementation of the third aspect, in a fourth possible implementation:

The cache coherency processing unit is further configured to: if the memory access request is a read memory instruction, send a memory access result to the virtual machine manager of the host by using the input and output unit.

With the second to fourth possible implementations of the third aspect, in a fifth possible implementation, the cache coherency processing unit includes:

a pre-processing sub-module, configured to be connected to the input and output unit, the local proxy sub-module, and the remote proxy sub-module, and configured to be responsible for the input and output unit and the local proxy sub-module, the remote end Message passing between proxy submodules;

The local proxy sub-module, configured to process a memory access request to the host, perform cache coherency processing, and send the cache coherency directory update command to the directory management unit; For processing a memory access request to a host other than the host, performing cache coherency processing, and accessing, by the network interface unit, the memory of the other host via the switching network.

In a fourth aspect, the embodiment of the present invention further provides a computer system, including: at least two hosts, at least two cache coherency processors, and a switching network, wherein each of the at least two hosts respectively Connected to one of the at least two cache coherency processors, the at least two cache coherency processors being connected by the switching network;

a first one of the at least two hosts, configured to send a memory processing command to the first cache coherency processor of the at least two cache coherency processors connected;

The first cache coherency processor, if the memory processing command is cache status update information, the first cache coherency processor is configured to update a local cache coherency directory according to the cache status update information, the cache The status update information includes the memory block address information and the cache status information, or the memory processing command is a memory access request of the virtual machine on the first host, configured to perform cache consistency processing, and access the memory access request. The memory corresponding to the memory address information.

In a first possible implementation manner of the fourth aspect, the first cache coherency processor is configured to update a local cache coherency directory according to the cache status update information, specifically:

The first cache coherency processor is configured to determine, according to the memory block address information, a record of a memory block corresponding to the memory block address information in the local cache coherency directory, and update information according to the cache status The cache state information in the cache updates the cache state information in the record of the memory block, and determines, according to the current copy information in the record of the memory block, the at least two hosts in which the copy of the memory block is saved The other hosts other than the first host notify the cache coherency processors corresponding to the other hosts to update their respective local cache coherency directories.

With reference to the fourth aspect, or the first possible implementation manner of the fourth aspect, in a second possible implementation, the first cache coherency processor is configured to perform cache coherency processing, and access the memory access The memory corresponding to the memory address information in the request is specifically:

The first cache coherency processor, if the memory corresponding to the memory address information is the first a memory on the host, configured to perform cache coherency processing, to access the memory of the first host, or the memory corresponding to the memory address information is other than the first host in the at least two hosts The memory on the other host is used for cache coherency processing, and the memory on the other host corresponding to the memory address information is accessed through the switching network.

With the second possible implementation of the fourth aspect, in a third possible implementation, the first cache coherency processor is configured to perform cache coherency processing, and access the memory by using the switching network. The memory on the other host corresponding to the address information is specifically:

The first cache coherency processor is configured to perform cache coherency processing, and communicate, by the switching network, with a cache coherency processor connected to the other host corresponding to the memory address information, and access the memory address. The memory on the other host corresponding to the information.

In combination with the second or third possible implementation of the fourth aspect, in a fourth possible implementation:

The first cache coherency processor, if the memory access request is a read memory instruction, is further configured to send a memory access result to a virtual machine manager of the first host.

In combination with the fourth aspect or any of the first to fourth possible implementations of the fourth aspect, in a fifth possible implementation:

The virtual machine manager of the first host is further configured to obtain the memory access request of the virtual machine, and determine, according to the memory address information in the memory access request, whether the memory that the memory access request needs to access is The memory on the first host, if it is the memory on the first host, accessing the memory on the first host according to the memory access request, and sending the cache status update information to the first a cache coherency processor; if not the memory on the first host, transmitting the memory access request to the first cache coherency processor.

The method, device, and system for memory sharing in the aggregate virtualization provided by the embodiment of the present invention, the memory processing command is sent to the cache coherency processor by the virtual machine manager of the host, and cached by the cache coherency processor. Consistency processing avoids the problem of occupying more processor resources caused by CC processing on the host in the aggregation virtualization, resulting in system performance degradation, thereby improving system processing performance and shortening memory access time. DRAWINGS In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a system architecture diagram of an aggregated virtualization application according to an embodiment of the present invention;

2 is a flowchart of a method for memory sharing in an aggregated virtualization according to Embodiment 1 of the present invention; FIG. 3 is a flowchart of a method for memory sharing in an aggregated virtualization according to Embodiment 2 of the present invention; FIG. 5 is a flowchart of a method for memory sharing in an aggregated virtualization according to Embodiment 4 of the present invention; FIG. 6 is a structural diagram of a cache coherency processor according to Embodiment 5 of the present invention;

7 is a structural diagram of a cache coherency processor according to Embodiment 6 of the present invention;

Figure 8 is a system diagram of a computer of Embodiment 7 of the present invention. The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, but not all embodiments. . All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without making creative labor are within the scope of the present invention.

1 is a system architecture diagram of an aggregated virtualization application according to an embodiment of the present invention. As shown in the figure, the system includes: multiple hosts, each processor on the host can support memory access sensitive instruction interception, and captures each host. All access to shared memory, and to ensure the correctness of the memory data. Each host's processor is interconnected by a high-speed peripheral component (Peripheral Component)

Interconnect Express (PCIE) interface, QuickPath Interconnect (QPI) interface or HyperTransport (ΗΤ) interface is connected to a cache coherency processor (CC processor); each host has Each of the independent Basic Input Output System (BIOS) runs the aggregate virtualization software. The aggregation virtualization software running on the host implements aggregation virtualization, so that multiple hosts can externally present one host, thereby establishing and running a large number of virtual machines on the aggregated virtualized device resource pool. The host in the system architecture applied in the embodiment of the present invention may be an ordinary computer or a mobile device. The mobile terminal, the workstation or the server, the dedicated server, and the like, such as an X86 processor, are not specifically limited in the present invention.

The system also includes a plurality of CC processors, and the CC processor can perform CC processing. One end of each CC processor is connected to a host processor, and can be connected through a PCIE interface, a QPI interface or an HT interface, and the other end is connected and exchanged. The internet. Preferably, the CC processor is a physical entity that is independent of the host.

The switching network interconnects multiple CC processors, so that each host can communicate through the CC processor. The switching network can be a PCIE switch, an Infiniband switch, or an Ethernet switch, and is processed by the PCIE interface, the Infiniband interface, or the Ethernet interface. Connected.

FIG. 2 is a flowchart of a method for memory sharing in aggregate virtualization according to Embodiment 1 of the present invention. As shown in the figure, this method is:

Step 101: The cache coherency processor receives a memory processing command sent by the host's virtual machine manager.

Aggregate virtualization presents the virtual machine as a contiguous memory address on the independent memory of each host. When the virtual machine on the host performs memory access, the virtual machine manager (Hyvistor) on the host intercepts the memory access of the virtual machine. The event, that is, the memory access request of the virtual machine is obtained, and the memory access request contains the memory address information to be accessed, and the memory read command or the memory write command. Preferably, the Distributed Shared Memory (DSM) interface in the virtual machine manager calls the PCIE to memory (PCIE to MEM) driver in the DomainO, and passes the PCIE port to the cache consistency according to the obtained memory access request. The processor sends a memory processing command, and the cache coherency processor receives the memory processing command. The PCIE port here refers to the port that communicates using the PCIE protocol. Of course, the virtual machine manager may also send a memory processing command to the cache coherency processor using a communication protocol port other than the PCIE port. The PCIE protocol is used as a general-purpose international standard. The use of the PCIE port can avoid the incompatible upgrade risk and cost caused by the proprietary protocol. For the convenience of description, the PCIE port is used for description in the embodiment of the present invention, and the present invention is not protected. The scope creates limits.

Preferably, the virtual machine manager of the host obtains a memory access request of the virtual machine, and first determines, according to the memory address information in the memory access request, whether the memory that the memory access request needs to access is the memory on the host, and if so, according to Memory access requests access memory on this machine: When writing instructions for memory, the virtual machine manager writes the contents to be written to the corresponding memory address, and sends the cache status update information to the cache coherency processor through the PC IE port, where the cache status is updated. The information includes the memory block address information and the Cache status information. The value of the Cache status information indicates what state the Cache is after the Cache writes the data, which may be: one of the Cache states such as exclusive, shared, invalid, etc.; When instructing, the virtual machine manager queries the cache coherency directory in the cache coherency processor, and reads the content to be accessed from the memory according to the Cache state information of the corresponding memory block in the CC directory. If the memory that needs to be accessed is not the memory on the host, the virtual machine's memory access request is sent to the cache coherency processor. The virtual machine manager of the host obtains the memory access request of the virtual machine, and does not judge, and directly sends the virtual machine memory access request to the cache coherency processor through the PC IE port. It can be seen that the memory processing command sent by the virtual machine manager on the host received by the cache coherency processor may be a memory access request of the virtual machine, or may be a Cache status update sent by the host virtual machine manager after performing a memory access. information.

Step 1 02: The cache consistency processor performs cache consistency processing according to the received memory processing command, specifically:

If the memory processing command is the Cache status update information sent by the host's virtual machine manager, the cache coherency processor updates the local cache coherency directory according to the Cache status update information. The Cache Consistency Directory records the Cache status of the shared memory in the entire system, and records the Cache status information and current copy information of the memory block. The Cache status information indicates the status of the local Cache, such as exclusive, shared, invalid, etc. status. The current copy information indicates which hosts have a copy of the memory block, and the cache coherency processor corresponding to the host has the information of the memory block in the local cache coherency directory. Each cache coherency processor maintains its own local cache coherency directory. When the memory state changes, the Cache state information of the cache coherency directory also needs to be refreshed: After the corresponding host performs a memory write operation, the cache coherency The processor needs to update the Cache state information of the memory block of the memory in the local cache coherency directory, and notifies the memory block in which the memory is saved according to the current copy information of the memory block in the cache coherency directory. The corresponding CC processor of the other hosts of the copy also refreshes their respective cache coherency directories. Here, the cache coherency processor updates the local cache coherency directory according to the received Cache status update information, which may be based on the cache shape. The memory block address information carried in the state update information (ie, the address information of the memory block in which the write operation is performed) and the Cache state information update the Cache state information of the memory block in which the write operation is performed in the cache coherency directory. First, the cache coherency processor determines the record of the memory block corresponding to the memory block address information in the local cache coherency directory according to the memory block address information in the cache status update information, and then updates the cache status information in the information according to the cache status. Updating the cache state information in the record of the memory block, and further, determining, according to the current copy information in the record of the memory block, another host that stores the copy of the memory block, and notifying the cache coherency processor corresponding to the other host Update their local cache coherency directories.

If the memory processing command is a memory access request of the virtual machine on the host, the cache coherency processor performs cache coherency processing, and accesses the memory corresponding to the memory address information in the memory access request. The memory corresponding to the memory address information herein refers to the memory on the host where the memory resource corresponding to the memory address information in the memory processing request is located. Specifically, if the memory corresponding to the memory address information to be accessed is the memory on the host, the cache consistency processor performs cache coherency processing, and accesses the memory of the host: if the memory access request is a write memory instruction, the cache is consistent The processor writes the content to the memory of the host, and the cache coherency processor notifies the Hyperv i sor to write the content into the local memory, or the cache coherency processor directly writes the content into the local memory, and Further, the cache coherency processor refreshes the Cache state information of the memory block corresponding to the write operation in the local CC directory; if the memory access request is a read memory instruction, the cache coherency processor according to the corresponding memory in the cache coherency directory The Cache Status information of the memory block notifies the host's virtual machine manager to perform a memory read, and the host's virtual machine manager sends the read information to the virtual machine that issued the memory access request. If the memory to be accessed is the memory on the other host, the cache coherency processor accesses the memory on the host where the memory corresponding to the memory address information of the memory processing request is accessed through the exchange network. For convenience of description, other hosts in which the memory corresponding to the memory address information is located may be referred to as a remote host, and a host that issues a memory access request is referred to as a local host. The switching network here may be a PCI E switch, an Inf iniband switch or an Ethernet switch, and the cache coherency processor corresponding to the local host communicates with the cache coherency processor corresponding to the remote host through the switching network, thereby realizing the remote end Access to memory on the host. If the memory access request is a write memory instruction, the cache coherency processor needs to refresh the Cache status information of the memory block corresponding to the memory in the local CC directory, and notify the remote host of the corresponding CC processor, and Need to write The content is written to the memory of the remote host; if the memory access request is a read memory instruction, the CC processor that issues the memory access request notifies the remote host of the corresponding CC processor to perform memory access, and the cache consistency processing corresponding to the remote host Receives the memory access result and sends it to the virtual machine manager of the local host that issued the memory access request, and the virtual machine manager sends the read information to the virtual machine that issues the memory access request, where the memory access result is the remote end. The corresponding cache coherency processor connected to the host reads from memory based on the memory access request and its local CC directory. Further technical details of the CC processing performed by the CC processor follow the general CC processing protocol of the industry, and will not be described herein.

The method for sharing memory in the aggregation virtualization provided by the embodiment of the present invention receives the memory processing command sent by the Hyperv i sor of the host by the cache consistency processor, and the cache consistency processing is performed by the cache consistency processor according to the memory processing command, thereby avoiding The problem of occupying more processor resources caused by CC processing in the aggregation virtualization by the software on the host, causing system performance degradation, thereby improving system processing performance and shortening memory access time.

FIG. 3 is a flowchart of a method for memory sharing in aggregate virtualization according to Embodiment 2 of the present invention. As shown in the figure, this method is:

Step 201: The virtual machine manager of the host obtains a memory access request of the virtual machine.

When a virtual machine on the host performs a memory access, the Hyperv i sor on the host intercepts the memory access event of the virtual machine, that is, obtains the memory access request of the virtual machine.

Step 202: The virtual machine manager of the host sends a memory processing command to the cache coherency processor, so that the cache coherency processor performs cache coherency processing according to the received memory processing command.

Specifically, the virtual machine manager of the host obtains the memory access request of the virtual machine, and may first determine, according to the memory address information in the memory access request, whether the memory that the memory access request needs to access is the local memory on the host: If yes, Accessing the local memory on the local device according to the memory access request, when writing the instruction for the memory, writing the content to be written to the corresponding memory address, and sending the cache status update information to the cache coherency processor, so as to The cache coherency processor updates the local cache coherency directory according to the received cache state update information, where the cache state update information includes the memory block address information and the Cache state information; when the memory read command, the virtual machine management Query the cache coherency directory in the cache coherency processor, and read the content to be accessed from the cache according to the Cache state information of the corresponding memory block in the CC directory. If the memory that needs to be accessed is not the memory on the host, send the virtual machine's memory access request to the cache. The consistency processor, in order to cache the consistency processor for cache coherency processing and access the memory corresponding to the memory address information in the memory access request. The virtual machine manager of the host obtains the memory access request of the virtual machine, does not perform the judgment of the memory address information, and directly sends the memory access request of the virtual machine to the cache consistency processor, so that the cache consistency processor performs the same. Cache coherency processing and accessing the memory corresponding to the memory address information in the memory access request, specifically, the cache coherency processor performs the cache coherency processing and accesses the memory corresponding to the memory address information in the memory access request and the embodiment 1 Similar in the matter, we will not repeat them here. According to the foregoing description, the memory processing command sent by the host's virtual machine manager to the cache coherency processor may be a virtual machine's memory access request, or may be a cache state information after the host's virtual machine manager performs a memory access.

Preferably, the DSM interface in the host's virtual machine manager invokes the PCI E to MEM driver in the Doma inO, and sends a memory processing command to the cache coherency processor through the PCI E port according to the obtained memory access request. The host's virtual machine manager communicates with the cache coherency processor through the PCI E port. The PC IE port can avoid the risk and cost of incompatible upgrades caused by the proprietary protocol. Of course, other communication protocol ports can also be used.

Further, if the memory access request is a read memory instruction, the host virtual machine manager receives the memory access result returned by the cache coherency processor and sends the result to the virtual machine that issues the memory access request.

The method for sharing memory in the aggregation virtualization provided by the embodiment of the present invention sends a memory processing command to the cache coherency processor through the Hyperv i sor of the host, so that the CPU is processed by the cache coherency processor, thereby avoiding aggregation virtualization. The CPU processing on the host implements CPU processing, which causes more processor resources and causes system performance degradation. This improves system processing performance and shortens memory access time.

4 is a flowchart of a method for memory sharing in an aggregated virtualization according to Embodiment 3 of the present invention. As shown in the figure, the method is specifically as follows:

Step 301: A virtual machine on the host initiates a memory access event. Aggregation virtualization presents the virtual machine as a contiguous memory address for the independent memory on each host. When the virtual machine on the host needs to access the memory, it initiates a memory access event.

Step 302: The virtual machine manager on the host intercepts the memory access event. In aggregate virtualization, in order to ensure the correctness of memory data, memory access sensitive instructions must be captured. Hyperv i sor Intercept the memory access event of the virtual machine, that is, obtain the memory access request of the virtual machine.

Step 303: Hyper V i s or determine whether the memory access request is accessing the memory on the host. The Hyperv i sor determines whether the memory that the memory access request needs to access is the memory on the host according to the memory address information in the memory access request. Specifically, the DSM interface in the Hyperv i sor processes the obtained memory access request, and determines whether to access the memory on the host according to the memory address information in the memory access request.

Step 304: If the memory on the host is accessed, the Hyperv i sor of the host accesses the memory on the host according to the memory address information in the memory access request.

Step 305: When writing an instruction for the memory, the host's Hyperv i sor sends the cache status update information to the local cache coherency processor, where the cache status update information includes the memory block address information and the Cache status information, and the value of the Cache status information. Indicates the state of the Cache after the data is written. It can be: one of the Cache states such as exclusive, shared, and invalid. This step is specifically: when the memory is written, the host virtual machine manager writes the memory, and the DSM interface in the virtual machine manager calls the PC IE to MEM driver in the Doma inO, through the PC IE port. The local cache coherency processor sends the cache status update information, and the input and output (Input Out put, 10 for short) interface unit in the local cache coherency processor receives the cache status update information. In this embodiment, for convenience of distinction, the cache coherency processor corresponding to the host that issues the memory request command is referred to as a local cache coherency processor, and the cache coherency processor corresponding to the remote host where the memory to be accessed is located. Cache-consistent processor

Step 306: The local cache coherency processor updates its own cache coherency directory according to the received Cache status update information. Specifically, the local proxy (Loca Proxy, LP) sub-module in the local cache coherency processor is responsible for updating the local CC directory according to the memory block address information and the Cache state information carried in the Cache status update information of the received host. , that is, updating the Cache state information of the memory block of the memory that is written in the local cache coherency directory, and further notifying the cached memory according to the current copy information of the memory block of the memory in the cache coherency directory The CC processor corresponding to the other host of the copy of the memory block also refreshes the respective local cache coherency directory. Specifically, first, the cache coherency processor determines, according to the memory block address information in the cache status update information, a record of the memory block corresponding to the memory block address information in the local cache coherency directory, and then updates the information according to the cache status. Cache status information is more The cache state information in the record of the memory block is newly added, and further, according to the current copy information in the record of the block, another host that saves the copy of the memory block is determined, and the cache consistency processing corresponding to the other host is notified. Updates their respective local cache coherency directories. Go to step 315.

Step 307: If the memory on the host is not accessed, the DSM interface in the host virtual machine manager calls the PC IE to MEM driver in the Doma inO, and sends a memory access request to the local cache coherency processor through the PC IE port. . The 10 interface unit responsible for the interface with the host side in the cache coherency processor receives the memory access request.

Step 308: The local cache coherency processor accesses the remote cache coherency processor through the switched network. After receiving the memory access request, the local cache coherency processor hands over the memory access request that needs to access the memory on the other host to the remote proxy (Remo te Proxy, RP for short) sub-module in the cache coherency processor. The submodule accesses the remote cache coherency processor through the switching network through the network interface unit. The remote cache coherency processor here refers to the CC processor responsible for managing the remote host, which is the host where the memory to be accessed is located.

Step 309: After receiving the memory access request, the remote cache coherency processor hands the memory access request to the local proxy sub-module for processing.

Step 31 0: The local proxy submodule of the remote cache coherency processor determines whether its local CC directory hits. The local proxy submodule of the remote cache coherency processor queries its local CC directory according to the memory address of the memory access request, and determines whether the Cache state of the memory block of the memory to be accessed is readable, and if it is in a readable state, That is, the local Cache directory hits, the Cache is available, otherwise it is a miss, and the Cache is unavailable.

Step 31: If the CC directory does not hit, the local proxy submodule in the remote cache coherency processor requests the remote host to perform memory access through the 10 interface module that interfaces with the host. The remote cache coherency processor sends a request to the remote host to access the memory of the memory address in the memory access request: for the read instruction, obtain the content of the memory address in the memory access request, and write the content to be written for the write instruction Host memory address.

Step 312: The remote cache coherency processor updates its local CC directory. The remote cache coherency processor updates the Cache status information of the memory block corresponding to the memory in the local CC directory corresponding to the memory read operation or the write operation, and writes the content of the current memory read and write to the cache, and updates CC directory for subsequent memory access. Step 313: If the CC directory hits, for the read command, the remote cache coherency processor directly reads the corresponding memory value from the Cache to obtain a memory access result. If it is a write instruction, the remote cache coherency processor writes the value to be written to the memory of the remote host, updating the local cache.

Step 314: For the read instruction, the remote cache coherency processor returns the obtained memory access result to the local cache coherency processor. The remote cache coherency processor returns the content of the read memory to the local cache coherency processor through the network interface unit through the switching network, and the local cache coherency processor updates the Cache state in the CC directory.

Step 315: For the read instruction, the local cache coherency processor returns the memory access result to the virtual machine that initiated the memory access event. The local cache coherency processor receives the memory access result returned by the remote cache coherency processor, and feeds the memory access result to the host's Doma in 0 through the 10-interface unit responsible for the interface with the host, and the feedback is processed by Doma in 0. Give the host

Hyperv i sor , and ultimately returned to the VM that initiated the memory access event.

The method for sharing memory in the aggregation virtualization provided by the embodiment of the present invention sends the memory processing command to the cache coherency processor through the Hyperv i sor of the host, and performs CC processing by the cache coherency processor, thereby avoiding aggregation virtualization. The CPU processing on the host implements CPU processing, which causes more processor resources and causes system performance degradation. This improves system processing performance and shortens memory access time.

FIG. 5 is a flowchart of a method for memory sharing in an aggregated virtualization according to Embodiment 4 of the present invention. As shown in the figure, the method is specifically as follows:

The steps 401-402 are the same as the steps 301-302 of the embodiment 3 of the present invention, and are not described here.

Step 403: The DSM interface in the host virtual machine manager invokes the PC IE to MEM driver in the Doma inO, and sends a memory access request to the local cache coherency processor through the PCI E port. The 10 interface unit responsible for interfacing with the host in the cache coherency processor receives the memory access request.

Step 404: The local cache coherency processor determines whether the memory access request is accessing the memory on the host. The local cache coherency processor receives the memory access request and determines whether to access the memory on the host according to the memory address information in the memory access request.

Step 405, if the memory on the host is accessed, the local cache coherency processor will store the memory. The local proxy submodule to which the access request is handed over is processed.

Step 406: The local proxy sub-module of the local cache coherency processor determines whether the local CC directory is hit. The local proxy sub-module queries its local CC directory, queries the local CC directory according to the memory address of the memory access request, and determines whether the Cache state of the memory block of the memory to be accessed is readable. If it is in a readable state, it indicates local. The Cache directory hits, the Cache is available, otherwise it is a miss.

Step 407: If the CC directory does not hit, the local cache coherency processor requests the host to perform memory access. The cache coherency processor sends a request to the host to access the memory of the memory address in the memory access request to obtain the memory access result.

Step 408: The local cache coherency processor updates its local CC directory according to the memory access result. The local cache coherency processor writes the content to the host's memory and flushes the Cache status information of the corresponding memory block in the local CC directory.

Step 409: If the CC directory hits, the local cache coherency processor directly performs cache access, obtains a memory access result for the read command, writes the content to the host memory for the write command, and updates the content in the original cache. .

Step 410: If the memory on the host is not accessed, the local cache coherency processor accesses the remote cache coherency processor through the switched network. The local cache coherency processor handles the remote proxy sub-module to which the memory access request for accessing the memory on other hosts is handled. The RP sub-module accesses the remote cache coherency processor through the switching network through the network interface unit. The remote cache coherency processor here refers to the CC processor responsible for managing the remote host, which is the host where the memory access request is to be accessed. In this embodiment, for convenience of distinction, the cache coherency processor corresponding to the host that issues the memory request command is referred to as a local cache coherency processor, and the cache coherency corresponding to the remote host where the memory to be accessed is located is processed. This is called the remote cache coherency processor.

411 ~ 417, specific implementation technical solutions and steps 309 ~ 315 of Embodiment 3 of the present invention

The method for sharing memory in the aggregation virtualization provided by the embodiment of the present invention sends a memory processing command to the cache coherency processor through the host hypervisor, and performs CC processing by the cache coherency processor, thereby avoiding the host in the aggregation virtualization process. Caused by CC processing through software It takes up more processor resources and causes system performance degradation, which can improve system processing performance and shorten memory access time.

FIG. 6 is a structural diagram of a cache coherency processor according to Embodiment 5 of the present invention, as shown in FIG. 6. The cache coherency processor 50 includes an input/output unit (referred to as 10 units) 51 and a directory management unit 52, and the cache is consistent. Sex processing unit 53. among them,

10 unit 51, used to receive the memory processing command sent by the host's virtual machine manager. The 10 unit provides an interface for the cache coherency processing unit to interact with the host. Its main function is to complete communication between the cache coherency processing unit and the host (specifically, the central processor in the host). When the virtual machine on the host performs memory access, the Hyperv i sor on the host intercepts the memory access event of the virtual machine, that is, obtains the memory access request of the virtual machine, and the memory access request includes the memory address information to be accessed, which may be Memory read instruction or memory write instruction. Preferably, the virtual machine manager sends a memory processing command to the 10 units in the cache coherency processor through the PCI E port according to the obtained memory access request, and the 10 unit receives the memory processing command. The PC IE port here refers to the port that uses the PCIE protocol for communication. Of course, the virtual machine manager may also send memory processing commands to 10 units using other communication protocol ports other than the PC IE port. The PCI E protocol is a more general international. In the standard, the use of the PC IE port in the 10th unit can avoid the risk of the incompatible upgrade caused by the proprietary protocol. For the convenience of description, the description is made by using the PC IE port in the embodiment of the present invention, which does not limit the protection scope of the present invention.

The cache consistency processing unit 53 is configured to perform cache consistency processing according to the memory processing command received by the 10 unit 51, and if the received memory processing command is the Cache status update information sent by the host virtual machine manager, the cache consistency is performed. The processing unit is configured to send a cache consistent directory update command to the directory management unit 52 to update the local cache consistent directory according to the Cache status update information; if the received memory processing command is a memory access request of the virtual machine on the host The cache coherency processing unit 53 is configured to perform cache coherency processing, and access the memory corresponding to the memory address information in the memory access request, where the memory corresponding to the memory address information refers to the memory corresponding to the memory address information in the memory processing request. The memory on the host where the resource is located.

The directory management unit 52 is configured to update the local cache coherency directory according to the cache coherency directory update instruction of the cache coherency processing unit 53. The cache consistency directory records the Cache status of the shared memory in the entire system, and records the Cache status information of the memory block of the memory and when Pre-copy information, where the Cache status information indicates the status of the local Cache, such as exclusive, shared, invalid, and so on. The current copy information indicates which hosts have a copy of the memory block, and the cache coherency processor corresponding to the host has the information of the memory block in the local cache coherency directory. The directory management unit of each cache coherency processor is used to maintain its own local cache coherency directory. When the memory state changes, the Cache state information of the cache coherency directory also needs to be refreshed, for example, in the corresponding host. After the memory write operation is performed, the directory management unit is used to update the Cache status information of the memory block of the memory in the local cache coherency directory that has been written. Here, the directory management unit is configured to update the cache state information of the memory block in the cache consistency directory according to the memory block address information and the Cache state information in the cache consistency directory update instruction. Specifically, the directory management unit is configured to determine, according to the memory block address information, a record of the memory block corresponding to the memory block address information in the local cache coherency directory, and update the record of the memory block according to the cache status information in the cache status update information. The cache state information in the cache, and according to the current copy information in the record of the memory block, determine other hosts that hold the copy of the memory block, and notify the cache coherency processors corresponding to other hosts to update their respective local cache coherency directories.

Preferably, when the memory processing command is a memory access request of the virtual machine, the cache coherency processing unit 53 is configured to perform cache coherency processing, and access the memory corresponding to the memory address information in the memory access request, specifically: if access is required The memory corresponding to the memory address information is the memory on the host, used for cache coherency processing, and accesses the memory of the host: If the memory access request is a write memory instruction, the cache coherency processing unit is used to write the content into the host. The corresponding memory on the host can be notified by the cache coherency processing unit through 10 units to capture the memory of the local writer, or the cache coherency processing unit directly writes the content into the memory of the host through 10 units. Further, the cache consistency processing unit is further configured to send a cache consistency directory update instruction to notify the directory management unit to refresh the Cache state information of the memory block corresponding to the memory in the local CC directory corresponding to the write operation. a directory management unit, configured to notify, according to the received cache consistency directory update instruction, the Cache status information of the memory block corresponding to the memory in the local CC directory corresponding to the write operation; if the memory access request is a read memory instruction, the cache consistency processing The unit is configured to notify the host's virtual machine manager of the memory reading according to the Cache status information of the corresponding memory block in the cache coherency directory, and the host virtual machine manager sends the read information to the issuing memory. Access the requested virtual machine. If the memory that needs to be accessed is memory on another host, then The cache coherency processing unit is configured to perform cache coherency processing, and access the memory on the host where the memory corresponding to the memory address information of the memory processing request is accessed by the network interface unit 54 via the switching network. At this time, the cache coherency processor 50 further includes a network interface unit 54 for providing communication between the cache coherency processing unit and other cache coherency processors, and transmitting the information of the cache coherency processing unit to the exchange network. Other cache coherency processors pass information from other cache coherency processors received from the switched network to the cache coherency processing unit. The switching network here may be a PCI E switch, an Inf iniband switch, or an Ethernet switch. The cache coherency processor 50 communicates by using a cache coherency processor connected to the host where the memory corresponding to the memory address information is exchanged. The access of the memory on the host where the memory corresponding to the memory address information is located, specifically, the cache consistency processing unit is configured to perform cache consistency processing, and the network interface unit corresponds to the memory address information through the switching network. The cache coherency processor connected to the other host communicates to access the memory on the other host corresponding to the memory address information. For convenience of description, other hosts in which the memory corresponding to the memory address information is located may be referred to as a remote host, and a host that issues a memory access request is referred to as a local host. If the memory access request is a write memory instruction, the cache coherency processing unit needs to notify the directory management unit to refresh the Cache state information of the memory block corresponding to the memory in the local CC directory corresponding to the write operation, and notify the remote host correspondingly through the 10 unit. The CC processor writes the content to be written to the memory of the remote host. If the memory access request is a read memory instruction, the cache coherency processing unit that issues the memory access request is further used to notify the remote host of the corresponding CC processor to perform memory. Accessing, and receiving a memory access result from a cache coherency processor connected to the remote host, and sending the result to the virtual machine manager of the host that issued the memory access request, and the virtual machine manager sends the read information to the memory access The requested virtual machine, wherein the memory access result is that the cache coherency processing of the remote host is read from the memory according to the memory access request and its local CC directory. Further technical details of CC processing follow the industry-wide CC processing protocol, and will not be repeated here.

Further, the directory management unit is configured to update the Cache state information of the memory block of the memory in the local cache coherency directory according to the received cache coherency directory update instruction, and according to the cache coherency directory The current copy information of the memory block of the memory notifies that the CC processor corresponding to the other host that caches the copy of the memory block of the memory also refreshes the local cache coherency directory, and may send a message to the cache coherency processing unit. Connected via the network The port unit sends relevant messages to other CC processors.

Preferably, the virtual machine manager of the host obtains a memory access request of the virtual machine, and first determines, according to the memory address information in the memory access request, whether the memory that the memory access request needs to access is the memory on the host, and if so, according to The memory access request accesses the memory on the local device: When writing the instruction for the memory, the virtual machine manager writes the content to be written to the corresponding memory address, and sends the cache status update information to the cache consistency processing through the PC IE port. 10 units in the device, wherein the cache status update information includes memory block address information and Cache status information, and the value of the Cache status information indicates what state the Cache is after writing the data, which may be: exclusive, shared, invalid, etc. One of the following; when reading instructions for memory, the virtual machine manager queries the cache coherency directory in the directory management unit in the cache coherency processor through the 10-unit, cache coherency processing unit, according to the corresponding memory in the CC directory. Cache status information of the memory block is read from the memory to be accessed. Content. If the memory to be accessed is not the memory on the host, the virtual machine's memory access request is sent to the cache coherency processing unit through 10 units. It can also be processed as follows. After the virtual machine manager of the host obtains the memory access request of the virtual machine, the memory access request of the virtual machine is directly sent to the cache coherency processor through the PC I E port through the PC I E port. It can be seen that the memory processing command sent by the virtual machine manager on the host received by the cache unit of the cache coherency processor may be a memory access request of the virtual machine, or may be a cache after the memory access of the host virtual machine manager. Status update information.

The cache coherency processor provided by the embodiment of the present invention receives the memory processing command sent by the host's Hyperv i sor, performs cache coherency processing according to the memory processing command, and avoids implementing CC processing in the aggregate virtualization by software on the host. As a result, it takes up more processor resources and causes system performance degradation, which can improve system processing performance and shorten memory access time.

FIG. 7 is a structural diagram of a cache coherency processor according to Embodiment 6 of the present invention. On the basis of the CC processor of the embodiment 5 shown in FIG. 6, the cache coherency processing unit 53 of the embodiment of the present invention includes:

The pre-processing sub-module 530 is configured to be connected to the 10-unit, the local proxy sub-module 531, and the remote proxy sub-module 532, and is responsible for packet transmission between the 10-unit and the local proxy sub-module and the remote proxy sub-module, and receives 10 units. The sent information is forwarded to the local proxy submodule or the remote proxy submodule, and the information sent by the local proxy submodule or the remote proxy submodule is received and forwarded to the 10 unit. The local proxy submodule 5 31 is configured to process a memory access request to the host. Specifically, the method is configured to perform cache consistency processing according to the memory processing command sent by the 10 units received by the preprocessing submodule, and if the received memory processing command is the Cache status update information sent by the virtual machine manager of the host, according to the Cache Status update information, the send cache coherency directory update command to the directory management unit 52 to update the local cache coherency directory; if the received memory processing command is a memory access request of the virtual machine on the host, and the memory access request here The memory corresponding to the memory address information is the memory on the host, and the local proxy sub-module is used for cache coherency processing to access the memory of the host: If the memory access request is a write memory instruction, the local proxy sub-module is used The content is written into the corresponding memory on the host, and the content of the Hyperv i sor can be written to the local memory through the pre-processing sub-module via the 10-unit unit, or the content can be directly directly processed by the local proxy sub-module through the pre-processing sub-module through 10 units. Write to the host's memory, and further, the local proxy submodule, For transmitting a directory update instruction cache coherency directory managing unit notifies the refresh local directory corresponding CC were Cache memory state information of memory block write operation. If the memory access request is a read memory instruction, the local proxy sub-module is configured to notify the host's virtual machine manager of the memory read by the pre-processing sub-module according to the Cache state information of the corresponding memory block in the cache coherency directory. The read information is sent by the host's virtual machine manager to the virtual machine that issued the memory access request. Of course, the local proxy sub-module can also receive the memory access request of other hosts transmitted by the network interface unit 54, and the memory corresponding to the memory address information in the memory access request is the memory on the host, and the local proxy sub-module is used according to other The host's memory access request is cache-consistent and accesses the host's memory.

The remote proxy submodule 5 32 is configured to process a memory access request to other hosts. If the received memory processing command sent by the 10 units sent by the preprocessing module is a memory access request of the virtual machine on the host, and the memory corresponding to the memory address information in the memory access request is the memory on the other host, then the far The end proxy sub-module performs cache coherency processing, accesses the memory on the host where the memory corresponding to the memory address information of the memory processing request is accessed through the network interface unit 54, and transfers the information of other hosts received from the switching network to the pre-processing Submodule. Further technical details of CC processing follow the industry-wide CC processing protocol, and will not be repeated here. The implementation details of the functions of the parts of the cache coherency processor are the same as those of the previous embodiment 1 to 5. The description of the previous embodiments can be referred to, and details are not described herein again. The cache coherency processor provided by the embodiment of the present invention receives the memory processing command sent by the Hypervi sor of the host, and performs cache coherency processing according to the memory processing command, thereby avoiding the CC processing in the aggregate virtualization by the software on the host. Occupy more processor resources, causing system performance degradation, which can improve system processing performance, shorten memory access time, and handle local memory access and remote memory access through local proxy sub-modules and remote proxy sub-modules, respectively. Further improve the processing performance of the processor.

8 is a computer system diagram of Embodiment 7 of the present invention. As shown, the computer system includes: at least two hosts, at least two cache coherency processors, and a switching network, wherein the at least two hosts are Each host is connected to a cache coherency processor of the at least two cache coherency processors, respectively, and the at least two cache coherency processors are connected by a switched network communication.

The first host of the at least two hosts is configured to send a memory processing command to the first one of the at least two CC processors that are connected. Preferably, when the virtual machine on the first host performs a memory access, the Hyperv i sor on the first host intercepts a memory access event of the virtual machine, that is, obtains a memory access request of the virtual machine, and the memory access request includes accessing The memory address information may be a memory read command or a memory write command, and the first host sends a memory processing command to the first cache coherency processor connected thereto through the PCI E port. Of course, the first host may also send a memory processing command to the first cache coherency processor by using a communication protocol port other than the PCI E port. The PC IE protocol is a relatively common international standard, and the PC IE port can be used to avoid private use. The incompatibility upgrade risk and cost brought by the protocol are described in the embodiment of the present invention by using the PCI E port for convenience of description, and do not limit the protection scope of the present invention. It should be noted that the "first host" and the "first cache coherency processor" described in the embodiments of the present invention are only for convenience of description, and represent multiple hosts or multiple cache coherency processors. An unspecified host or cache coherency processor, not a special host or CC processor.

The first cache coherency processor is configured to perform cache coherency processing according to the received memory processing command, where: if the memory processing command is the Cache status update information sent by the virtual machine manager of the first host, A cache coherency processor is used to update the local cache coherency directory according to the Cache status update information. The Cache Consistency Directory records the Cache status of the shared memory in the entire system, and records the Cache status information and current copy information of the memory block. The Cache status information indicates the status of the local Cache, such as exclusive, shared, Invalid state. The current copy information indicates which hosts have a copy of the memory block. The first cache coherency processor is configured to update the local cache coherency directory according to the received Cache status update information, and specifically may be the memory block address information carried in the update information according to the Cache status (ie, the memory block that has been written) And Cache status information, updating the Cache status information of the memory block in the cache coherency directory. Further, the first cache coherency processor is further configured to notify, according to current copy information of the memory block of the memory in the cache coherency directory, CC processing of other hosts in the at least one host that have a copy of the memory block in which the memory is cached. The device also refreshes its local cache coherency directory. Specifically, the first cache consistency processor is configured to determine, according to the memory block address information, a record of the memory block corresponding to the memory block address information in the local cache coherency directory, and update the cache status information in the information according to the cache status. Updating the cache state information in the record of the memory block, and determining, according to the current copy information in the record of the memory block, another host other than the first host of the at least two hosts storing the copy of the memory block, notifying other The cache coherency processor corresponding to the host updates its own local cache coherency directory.

Preferably, the virtual machine manager of the first host obtains a memory access request of the virtual machine, and may first determine, according to the memory address information in the memory access request, whether the memory that the memory access request needs to access is the memory on the host, and if so, Accessing the memory on the local device according to the memory access request: When writing the instruction for the memory, the virtual machine manager of the first host is used to write the content to be written to the corresponding memory address, and the cache status update information is cached. The Cache status update information includes the memory block address information and the Cache status information, where the value of the Cache status information indicates the status of the Cache after the data is written, which may be: One of Cache states: exclusive, shared, invalid, etc.; when reading instructions in memory, the virtual machine manager of the first host queries the cache coherency directory in the first cache coherency processor, according to the corresponding memory in the CC directory The Cache status information of the memory block reads the content to be accessed from the memory. If the memory to be accessed is not the memory on the host, the first host is used to send the virtual machine's memory access request to the first cache coherency processor. Alternatively, after the virtual machine manager of the first host obtains the memory access request of the virtual machine, the virtual machine manager sends the memory access request of the virtual machine to the first cache coherency processor directly through the PC I E port.

If the memory processing command received by the first cache coherency processor is a memory access request of the virtual machine on the host, the first cache coherency processor is configured to perform cache coherency processing, and access the memory access Ask the memory corresponding to the memory address information in the request. The memory corresponding to the memory address information herein refers to the memory on the host where the memory resource corresponding to the memory address information in the memory processing request is located. Specifically, if the memory corresponding to the memory address information to be accessed is the memory on the first host, the first cache coherency processor performs cache coherency processing to access the memory on the first host: if the memory access request is a write a memory instruction, the first cache coherency processor writes the content to the memory of the first host, and the first cache coherency processor notifies the first host of the Hyperv i sor to write the content into the local memory, or by the first The cache coherency processor directly writes the content to the memory of the first host, and further, the first cache coherency processor refreshes the Cache state information of the memory block corresponding to the memory in the local CC directory corresponding to the write operation. If the memory access request is a read memory instruction, the first cache coherency processor notifies the first host's virtual machine manager to perform memory read according to the Cache state information of the corresponding memory block in the cache coherency directory, and is configured by the first host The virtual machine manager sends the read information to the virtual machine that issued the memory access request. If the memory to be accessed is the memory on the host other than the first host, the first cache coherency processor accesses the memory on the other host where the memory corresponding to the memory address information of the memory processing request is accessed through the exchange network. The switching network here may be a PCI E switch, an Inf iniband switch or an Ethernet switch, and the first cache coherency processor communicates by using a cache coherency processor connected to another host where the memory corresponding to the memory address information is exchanged, Access to memory on other hosts where the memory corresponding to the memory address information is located. If the memory access request is a write memory instruction, the first cache coherency processor is configured to refresh the Cache state information of the memory block corresponding to the memory in the local CC directory, and notify the other host where the memory corresponding to the memory address information is located. The corresponding CC processor writes the content to be written to the cache of the other host. If the memory access request is a read memory instruction, the first cache coherency processor that issues the memory access request notifies the memory corresponding to the memory address information. The CC processor corresponding to the other host performs memory access, receives the memory access result from the cache coherency processor connected to the other host, and sends the result to the virtual machine manager of the first host that issues the memory access request, by the virtual machine The manager sends the read information to the virtual machine that issued the memory access request, wherein the memory access result is that the cache coherency processor connected to the other host reads from the memory according to the memory access request and its local CC directory. In the embodiment of the present invention, further technical details of the CC processing performed by the CC processor follow the CC processing protocol generally used in the industry, and details are not described herein again. The cache coherency processor in this embodiment may be implemented in accordance with the present invention. The cache coherency processor described in Embodiment 5 and Embodiment 6 is not described herein again. The computer system provided by the embodiment of the present invention sends a memory processing command to a cache coherency processor through a Hyperv i sor of the host, and the cache coherency processor performs cache coherency processing according to the memory processing command, thereby avoiding passing the software on the host. The CPU processing in the aggregation virtualization process occupies more processor resources and causes system performance degradation, thereby improving system processing performance and shortening memory access time.

From the description of the above embodiments, it will be apparent to those skilled in the art that the present invention can be implemented in hardware, or firmware implementation, or a combination thereof. When implemented in software, the functions described above may be stored in or transmitted as one or more instructions or code on a computer readable medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage medium may be any available media that can be accessed by a computer. By way of example and not limitation, the computer readable medium can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used to carry or store an instruction or data structure. The desired program code and any other medium that can be accessed by the computer. This evening. Any connection may suitably be a computer readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwaves are included in the fixing of the associated media. As used in the present invention, a disc (D i sk ) and a disc (CD) include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disc, and a Blu-ray disc, wherein the disc is usually magnetically replicated, The disc uses a laser to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

In summary, the above description is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalents, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

Rights request

1. A method for memory sharing in aggregate virtualization, including:

The cache consistency processor receives a memory processing command sent by the virtual machine manager of the host; if the memory processing command is cache status update information, the cache consistency processor performs local cache consistency processing based on the cache status update information. The directory is updated, and the cache status update information includes memory block address information and cache status information;

Alternatively, if the memory processing command is a memory access request of a virtual machine on the host, the cache consistency processor performs cache consistency processing and accesses the memory corresponding to the memory address information in the memory access request.

2. The method according to claim 1, characterized in that, the cache consistency processor updates the local cache consistency directory according to the cache status update information, specifically: the cache consistency processor updates the local cache consistency directory according to the cache status update information. The memory block address information determines the memory block record corresponding to the memory block address information in the local cache consistency directory;

Update the cache status information in the record of the memory block according to the cache status information in the cache status update information;

According to the current copy information in the record of the memory block, other hosts that store copies of the memory block are determined, and the corresponding cache consistency processors of the other hosts are notified to update their respective local cache consistency directories.

3. The method according to claim 1 or 2, characterized in that the cache consistency processor performs cache consistency processing and accesses the memory corresponding to the memory address information in the memory access request, specifically:

If the memory corresponding to the memory address information is the memory on the host, the cache consistency processor performs cache consistency processing and accesses the memory of the host;

Alternatively, if the memory corresponding to the memory address information is a memory on a host other than the host, the cache consistency processor performs cache consistency processing and accesses the memory address corresponding to the memory address information through a switching network. memory on other hosts.

4. The method according to claim 3, wherein the cache consistency processor accesses the memory on the other host corresponding to the memory address information through a switching network, specifically: The cache consistency processor communicates with the cache consistency processor connected to the other host through the switching network, and accesses the other memory address corresponding to the memory address information through the cache consistency processor connected to the other host. memory on the host.

5. The method according to claim 3 or 4, further comprising:

If the memory access request is a read memory instruction, the cache consistency processor sends the memory access result to the virtual machine manager of the host.

6. The method according to any one of claims 1 to 5, characterized in that, before the cache coherence processor receives the memory processing command sent by the virtual machine manager of the host, it further includes: virtual machine management of the host The virtual machine manager of the host obtains the memory access request of the virtual machine; and the virtual machine manager of the host determines whether the memory that needs to be accessed by the memory access request is the memory on the host based on the memory address information in the memory access request. , if it is the memory on the host, access the memory on the host according to the memory access request, and send the cache status update information to the cache consistency processor; if it is not on the host memory, the memory access request is sent to the cache coherence processor.

7. A method for memory sharing in aggregate virtualization, including:

The host's virtual machine manager obtains the virtual machine's memory access request;

The virtual machine manager of the host determines whether the memory that needs to be accessed by the memory access request is the memory on the host based on the memory address information in the memory access request. If it is the memory on the host, then based on the The memory access request accesses the memory on the host, and when the memory access request is a memory write instruction, cache status update information is sent to the cache consistency processor so that the cache consistency processor updates the cache consistency The cache status information corresponding to the memory block that has been written in the local cache consistency directory of the processor; if the memory access request is a read instruction, the memory access request is sent to the cache consistency processor, so that The cache consistency processor performs cache consistency processing and accesses the memory corresponding to the memory address information in the memory access request;

Alternatively, the virtual machine manager of the host sends the memory access request to the cache consistency processor, so that the cache consistency processor performs cache consistency processing and accesses the memory address in the memory access request. The memory corresponding to the information.

8. The method according to claim 7, characterized in that, if the memory access request is a read instruction, the virtual machine manager of the host sends the memory access request to the cache. After the consistency processor, it also includes:

The virtual machine manager of the host receives the memory access results returned by the cache coherence processor.

9. A cache coherence processor, characterized by including:

The input and output unit is used to receive the memory processing command sent by the virtual machine manager of the host; the cache consistency processing unit, if the memory processing command is cache status update information, is used to send cache consistency according to the cache status update information. A directory update instruction is given to the directory management unit, where the cache status update information includes memory block address information and cache status information, or the memory processing command is a memory access request of a virtual machine on the host, for Perform cache consistency processing and access the memory corresponding to the memory address information in the memory access request; The directory management unit is used to update the local cache consistency directory according to the cache consistency directory update instruction.

10. The cache consistency processor according to claim 9, characterized in that: the directory management unit is used to update the local cache consistency directory according to the cache consistency directory update instruction, specifically:

The directory management unit is configured to determine the memory block record corresponding to the memory block address information in the local cache consistency directory according to the memory block address information, and update the cache status in the information according to the cache status. The information updates the cache status information in the record of the memory block, and determines other hosts that store copies of the memory block based on the current copy information in the record of the memory block, and notifies the other hosts that the corresponding caches are consistent The processors update their local cache coherency directories.

11. The cache consistency processor according to claim 9 or 10, characterized in that the cache consistency processing unit is used to perform cache consistency processing and access the memory address information in the memory access request. The corresponding memory is specifically:

The cache consistency processing unit, if the memory corresponding to the memory address information is the memory on the host, is used to perform cache consistency processing and access the memory of the host. If the memory address information corresponds to If the memory is a memory on a host other than the host, the cache consistency processing unit is used to perform cache consistency processing, and accesses the memory on the other host corresponding to the memory address information through the network interface unit through the switching network. Memory;

Then, the cache consistency processor also includes: The network interface unit is used to provide communication between the cache consistency processing unit and other cache consistency processors, and send the information of the cache consistency processing unit to the other cache consistency processors through the switching network. The processor is configured to pass information about the other cache coherence processors received from the switching network to the cache coherence processing unit.

12. The cache coherence processor according to claim 11, characterized in that, the cache coherence processing unit is used to perform cache coherence processing, and accesses all locations corresponding to the memory address information through a switching network through a network interface unit. Describe the memory on other hosts, specifically:

The cache consistency processing unit is used to perform cache consistency processing, and communicates with the cache consistency processor connected to the other host corresponding to the memory address information through the network interface unit through the switching network. The cache consistency processor connected to the other host accesses the memory on the other host corresponding to the memory address information.

13. The cache consistency processor according to claim 11 or 12, characterized in that: the cache consistency processing unit is further configured to, if the memory access request is a read memory instruction, pass the memory access result through The input and output unit sends the information to the virtual machine manager of the host.

14. The cache consistency processor according to any one of claims 11 to 13, characterized in that, the cache consistency processing unit includes:

Preprocessing submodule, used to connect with the input and output unit, the local agent submodule, and the remote agent submodule, and used to be responsible for the interaction between the input and output unit, the local agent submodule, and the remote agent submodule. message transmission between;

The local agent sub-module is used to process memory access requests to the host, perform cache consistency processing, and send the cache consistency directory update instructions to the directory management unit; the remote agent sub-module, Used to process memory access requests to other hosts other than the host, perform cache consistency processing, and access the memory of the other hosts through the switching network through the network interface unit.

15. A computer system, including: at least two hosts, at least two cache coherence processors and a switching network, wherein each of the at least two hosts is respectively consistent with the at least two caches. One cache coherence processor in the processor is connected, and the at least two cache coherence processors are communicatively connected through the switching network;

The first host among the at least two hosts is used to send memory processing commands to the connected a first cache coherence processor of at least two cache coherence processors;

The first cache consistency processor, if the memory processing command is cache status update information, is used to update the local cache consistency directory according to the cache status update information, where the cache status update information includes a memory block address. information and cache status information, or, the memory processing command is a memory access request of the virtual machine on the first host, used to perform cache consistency processing, and access the memory corresponding to the memory address information in the memory access request. .

16. The system according to claim 15, characterized in that the first cache consistency processor is used to update the local cache consistency directory according to the cache status update information, specifically:

The first cache consistency processor is configured to determine, according to the memory block address information, a record of the memory block corresponding to the memory block address information in the local cache consistency directory, and update the information according to the cache status Update the cache status information in the record of the memory block with the cache status information in the record of the memory block, and determine all of the at least two hosts that store copies of the memory block based on the current copy information in the record of the memory block. Hosts other than the first host notify the corresponding cache consistency processors of the other hosts to update their respective local cache consistency directories.

17. The system according to claim 15 or 16, characterized in that the first cache consistency processor is used to perform cache consistency processing and access the memory address information corresponding to the memory access request. memory, specifically:

The first cache consistency processor, if the memory corresponding to the memory address information is the memory on the first host, is used to perform cache consistency processing and access the memory of the first host, or, If the memory corresponding to the memory address information is a memory on a host other than the first host among the at least two hosts, it is used for cache consistency processing, and the memory address information corresponding to the memory address information is accessed through the switching network. of memory on said other hosts.

18. The system according to claim 17, characterized in that the first cache consistency processor is used to perform cache consistency processing and access the memory address corresponding to the memory address information through the switching network. Memory on other hosts, specifically:

The first cache consistency processor is used to perform cache consistency processing and communicate with the cache consistency processor connected to the other host corresponding to the memory address information through the switching network. The connected cache coherence processor accesses the memory on the other host corresponding to the memory address information.

19. The system according to claim 17 or 18, characterized in that:

The first cache consistency processor, if the memory access request is a read memory instruction, is also used to send the memory access result to the virtual machine manager of the first host.

20. The system according to any one of claims 15 to 19, characterized in that,

The virtual machine manager of the first host is also used to obtain the memory access request of the virtual machine, and determine whether the memory that needs to be accessed by the memory access request is the memory address information in the memory access request. The memory on the first host, if it is the memory on the first host, accesses the memory on the first host according to the memory access request, and sends the cache status update information to the third host. A cache coherence processor; if it is not the memory on the first host, then send the memory access request to the first cache coherence processor.