CN112579480A

CN112579480A - Storage management method, storage management device and computer system

Info

Publication number: CN112579480A
Application number: CN202011446206.9A
Authority: CN
Inventors: 杨凯歌; 林江; 曹俊
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2021-03-30
Anticipated expiration: 2040-12-09
Also published as: CN112579480B

Abstract

The present disclosure provides a storage management method, a storage management apparatus, and a computer system, the storage management apparatus including storage channel groups, each storage channel group including: at least two storage channels; and the shared directory is configured to store cache state information of cache data in a plurality of parallel caches, and can be accessed by the consistency master agent of each storage channel respectively, and the consistency master agent is configured to access the shared directory according to a received storage access request and perform cache consistency maintenance on the plurality of parallel caches according to the cache state information stored by the shared directory. A plurality of storage channels of the storage management device share one directory to maintain cache consistency, and the whole shared directory is in a working state, namely the storage channels do not have the situation that the directory is idle and does not work, so that the performance of the storage management device and a computer system is better.

Description

Storage management method, storage management device and computer system

Technical Field

The embodiment of the disclosure relates to a storage management method, a storage management device and a computer system.

Background

As semiconductor technology advances, processor designers can utilize more transistor resources to achieve higher performance chips. Meanwhile, the target workload is continuously changing, and from early days, mainly scientific computing to today's personal applications, server transactions, e-commerce applications and various embedded applications coexist.

Under the dual push of application requirements and the improvement of semiconductor process level, on-chip multiprocessor structures with higher parallelism are produced and become the latest direction of the development of the current high-performance processor architecture. Cache (Cache, referred to as Cache for short) consistency is a major core technology of a multiprocessor, and becomes a hot spot of research in academic and industrial fields, and in order to further improve the performance of the multicore processor, the management of Cache becomes an important problem in the research of the multicore processor.

Disclosure of Invention

Embodiments of the present disclosure provide a storage management method, a storage management apparatus, and a computer system, where a plurality of storage channels share a shared directory to perform cache consistency maintenance, so that the performance of the storage management apparatus and the computer system is better.

At least one embodiment of the present disclosure provides a storage management apparatus, including storage channel groups, each of the storage channel groups including:

at least two storage channels; and

the directory is shared in a shared manner,

wherein each of the memory channels includes a coherency master agent, the shared directory is configured to store cache state information for cache data in a plurality of parallel caches, accessible by the coherency master agent of each of the memory channels respectively,

the consistency master agent is configured to access the shared directory according to the received storage access request, and perform cache consistency maintenance on the plurality of parallel caches according to the cache state information stored by the shared directory.

For example, in a storage management apparatus provided in at least one embodiment of the present disclosure, the cache state information includes a coherency state of cache data in the cache and a cache address of the cache data in the cache, the cache data in the cache is provided by at least one storage apparatus, and the cache state information of the cache data includes the cache address which is a memory address of the storage apparatus providing the cache data, where the cache data is stored.

For example, in a storage management apparatus provided in at least one embodiment of the present disclosure, the storage access request includes an operation to be processed sent by a processor and a target storage access address corresponding to the operation, where the target storage access address is a memory address used for storing target data in the storage device of a storage channel to be accessed, and the processor sends the storage access request to a coherency master agent of the storage channel to be accessed according to the target storage access address.

For example, in a storage management apparatus provided in at least one embodiment of the present disclosure, the operation to be processed is a read operation, and the storage access request includes the read operation and a target storage access address corresponding to the read operation, so as to read the target data; alternatively, the first and second electrodes may be,

the operation to be processed is a write operation, the storage access request includes the write operation, and includes a target storage access address corresponding to the write operation and modification data to be written into the target storage access address, so as to replace the target data stored by the target storage access address with the modification data.

For example, in a storage management apparatus provided in at least one embodiment of the present disclosure, the shared directory includes a directory memory, the directory memory stores the cache state information according to a directory storage address, and the target storage access address included in the storage access request corresponds to the directory storage address, so that the coherent master agent accesses the directory storage address corresponding to the target storage access address in the shared directory according to the target storage access address of the storage access request.

For example, in a storage management device provided in at least one embodiment of the present disclosure, each directory storage address stores one or more cache status information, and each cache status information corresponds to an address subspace of the directory storage address.

For example, in a memory management device provided in at least one embodiment of the present disclosure, the shared directory further includes an arbitration distribution module, and the arbitration distribution module includes an arbitration sub-module configured to, in response to a plurality of coherent master agents of the memory channels simultaneously accessing the shared directory, determine that the plurality of coherent master agents access the directory memory in an access order through arbitration, and obtain the cache state information.

For example, in a storage management apparatus provided in at least one embodiment of the present disclosure, the directory memory includes N sub-directory memories, each sub-directory memory includes one or more directory storage addresses for storing the one or more cache status information, N is an integer greater than or equal to 1,

the arbitration distribution module determines that the number M of the consistent master agents which can access the directory memory at the same time is less than or equal to N, the number of the consistent master agents which can be accessed by each sub-directory memory before the same time is not more than 1, and M is an integer greater than or equal to 1.

For example, in a storage management device provided in at least one embodiment of the present disclosure, the arbitration distribution module further includes a distribution sub-module, and the distribution sub-module is configured to distribute the cache state information read from the directory memory to the coherency master agents of the corresponding storage channels, respectively.

For example, in a storage management apparatus provided in at least one embodiment of the present disclosure, each address subspace of the directory storage address is further used for storing channel information, so that the coherency master agent reads the cache state information and the channel information together according to the same address subspace of the same directory storage address, and the arbitration distribution module distributes the cache state information stored in the same address subspace with the channel information to the coherency master agent of a corresponding storage channel according to the channel information.

At least one embodiment of the present disclosure provides a storage management method, including:

providing at least one shared directory for a storage channel group comprising at least two storage channels, wherein the shared directory stores cache state information of cache data in a plurality of parallel caches;

and respectively sending a storage access request to a consistency master agent of at least one storage channel in the storage channel group to access the shared directory, and performing cache consistency maintenance on the plurality of parallel caches according to the cache state information stored in the shared directory.

For example, in a storage management method provided in at least one embodiment of the present disclosure, the cache state information includes: the cache state information of the cache data comprises a cache address which is a memory address for storing the cache data in the storage device which provides the cache data.

For example, in a storage management method provided by at least one embodiment of the present disclosure, respectively sending a storage access request to a consistent master agent of at least one storage channel in the storage channel group to access the shared directory, the method includes:

causing the memory access request to include an operation to be processed and a target memory access address corresponding to the operation, wherein the target memory access address is a memory address for storing target data in the memory device of a memory channel to be accessed,

and respectively sending the storage access requests to the consistency master agent of the storage channel to be accessed according to the target storage access address.

For example, in a storage management method provided in at least one embodiment of the present disclosure, the operation to be processed is a read operation, and the storage access request includes the read operation and a target storage access address corresponding to the read operation, so as to read the target data; alternatively, the first and second electrodes may be,

For example, in a storage management method provided in at least one embodiment of the present disclosure, accessing the shared directory includes: and reading the cache state information from the shared directory, and/or writing the cache state information into the shared directory.

For example, in a storage management method provided by at least one embodiment of the present disclosure, reading the cache state information from the shared directory, and/or writing the cache state information to the shared directory includes: the shared directory stores the cache state information according to a directory storage address, and a target access address included in the storage access request corresponds to the directory storage address, so that the corresponding directory storage address in the shared directory is accessed according to the target access address of the storage access request to read the cache state information stored in the directory storage address, and/or to write the cache state information into the directory storage address.

For example, in a storage management method provided by at least one embodiment of the present disclosure, each directory storage address stores one or more cache state information, and each cache state information corresponds to an address subspace of the directory storage address.

For example, in a storage management method provided in at least one embodiment of the present disclosure, reading the cache state information from the shared directory further includes:

and after the storage access requests are simultaneously sent to the consistency master agents of the plurality of storage channels in the storage channel group, determining to access the shared directory according to the storage access requests by arbitration, and respectively acquiring the cache state information.

For example, in a storage management method provided in at least one embodiment of the present disclosure, the reading, by the shared directory, the cache state information further includes:

and distributing the cache state information read from the shared directory to a consistency master agent of a corresponding storage channel.

For example, in a storage management method provided by at least one embodiment of the present disclosure, distributing the cache state information read from the shared directory to a coherency master agent of a corresponding storage channel includes:

and distributing the cache state information which is stored in the same address subspace with the channel information and is read out together with the channel information to a consistency master agent of a corresponding storage channel according to the channel information stored in each address subspace of the directory storage address, wherein the channel information stored in the address subspace of the directory storage address is written into the address subspace together with the cache state information.

For example, in a storage management method provided in at least one embodiment of the present disclosure, performing cache consistency maintenance on the multiple parallel caches according to the cache state information stored in the shared directory includes:

and responding to the storage access request and obtaining an access result, and writing cache state information matched with the access result and the storage access request into the shared directory to update the shared directory.

For example, in a storage management method provided by at least one embodiment of the present disclosure, in response to the storage access request and obtaining an access result, writing cache state information matching the access result and the storage access request into the shared directory to update the shared directory, including:

in response to that the directory storage address of the shared directory comprises first cache state information with a cache address identical to a target access address of the storage access request, writing second cache state information matched with the access result and the storage access request into the directory storage address, so that the first cache state information of a corresponding address subspace of the directory storage address is updated to the second cache state information;

or, in response to that the cache addresses of all first cache state information included in the directory storage address of the shared directory are different from the target storage access address of the storage access request, writing second cache state information matched with the access result and the storage access request into the directory storage address, so that an address subspace, in which the first cache state information is not stored, in the directory storage address stores the second cache state information, or selecting one address subspace, in which the first cache state information is stored, in the directory storage address to store the second cache state information.

At least one embodiment of the present disclosure provides a computer system, including:

a plurality of parallel processing nodes, wherein each processing node comprises a processor and a cache;

a storage management apparatus, wherein the storage management apparatus includes storage channel groups, each of the storage channel groups including: at least two storage channels; the cache coherency management system comprises a plurality of parallel caches, a shared directory, a plurality of processing nodes and a plurality of cache coherency management modules, wherein each storage channel comprises a coherency master agent, the shared directory is configured to store cache state information of cache data in the plurality of parallel caches, and can be accessed by the coherency master agent of each storage channel respectively, and the coherency master agent is configured to access the shared directory according to a received storage access request and maintain the cache coherency of the plurality of parallel processing nodes according to the cache state information stored by the shared directory;

at least one storage device configured to communicate with the storage management device and provide cached data to the caches of the plurality of parallel processing nodes over the at least two storage channels.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a basic multi-core processor multi-cache computer system;

FIG. 2 is a schematic diagram of a computer system including a storage management device according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a computer system including a storage management device according to yet further embodiments of the present disclosure; and

fig. 4 is a schematic composition diagram of a shared directory according to some embodiments of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The use of the terms "a" and "an" or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

In a computer system with a multi-core processor and a multi-Cache (Cache, abbreviated as Cache), a Cache may Cache a large amount of data, and the cached data may be exclusive or may store copies of cached data with the same memory address in different caches. When different caches operate on cached data for the same memory address, coherency problems arise.

Many methods have been developed to maintain coherency, for example, when multiple caches have the same cached data copy, if a processor of a computer system wants to modify a cached data copy, the data copy in other caches will be marked invalid to avoid coherency errors.

Generally, there are two ways to implement cache coherency maintenance, one based on broadcast and the other based on directory. With the scale of the multi-core multi-processor system becoming larger and larger, the cache coherence protocol based on the directory becomes the mainstream nowadays, so that the multi-core multi-processor system can improve the efficiency of cache coherence maintenance. A directory-based coherency protocol may help track cache state in multiple caches, e.g., only a single copy in a cache, multiple copies, or only main memory medium state for the data.

A multi-core processor system typically includes multiple memory channels, with the processor accessing the memory of different memory channels according to an access address. In a directory-based coherency protocol system, each memory channel is typically associated with a directory that tracks the state of the cache accessing the memory channel and stores the tracked cache state information in the directory. When a coherency agent discovers coherency transactions (e.g., various requests and processes thereof that require maintaining cache coherency), it queries the cache state information tracked in the directory and issues corresponding probes to complete cache coherency maintenance.

FIG. 1 is a schematic diagram of a basic multi-core processor multi-cache computer system. As shown in fig. 1, the storage management apparatus of the computer system includes two storage channels, each storage channel includes a consistency master agent, each consistency master agent is connected to a directory, and each directory records cache status information for maintaining cache consistency.

The inventor finds that: in the computer system shown in fig. 1, each of the plurality of storage channels of the storage management apparatus includes a coherency master agent and a directory corresponding thereto, and when a certain storage channel needs to be accessed, the coherency master agent first queries the directory and completes coherency maintenance and accesses the corresponding memory or cache. The multi-memory channel corresponds to a plurality of directories, each directory corresponds to a memory channel one by one, and the memory channels in the system are usually not all enabled, that is, only part of the memory channels in the plurality of memory channels are connected with the memory, other channels are not connected with the memory, the computer system with the multi-core processor and the multi-cache can still work normally, but under the condition that the memory channels are not completely used, the consistency master agent and the directories of the unused memory channels are also in idle and non-working states, and each directory including the idle directory needs to store a large amount of cache state information, so that a large circuit area is occupied, namely, a large amount of circuit area is wasted by the idle and non-working directory.

At least one embodiment of the present disclosure provides a storage management apparatus, including storage channel groups, each storage channel group including:

at least two storage channels; and

the directory is shared in a shared manner,

each storage channel comprises a consistency master agent, and the shared directory is configured to store cache state information of cache data in a plurality of parallel caches and can be accessed by the consistency master agent of each storage channel respectively; the consistency master agent is configured to access the shared directory according to the received storage access request, and perform cache consistency maintenance on the plurality of parallel caches according to the cache state information stored by the shared directory.

Compared with the case that the plurality of storage channels respectively correspond to one independent directory, the embodiment does not have the case that the directory is idle and does not work even if the channels are not used, so that the performance of the storage management device and the computer system is better.

At least one embodiment of the present disclosure provides a storage management apparatus, for example, the storage management apparatus includes one storage channel group or includes a plurality of storage channel groups, where each storage channel group includes a plurality of storage channels and a shared directory, respectively. The following description mainly takes an example that one storage channel group of the storage management device includes 2 storage channels and 1 shared directory, the number of memory channel groups and the number of memory channels included in each memory channel group are not limited by the disclosed embodiments, however, for example, 3 memory channels in one memory channel group share 1 shared directory, or 4 memory channels in one memory channel group share 2 shared directories (for example, every two memory channels share one shared directory respectively), or 5 memory channels share 2 shared directories (for example, two memory channels share one shared directory, and the other three memory channels share another shared directory), as long as a plurality of memory channels in each memory channel group share one shared directory, which is not exhaustive and described herein in the embodiments of the present disclosure.

At least one embodiment of the present disclosure further provides a storage management method.

At least one embodiment of the present disclosure also provides a computer system including a storage management apparatus.

FIG. 2 is a schematic diagram of a computer system including a storage management device according to some embodiments of the present disclosure.

For example, as shown in FIG. 2, a computer system includes a storage management device including a storage channel group including 2 storage channels and 1 shared directory, a plurality of parallel processing nodes, and two storage devices (e.g., memory 501 and memory 502 shown in FIG. 2).

Each processing node includes a processor node (hereinafter referred to simply as a processor) and a cache (hereinafter referred to simply as a cache), and the processor of each processing node is configured to access the corresponding cache or memory via a memory management device during operation. The present disclosure is not limited with respect to the type and implementation of the processor and the memory, for example, the processor may be a single-core processor or a multi-core processor, may be a RISC or CISC processor, etc., and the memory may be a semiconductor memory, such as a volatile memory or a non-volatile memory. For example, in some examples, as shown in fig. 2, a first processor node includes processor node 101 and cache 201, a second processor node includes processor node 102 and cache 202, a third processor node includes processor node 103 and cache 203, and a fourth processor node includes processor node 104 and cache 204.

The memory 501 and the memory 502 are configured to communicate with a storage management apparatus and provide cache data to caches of a plurality of parallel processing nodes through two storage channels.

It should be noted that the four processing nodes and the two memories in fig. 2 are only an example, and are not limiting to the present disclosure, and may be freely adjusted specifically according to actual needs, and the embodiments of the present disclosure are not exhaustive and repeated here.

For example, in some examples, each storage channel includes a coherence master agent (HomeAgent). The consistency master agent is a concept of a computer system for cache consistency maintenance technology, and is a circuit module for processing cache consistency transactions related to a memory in a chip, for example, the consistency master agent includes various probe processing modules for processing access transactions to the memory and maintaining consistency, that is, a specific circuit design of the consistency master agent is subject to only functions and operations implemented in the embodiments herein, and the embodiments of the present disclosure are not limited thereto and are not described herein again.

As shown in fig. 2, the 2 memory channels included in the memory channel group are respectively denoted as a first memory channel and a second memory channel, the first memory channel includes a coherency master agent 301, and the second memory channel includes a coherency master agent 302. The consistency master agent 301 and the consistency master agent 302 share a directory, that is, the consistency master agent 301 and the consistency master agent 302 are connected in communication with a shared directory 4, and the shared directory 4 is configured to store cache state information of cache data in a plurality of parallel caches, which can be accessed by the consistency master agent (e.g. the consistency master agent 301 and the consistency master agent 302) of each memory channel respectively.

For example, in some examples, a memory channel refers to a channel from a memory to a connected coherency master agent to a coherency interconnect. For example, in the example of FIG. 2, the first memory channel refers to the channel from memory 501 to the connected coherent master agent 301 to the coherent interconnect 6, and the second memory channel refers to the channel from memory 502 to the connected coherent master agent 302 to the coherent interconnect 6. The coherent interconnect may be implemented, for example, by using a bus and using an appropriate internal communication protocol, which is not limited by this disclosure.

For example, in some examples, a coherency master (e.g., coherency master 301 and coherency master 302) is configured to access shared directory 4 based on a received memory access request and to perform cache coherency maintenance on caches of multiple parallel processing nodes based on cache state information stored by shared directory 4. For example, the cache state information about the first memory channel and the second memory channel is stored in the same shared directory 4, and the same shared directory 4 is also accessed when coherency maintenance is required.

For example, in some examples, the cache state information includes a coherency state of the cache data in the cache and a cache address of the cache data in the cache, wherein the cache data in the cache is provided by the at least one memory, and the cache address included in the cache state information of the cache data is a memory address in the memory providing the cache data where the cache data is stored. For example, the coherency state included in the cache state information of the cache data may be modified (M), exclusive (E), shared (S), invalid (I), or the like, which is not limited by the embodiments of the present disclosure.

For example, in some examples, the storage access request received by the coherent master agent includes: the method comprises the steps of sending a to-be-processed operation and a target storage access address corresponding to the operation by a processor, wherein the target storage access address is a memory address used for storing target data in a memory of a to-be-accessed memory channel, and therefore the processor sends a corresponding storage access request to a consistency master agent of the to-be-accessed memory channel according to the target storage access address. For example, coherency master 301 receives a pending read operation sent by processor 101 and a memory address for storing target data in memory 501.

For example, in some examples, the pending operation sent by the processor is a read-write operation.

For example, when the operation to be processed is a read operation, the memory access request includes the read operation and a target memory access address corresponding to the read operation, so as to read target data stored in the target memory access address. For example, when a processor of a processing node needs to read from a cache, if the required data cannot be found in the cache, the processor needs to issue a storage access request to obtain the required data from another cache or a memory; specifically, a memory access request sent by the processor to the memory channel needs to pass through a consistency master agent of the memory channel to be accessed, the consistency master agent accesses the cache state information of the shared directory 4, searches for corresponding cache state information in the shared directory through a target memory access address of the memory access request, and then enables the processor to obtain required data from other caches or memories according to an access result.

For example, when the operation to be processed is a write operation, the memory access request includes the write operation and modification data including a target memory access address corresponding to the write operation and a target memory access address to be written, so as to replace the target data stored by the target memory access address with the modification data.

It should be noted that, in the embodiment of the present disclosure, the number of times of the storage access request issued by a certain processor or the number of processors for issuing the storage access request are not limited, and may be freely adjusted according to actual needs.

For example, in some examples, when the coherent master agent accesses shared directory 4, the cache state information may be read from the shared directory or written to the shared directory.

FIG. 3 is a schematic diagram of a computer system including a storage management device according to yet further embodiments of the present disclosure.

For example, as shown in fig. 3, the coherency master agent 301 of one of the memory channels in the memory channel group of the memory management apparatus is communicatively connected to the memory 501, and the coherency master agent 302 of the other memory channel is not communicatively connected to the corresponding one of the memories, which means that the shared directory 4 is now exclusively owned by the one of the memory channels in which the coherency master agent 301 is located. For example, if the memory channel in which the coherency master agent that has been communicatively connected to the memory is located is denoted as an available memory channel and the memory channel in which the coherency master agent that has not been communicatively connected to the memory is located is denoted as an unavailable memory channel, any processor sends a memory access request to the available memory channel, but does not send a memory access request to the unavailable memory channel, according to the memory channel enable of the system.

For example, in some examples, the dashed boxes in fig. 2 and fig. 3 represent processor chips inside a computer system, and the devices outside the dashed boxes all represent devices outside the computer system, for example, a memory slot is provided on a computer, when a memory channel group includes two coherent master agents, two memory slots are provided correspondingly, and in actual use, both the memory slots may be plugged with a memory, that is, both the memory channels are available memory channels, or only one of the memory slots may be selected to be plugged with a memory, that is, only one available memory channel is available at this time.

It should be noted that no matter how many coherent master agents of memory channels exist, at least one available memory channel exists in the computer system (i.e. at least one memory slot is inserted with memory) so that the computer system can operate normally, otherwise, the cache of the computer system has no cache target and cannot be used normally.

In addition, for the memory channel enablement of the system, it can be understood that: although the storage channel group comprises a plurality of storage channels and a consistency master agent, a part of the consistency master agent may be in communication connection with an external memory, another part of the consistency master agent is not in communication connection with the external memory, and the processor needs to send a storage access request to an available storage channel in communication connection with the external memory, that is, the processor learns relevant information of the available storage channel through other functional modules of the computer system in advance and sends out an available storage channel corresponding to the corresponding storage access request.

It is noted that although only one storage channel in which the coherency master agent 301 is located is available and the shared directory is exclusively owned by the one storage channel in the example of fig. 3, the shared directory 4 of the example of the present disclosure is still a shared directory, which does not have the directory idle and idle as compared to a case where one directory is idle and idle as compared to a case where two separate independent directories are available in one storage channel, and the size of the directory capacity of the shared directory 4 is doubled (e.g., equal to 2 times or close to 2 times) as compared to a case where two separate independent directories are available in a single storage channel, the entire shared directory of the example of the present disclosure can be used, the shared directory is less prone to performance-affecting problems such as degradation, and the better tolerance of local non-uniformity, the performance of the system will be better.

As shown in fig. 4, the shared directory 4 includes a directory memory 401, wherein the directory memory 401 stores each cache state information according to a directory storage address, and a target storage access address included in the storage access request corresponds to the directory storage address of the directory memory 401, so that the coherency master agent accesses the directory storage address corresponding to the target storage access address in the shared directory 4 according to the target storage access address of the storage access request, to read the cache state information stored by the directory storage address, and/or to write the cache state information to the directory storage address.

It should be noted that, regarding the way in which the target memory access address included in the memory access request corresponds to the directory memory address of the directory memory 401, the embodiment of the present disclosure is not limited to this, for example, directory memory address 1 can store 10 pieces of cache status information, the cache addresses stored in the directory memory address 1 are all even numbers, the directory memory address 2 can also store 10 pieces of cache status information, the cache addresses stored in the directory storage address 2 are all odd numbers, and if the target storage access address included in the current storage access request is an even number, the query needs to be accessed from the directory storage address 1, but the query cannot be accessed from the directory storage address 2, which is only an example, the application range of the embodiments of the present disclosure is not limited, and the embodiments of the present disclosure are not described herein.

For example, in some examples, in response to a memory access request issued by a certain processor, a coherency master agent of a memory channel corresponding to the memory access request may obtain a corresponding access result (e.g., the directory storage address of the shared directory 4 includes cache state information having a cache address identical to a target access address of the memory access request, or the directory storage address of the shared directory 4 includes all first cache state information having a cache address different from the target memory access address of the memory access request), and the coherency master agent may write the cache state information matching the access result and the memory access request to the shared directory 4 to update the shared directory 4.

For example, in some examples, each directory storage address may store one cache state information, or may store a plurality of cache state information, each corresponding to an address subspace of the directory storage address. For example, the bit width of the directory storage address is 32 bits and the directory storage address includes two pieces of cache state information, the first cache state information is placed in the lower 16 bits (i.e. one address subspace, the lower 16 bits may be referred to as the first vacancy of the directory storage address) of the directory storage address for storage, and the second cache state information is placed in the upper 16 bits (i.e. another address subspace, the upper 16 bits may be referred to as the second vacancy of the directory storage address) of the directory storage address for storage. Of course, this is merely an example, and is not a limitation of the present disclosure, that is, the cache state information stored in each directory storage address is not limited in the embodiment of the present disclosure, and details are not described here.

It should be noted that, no matter whether the cache address of the cache state information that can be found according to the storage access request is the same as the target storage access address of the storage access request, the directory memory 401 will have a directory storage address corresponding to the target storage access address of the storage access request for the access of the coherency master agent, but the embodiment of the present disclosure performs different coherency maintenance for different access results.

For example, in some examples, when the directory storage address of the shared directory 4 includes the same cache state information (denoted as first cache state information) as the target access address of the storage access request, the coherency master agent writes new cache state information (denoted as second cache state information) matching the access result and the storage access request to the directory storage address at this time, so that the first cache state information of the corresponding address subspace of the directory storage address is updated to the second cache state information.

For another example, in some examples, when the directory storage address of the shared directory 4 includes all the cache addresses of the first cache state information that are different from the target storage access address of the storage access request, the coherency master agent writes the second cache state information matching the access result and the storage access request into the directory storage address at this time, so that the second cache state information is stored into the appropriate address subspace in the target storage access address. Further, for example, when the target storage access address has a vacant address subspace (i.e. an address subspace not storing the first cache state information), any vacant address subspace in the directory storage address is allowed to store the second cache state information; for another example, when the target storage access address has no empty address subspace (i.e., an address subspace not storing the first cache state information), one address subspace used for storing the first cache state information in the directory storage address may be selected to store the second cache state information, that is, the second cache state information replaces the originally stored first cache state information in the address subspace, where as to which address subspace storing the first cache state information is selected, the address subspace may be freely adjusted according to specific situations, which is not limited and elaborated in the embodiment of the present disclosure.

As described above, due to local non-uniformity of memory access, the above-described embodiment of the present disclosure uses 1 shared directory with a larger capacity, and has more cache state information than non-uniformity that can be accommodated by using 2 independent directories, so that performance is not easily affected by degradation, and the probability of evicting cache state information of a directory due to local non-uniformity is reduced. Specifically, in order to balance the access numbers of the plurality of memory channels, the access numbers of the plurality of memory channels are averaged by various methods, and generally, the access numbers can be randomly distributed on the plurality of memory channels, but the random averaging effect becomes worse in a smaller time or space locality, and in the embodiment of the present disclosure, as the capacity of the shared directory increases, the spatial locality that can be accommodated becomes larger, and the unevenness becomes smaller, that is, the probability of uneven local distribution caused by the capacity limitation of the associated number of directory groups or each group is reduced.

It is to be noted that, in the above embodiment of the present disclosure, a shared directory with a larger capacity is used, and a circuit area of the shared directory may be substantially equal to or slightly smaller than a sum of circuit areas of two independent directories, which is not limited by the embodiment of the present disclosure.

For example, the shared directory may be implemented by an SRAM (Static Random-Access Memory), which supports 1 read or write Access at the same time, and when multiple coherent master agents Access at the same time, a concurrency conflict may occur. To solve this technical problem, for example, as shown in fig. 4, the shared directory 4 is provided with an arbitration distribution module 402, wherein the arbitration distribution module 402 is used for processing concurrent conflicts when a plurality of coherent master agents simultaneously access the shared directory 4.

For example, in some examples, the arbitration distribution module 402 includes an arbitration sub-module, wherein when the coherent master agents of multiple memory channels simultaneously access the shared directory 4 (e.g., the coherent master agent 301 and the coherent master agent 302 simultaneously access the shared directory 4 in fig. 4), the arbitration sub-module of the arbitration distribution module 402 is required to handle conflicting or non-conflicting accesses by arbitration so that the coherent master agents smoothly access the directory memory 401. For example, the arbitration submodule of the arbitration distribution module 402 determines, through arbitration, that the plurality of coherent master agents access the directory memory 401 of the shared directory 4 according to the set access order, and respectively obtain corresponding cache state information.

It should be noted that the embodiment of the present disclosure is not only applicable to the coherent master agent of multiple memory channels accessing the shared directory 4 at the same time, but also applicable to the coherent master agent of only one memory channel accessing the shared directory 4 at a certain time, and the embodiment of the present disclosure does not limit this.

Specifically, when only one coherent master agent of a memory channel accesses the shared directory 4 at a certain time, the arbitration submodule included in the arbitration distribution module 402 can still perform an arbitration function, so that the only coherent master agent accesses the shared directory. Or, when only one consistent master agent of a storage channel accesses the shared directory 4 at a certain time, the arbitration submodule included in the arbitration distribution module 402 does not perform an arbitration function at this time, that is, the only consistent master agent directly accesses the shared directory, which is not limited to a specific implementation manner in the embodiment of the present disclosure, and is not described herein again.

For example, in some examples, directory memory 401 in fig. 4 includes N sub-directory memories, N being an integer greater than or equal to 1. Each subdirectory memory includes one or more directory storage addresses, and each directory storage address may store one cache status information or a plurality of cache status information.

For example, in some examples, each sub-directory memory can be accessed by at most one consistent master agent at a time, and correspondingly, the arbitration sub-module of the arbitration distribution module 402 determines that the number M of consistent master agents that can access the entire directory memory 401 at the same time is less than or equal to N, where M is an integer greater than or equal to 1. For example, even if the addresses accessed by the consistency master agents are not the same directory storage address, as long as the addresses to be accessed by the consistency master agents are in the same subdirectory storage, the arbitration submodule of the arbitration distribution module 402 needs to enable only one of the consistency master agents to access at the same time. It should be noted that, in the embodiment of the present disclosure, the number of the subdirectory memories included in the directory memory 401 and the specific design of each subdirectory memory are not limited, and may be determined according to some factors, such as area, timing sequence, and cost, that need to be considered in circuit design, and no further description is given here in the embodiment of the present disclosure.

For example, as shown in fig. 4, the arbitration distribution module 402 further includes a distribution submodule, and the distribution submodule of the arbitration distribution module 402 is configured to distribute the cache state information read from the directory memory 401 to the coherency master agent (e.g., the coherency master agent 301 or the coherency master agent 302) of the corresponding memory channel, respectively.

As can be seen from the above, the arbitration submodule in the arbitration distribution module 402 plays an arbitration role when the coherency master agent accesses the shared directory to read the cache state information, and the distribution submodule in the arbitration distribution module 402 plays a distribution role when the read cache state information is provided to the coherency master agent.

In contrast to separate directories, for example, each address subspace of the directory storage address of the shared directory 4 of the disclosed embodiments not only stores cache state information, but is also used to additionally store channel information. For example, in some examples, the address subspace of the directory storage address stores the channel information that is written to the address subspace together with the cache state information, such as cache state information A1 and channel information B1, and cache state information A2 and channel information B2 in the example of FIG. 4.

Thus, the coherency master agent may read the cache state information and the channel information together according to the same address subspace of the same directory storage address, for example, the coherency master agent may read the cache state information a1 and the channel information B1 together or the cache state information a2 and the channel information B2 together.

For example, when a directory storage address of a certain memory space is found from the shared directory, the directory storage address is continuously divided to obtain a corresponding address subspace, and if the cache state information and the corresponding channel information are read or written together, the implementation can be realized by determining the read-write head address and the number of bytes or bits read or written. Illustratively, for example, if a bit width of a directory storage address is 64 bits, the directory storage address is divided into four slots (i.e., four address subspaces), and every 16 bits is taken as a slot, the first cache state information and the corresponding first channel information occupy one 16 bits, the second cache state information and the corresponding second channel information occupy one 16 bits, the third cache state information and the corresponding third channel information occupy one 16 bits, and the fourth cache state information and the corresponding fourth channel information also occupy one 16 bits.

As described above, the distribution submodule of the arbitration distribution module 402 distributes the cache state information stored in the same address subspace as the channel information to the consistency master agent of the corresponding storage channel according to the channel information. For example, the distribution submodule of the arbitration distribution module 402 distributes the cache state information a1 stored in the same address subspace as the channel information B1 to the coherency master agent 301 of the corresponding memory channel according to the channel information B1, and distributes the cache state information a2 stored in the same address subspace as the channel information B2 to the coherency master agent 302 of the corresponding memory channel according to the channel information B2.

For example, in some examples, the channel information stored in the address subspace may be a channel number, such as the channel information B1 being the number 1 and the channel information B2 being the number 2, but the channel information of the embodiments of the present disclosure is not limited thereto, that is, the embodiments of the present disclosure do not limit the specific form of the channel information. It should be noted that, in order to implement the distribution of the cache state information read from the directory memory to the coherency master agent of the corresponding memory channel, the embodiments of the present disclosure are not limited to the corresponding distribution according to the channel information, and any method capable of implementing the mutual correspondence between the cache state information and the coherency master agent of the memory channel belongs to the protection scope of the embodiments of the present disclosure. Therefore, based on the distribution submodule of the arbitration distribution module 402, the embodiment of the present disclosure can reply to the corresponding coherency master agent according to read or write access, and can avoid replying to the wrong coherency master agent, so as to smoothly complete cache coherency maintenance.

For example, as shown in fig. 4, the shared directory 4 further includes a shared directory control module 403, and the shared directory control module 403 is configured to perform configuration and control operations on the shared directory 4, so that the respective portions of the shared directory can work together normally. In addition, for example, the shared directory 4 includes peripheral circuits and interfaces in addition to the directory memory 401, the arbitration distribution module 402, and the shared directory control module 403, which are not described in detail in this embodiment of the disclosure.

For example, in some examples, the shared directory control module 403 may control and coordinate the modules in the shared directory 4 to cooperate with each other (e.g., the shared directory further includes an interface module, etc.), and the shared directory control module 403 may also configure and control the arbitration distribution module 402, such as the shared directory control module 403 controls the arbitration distribution module 402 to arbitrate and distribute.

For example, when multiple coherent master agents access the shared directory, the shared directory control module 403 may notify the control arbitration distribution module 402 that some coherent master agents of the memory channels are available and some coherent master agents of the memory channels are not available, and the shared directory control module 403 configures the arbitration mode of the arbitration distribution module 402 (e.g., controls how the arbitration distribution module 402 should decide the access sequence), and the arbitration distribution module 402 itself determines the access sequence of the coherent master agents to access the directory memory. It is to be noted that the function of the shared directory control module 403 in the embodiment of the present disclosure is not limited thereto, and it needs to be freely adjusted according to actual situations, and the embodiment of the present disclosure does not limit the specific circuit design of the shared directory control module 403, as long as the functions and operations implemented in the embodiment herein are taken as the standard, and a person skilled in the art can know the specific scheme of implementing the circuit design of the shared directory control module 403 according to the description related to the embodiment herein, and the embodiment of the present disclosure is not described in detail.

In the storage management device according to the embodiment of the present disclosure, the plurality of storage channels share one directory for maintaining cache consistency, and the shared directory utilizes all directory spaces, and compared with a case where the plurality of storage channels respectively correspond to one independent directory, the embodiment does not have a case where a directory is idle and does not work when a single storage channel is available, and the shared directory is not prone to degradation and other problems that affect performance, and the better the tolerance degree of local non-uniformity is, so that the performance of the storage management device and the computer system is better.

At least one embodiment of the present disclosure further provides a storage management method, including:

the method comprises the steps of respectively sending a storage access request to a consistency master agent of at least one storage channel in a storage channel group to access a shared directory, and carrying out cache consistency maintenance on a plurality of parallel caches according to cache state information stored in the shared directory.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the description of the storage management apparatus above for specific processes and technical effects of the storage management method, and details are not described here.

At least one embodiment of the present disclosure provides a computer system, including: a plurality of parallel processing nodes, a storage management device and at least one storage device.

Each processing node of the plurality of parallel processing nodes includes a processor and a cache. The storage management apparatus includes storage channel groups, each storage channel group including: at least two storage channels; and the shared directory is configured to store cache state information of cache data in a plurality of parallel caches, and can be accessed by the master consistency agent of each storage channel respectively, and the master consistency agent is configured to access the shared directory according to a received storage access request and perform cache consistency maintenance on the caches of the plurality of parallel processing nodes according to the cache state information stored by the shared directory. At least one storage device is configured to communicate with the storage management device and provide cached data to caches of multiple parallel processing nodes over at least two storage channels.

It should be noted that, in the embodiment of the present disclosure, the storage management device included in the computer system may refer to the description about the storage management device in the foregoing, and details are not described here.

The various modules in the above embodiments of the present disclosure may each be configured as software, hardware, firmware, or any combination thereof that performs a particular function. For example, the modules may correspond to an application specific integrated circuit, to pure software code, or to a combination of software and hardware.

It should be noted that, although the storage management apparatus is described above as being divided into modules for respectively executing corresponding processes, it is clear to those skilled in the art that the processes executed by the modules may also be executed without any specific division of the modules by the storage management apparatus or without explicit delimitation between the modules.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A storage management apparatus comprising storage channel groups, each of the storage channel groups comprising:

at least two storage channels; and

the directory is shared in a shared manner,

2. The storage management apparatus of claim 1, wherein the cache state information comprises a coherency state of the cache data in the cache and a cache address of the cache data in the cache,

the cache data in the cache is provided by at least one storage device, and the cache state information of the cache data comprises a cache address which is a memory address for storing the cache data in the storage device providing the cache data.

3. The storage management apparatus of claim 2, wherein the storage access request comprises a pending operation sent by a processor and a target storage access address corresponding to the operation,

the target memory access address is a memory address for storing target data in the memory device of the memory channel to be accessed,

and the processor sends the storage access request to a consistency master agent of the storage channel to be accessed according to the target storage access address.

4. The storage management apparatus of claim 3,

the operation to be processed is a read operation, and the storage access request comprises the read operation and a target storage access address corresponding to the read operation, so as to read the target data; alternatively, the first and second electrodes may be,

5. The storage management apparatus of claim 3, wherein the shared directory comprises a directory memory,

and the directory memory stores the cache state information according to a directory memory address, and a target memory access address included in the memory access request corresponds to the directory memory address, so that the consistency master agent accesses the directory memory address corresponding to the target memory access address in the shared directory according to the target memory access address of the memory access request.

6. The storage management device of claim 5, wherein each of the directory storage addresses stores one or more cache state information, each of the cache state information corresponding to an address subspace of the directory storage addresses, respectively.

7. The storage management apparatus of claim 6, wherein the shared directory further comprises an arbitration distribution module comprising an arbitration sub-module,

the arbitration distribution module comprises an arbitration submodule configured to, in response to simultaneous access of the shared directory by the coherent master agents of the plurality of storage channels, determine that the plurality of coherent master agents access the directory memory in an access order by arbitration, and acquire the cache state information.

8. The storage management device of claim 7, wherein the directory memory comprises N sub-directory memories, each sub-directory memory comprising one or more of the directory storage addresses for storing the one or more cache state information, N being an integer greater than or equal to 1,

9. The storage management apparatus of claim 7, wherein the arbitration distribution module further comprises a distribution submodule,

the distribution submodule is configured to distribute the cache state information read from the directory memory to the coherency master agents of the corresponding memory channels, respectively.

10. The storage management device of claim 7, wherein each address subspace of the directory storage address is further configured to store channel information, respectively, such that the coherence master agent reads the cache status information and the channel information together according to a same address subspace of a same directory storage address,

and the arbitration distribution module distributes the cache state information stored in the same address subspace with the channel information to a consistency master agent of a corresponding storage channel according to the channel information.

11. A storage management method, comprising:

12. The storage management method of claim 11, wherein the cache state information comprises: a coherency state of the cache data in the cache and a cache address of the cache data in the cache,

13. The storage management method of claim 12,

accessing the shared directory by sending a storage access request to a consistent master agent of at least one of the storage channels in the storage channel group, respectively, comprising:

14. The storage management method of claim 13,

15. The storage management method according to any one of claims 11 to 14,

accessing the shared directory, including:

and reading the cache state information from the shared directory, and/or writing the cache state information into the shared directory.

16. The storage management method of claim 15,

reading the cache state information from the shared directory, and/or writing the cache state information into the shared directory, including:

the shared directory stores the cache state information according to a directory storage address, and a target access address included in the storage access request corresponds to the directory storage address, so that the corresponding directory storage address in the shared directory is accessed according to the target access address of the storage access request to read the cache state information stored in the directory storage address, and/or to write the cache state information into the directory storage address.

17. The storage management method of claim 16,

each directory storage address stores one or more cache state information, and each cache state information corresponds to an address subspace of the directory storage address.

18. The storage management method of claim 17,

reading the cache state information from the shared directory, further comprising:

19. The storage management method of claim 17,

the shared directory reads the cache state information, and the method further comprises the following steps:

20. The storage management method of claim 19,

distributing the cache state information read from the shared directory to a coherency master agent of a corresponding storage channel, comprising:

21. The storage management method according to any one of claims 17 to 20,

performing cache consistency maintenance on the plurality of parallel caches according to the cache state information stored in the shared directory, including:

22. The storage management method of claim 21,

responding to the storage access request and obtaining an access result, writing cache state information matched with the access result and the storage access request into the shared directory to update the shared directory, wherein the updating comprises the following steps:

or, in response to that the cache addresses of all the first cache state information included in the directory storage address of the shared directory are different from the target storage access address of the storage access request, writing second cache state information matched with the access result and the storage access request into the directory storage address, so that the second cache state information is stored in an address subspace where the first cache state information is not stored in the directory storage address,

or, one address subspace used for storing the first cache state information in the directory storage address is selected to store the second cache state information.

23. A computer system, comprising:

a storage management apparatus, wherein the storage management apparatus includes storage channel groups, each of the storage channel groups including:

at least two storage channels; and

a shared directory, wherein each storage channel comprises a consistency master agent, the shared directory is configured to store cache state information of cache data in a plurality of parallel caches, and is accessible by the consistency master agent of each storage channel, the consistency master agent is configured to access the shared directory according to a received storage access request, and perform cache consistency maintenance on the caches of the plurality of parallel processing nodes according to the cache state information stored by the shared directory;