CN106898650B - 具有渐变主体掺杂的ldmos器件 - Google Patents

具有渐变主体掺杂的ldmos器件 Download PDF

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CN106898650B
CN106898650B CN201611181657.8A CN201611181657A CN106898650B CN 106898650 B CN106898650 B CN 106898650B CN 201611181657 A CN201611181657 A CN 201611181657A CN 106898650 B CN106898650 B CN 106898650B
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CN106898650A (zh
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H·L·爱德华兹
J·R·托德
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Texas Instruments Inc
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Texas Instruments Inc
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    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

一种横向扩散MOS(LDMOS)器件(200)包括具有在其上的p外延层(115)的衬底(110)。P主体区域(140)在p外延层中。ndrift(NDRIFT)区域(120)在提供漏极扩展区域(145)的p主体区域内，并且栅极介电(122)层形成在与NDRIFT区域的结的相应侧相邻的和在与NDRIFT区域的结的相应侧上的p主体区域中的沟道区域上，并且图案化的栅极电极(123)形成在栅极电介质上。DWELL区域(130)在p主体区域内，侧壁间隔物(138)在栅极电极的侧壁上，源极区域(148)在DWELL区域内，并且漏极区域在NDRIFT区域内。p主体区域(140)包括具有高于p外延层(115)的掺杂水平的净p型掺杂水平和至少5/μm的净p型掺杂分布梯度的至少一个0.5μm宽的一部分。

Description

具有渐变主体掺杂的LDMOS器件
相关申请的交叉参考
本申请是2015年12月18日提交的美国非临时专利申请序列No.14/974,951的继续申请，其全部内容以引用方式并入本文。
技术领域
所公开的实施例涉及横向扩散金属氧化物半导体(LDMOS)器件。
背景技术
随着DC-DC转换器按比例缩小为下一代功率转换器产品，需要增加开关频率，以减少外部无源部件(诸如电感器)的尺寸，同时维持在其集成功率场效应晶体管(FET)(诸如LDMOS器件)中的低功率消耗。在LDMOS器件中，横向布置漏极，以允许电流横向流动，并且漂移区域被插入在沟道和漏极之间，以提供高的漏极到源极的击穿电压。增加开关频率涉及减少功率FET的二极管反向恢复(Drr)时间。
Drr是反向恢复电荷(Qrr)的函数，反向恢复电荷(Qrr)是在换向期间储存在功率FET的主体区域中的少数载流子电荷量。换向是当电感变换器负载迫使电流进入功率FET的主体二极管中时，对于n沟道功率FET导致p型主体区域充满少数载流子(电子)。二极管恢复电流的时间积分是Qrr。高的Qrr能够引起各种问题，包含(1)在漏极电压斜升期间激活寄生主体NPN双极性路径，这能够引起功率消耗或处于功率FET的热失效的极端情况，以及(2)主体二极管感应电流消耗，这能够导致开关电路减少的效率。
传统的功率LDMOS器件是n沟道器件，该n沟道器件采用在垂直方向上具有相当均匀的掺杂分布的p型主体区域。主体掺杂中的一些一般来自p型外延硅，该p型外延硅具有实质上均匀的硼掺杂。额外的p型主体掺杂能够来自高能量(接近MeV或MeV)的p型(例如，硼)埋层(PBL)注入物，该p型(例如，硼)埋层(PBL)注入物遭受随后的高温炉处理，并且因此使如大量注入的高斯硼掺杂物分布在垂直方向上扩散，使得在垂直方向上跨越LDMOS主体区域的p型掺杂中的变化是大致是逐渐的。例如，对于已知的LDMOS器件，p主体区域可以是4μm(微米)深度，并且从以本质上恒定的垂直掺杂物浓度梯度分散的主体区域的顶部(硅表面)到底部具有至多12倍(X)掺杂变化。本质上恒定的垂直掺杂物浓度梯度通常是高于通过主体的任何0.5μm或更宽的区域的p外延区域的掺杂水平的至多大约2X/μm到3X/μm。
发明内容
本发明内容被提供用于以简化形式介绍下面在包括所提供的附图的具体实施方式中进一步描述的所公开的概念的简单选择。本发明内容不旨在限制所要求保护的主题的保护范围。
所公开的实施例包括横向扩散金属氧化物半导体(LDMOS)器件和用于形成此类器件的过程，该过程使得能够减少反向恢复电荷(Qrr)，这还能够使得能够减小面积规范化导通状态电阻(RSP)。如本文中所使用的，LDMOS器件与扩散金属氧化物半导体(DMOS)器件同义。历史上地，如上所述，用于LDMOS功率器件的常规处理已经使用具有高能量接近MeV或MeV硼注入物的长/高温炉退火，以实现逐渐的或几乎均匀的垂直p主体掺杂分布，具有很小的垂直主体掺杂浓度(C)梯度(dC/dz)，例如高于通过任何0.5μm或更宽的区域的p外延区域的掺杂水平的至多2X/μm到3X/μm。
所公开的实施例认识到，由于逐渐的或几乎均匀的常规主体掺杂分布，在开关事件期间注入到主体中的少数载流子(电子)在其中被保持相对较长的时间(被称为二极管储存时间)。在二极管储存时间期间，电子通过扩散离开主体区域，以被收集在最近的反向偏压结(NBL，漏极)处，或在接地结(NBL，源极)处以减少的收集效率被收集。能够使用NPN双极性晶体管的基区渡越时间，估计二极管储存时间。考虑具有～1x1017cm-3的硼(基极)掺杂的NPN晶体管主体。在该掺杂水平下的室温电子扩散系数是21cm2/s，导致5μm宽(厚)的主体区域的基区渡越时间是6ns，或2μm宽的主体区域的基区渡越时间是1ns。常常会出现遇到在集成功率LDMOS器件中的几μm厚度(例如，3μm到5μm厚度)的p型主体区域，所以预期在ns的量级上发生Qrr有关的瞬态，这事实上是通过本公开的发明人已经观测到的。
对于在MHz范围中的DC-DC转换器开关，ns级开关瞬态能够快速地使功率转换效率恶化，其中高于80％或甚至90％的功率转换效率被认为是重要的功率产品性能指标。用于减少二极管恢复时间且由此减少Qrr的冲击的技术被认为是期望的，通过所公开的方法和从此具有渐变/梯度(graded)主体掺杂的LDMOS器件提供该技术。如本文中所使用的，“渐变(graded)主体掺杂”是指净硼掺杂分布，该净硼掺杂分布在具有高于p外延层115的净掺杂水平的净掺杂水平的至少一个0.5μm宽的主体区域中的垂直方向(dC/dz)上具有至少5X/μm的因子(at least a factor of 5X/μm)的掺杂物梯度。所公开的渐变主体掺杂可以与从高于通过用于如上所述的常规的LDMOS器件的任何0.5μm或更宽的区域的p外延区域的掺杂水平的2x/μm到3X/μm的主体区域中的硼的显著降低的dC/dz进行比较。
附图说明
现在将参考附图，没有必要按比例绘制附图，其中：
图1根据一个示例实施例是示出在用于形成在垂直方向上具有渐变主体掺杂的所公开的LDMOS器件的示例方法中的步骤的流程图。
图2A根据一个示例实施例是示出在垂直方向上具有渐变主体掺杂的示例LDMOS器件的横截面图，示例LDMOS器件具有与硅的局部氧化(LOCOS层)重叠的一部分的栅极电极。
图2B根据一个示例实施例是在垂直方向上具有渐变主体掺杂的示例LDMOS器件的顶视图，其中栅极电极处于跑道式配置中。
图3根据一个示例实施例示出在垂直方向上具有渐变主体掺杂的所公开的LDMOS器件(没有LOCOS层)的平面版本。
图4示出作为开始于用于具有常规大致平坦主体掺杂分布的已知的LDMOS器件的NDRIFT区域的顶部硅表面在垂直方向上的距离的函数的掺杂水平，以及根据一个示例实施例的作为开始于在垂直方向上具有渐变主体掺杂分布的所公开的LDMOS器件的NDRIFT区域的顶部硅表面在垂直方向上的距离的函数的掺杂水平。
图5A和图5B分别示出来自用于具有常规大致平坦的主体掺杂分布的已知的LDMOS器件和具有渐变主体掺杂的所公开的LDMOS器件的反向恢复事件的时间序列技术计算机辅助设计(TCAD)仿真的结果。
具体实施方式
参考附图描述了示例实施例，其中相同的附图标记被用于指代类似的或等价的元件。所例示的动作或事件的次序不应被认为是限制性的，因为一些动作或事件可以以不同的次序发生，和/或与其它动作或事件同时发生。另外，可以不需要一些所例示的动作或事件来实施根据本公开的方法。
再者，如本文中所使用的而没有进一步限制的术语“联接到”或“与...联接”(等)旨在描述或间接或直接电气连接。因此，如果第一器件“联接到”第二器件，则该连接能够是通过直接电气连接(其中在路径中仅有寄生效应)，或经由包括其它器件和连接的中间项目通过间接电气连接。对于间接联接，中间项目一般不会修改信号的信息，但是可以调整其电流电平、电压电平和/或功率电平。
所公开的实施例包括LDMOS制作过程且由此的LDMOS器件，LDMOS制作过程具有提供渐变主体掺杂分布的新的p主体过程流程。图1是根据一个示例实施例的示出在用于形成具有渐变主体掺杂分布的所公开的LDMOS器件的示例方法100中的步骤的流程图。使用如本领域中已知的将双极性和CMOS技术组合的BiCMOS过程流程描述方法100。虽然本文中描述了NMOS LDMOS晶体管，但是本领域中的普通技术人员很清楚，通过由p掺杂区域替换n掺杂区域，使用该信息以形成PMOS晶体管，并且反之亦然。
方法100包含新的p埋层(PBL)过程，其中在过程流程中，在完成所有显著的热步骤(即，炉循环诸如≥900℃驱动≥30分钟(例如，浅沟槽隔离(STI)衬里退火、深n阱(deepnwell，DNWELL)驱动)，因此具有显著的DT，其中DT是具有是扩散系数D和温度T的热扩散系数)之后进行PBL高能量(例如，400keV到2MeV)硼注入物。这导致将主体掺杂分布留在最终LDMOS器件中，最终LDMOS器件具有急剧的渐变主体区域，急剧的渐变主体区域还反映了如所注入的掺杂物分布，如所注入的掺杂物分布是具有是p型离子的“投射范围”的Rp的近似的高斯分布。在最终LDMOS器件中的急剧的主体掺杂梯度被认为导致在垂直/厚度方向上的内置电场(由于显著的导带能量(Ec)倾斜，所以具有电场E＝dEc/dz的梯度)，该内置电场提供电场力，该电场力有效地使少数载流子电子朝向邻近pn结快速移动，使得其显著地更快速地发生。
使用所公开的主体掺杂梯度本质上足以移除LDMOS器件的p型主体中的“平坦的”或大致上均匀地掺杂区域。例如，参看如图4中所示的具有渐变主体掺杂分布的所公开的LDMOS器件相对具有常规大致上平坦的主体掺杂分布的已知的LDMOS器件。已经发现渐变主体掺杂分布加速Qrr二极管恢复瞬态，并且避免当少数载流子拉出花费很长时间时能够发生的功率损失和寄生NPN导通。
随同具有所公开的渐变主体掺杂分布的所公开的LDMOS器件有额外的优点。因为PBL本质上不会跟随其注入物扩散，所以能够增加PBL剂量，而不会增加接近顶部半导体表面主体掺杂，这允许抑制垂直寄生NPN的增益，进一步提高LDMOS器件的安全工作区域(SOA)。由于渐变主体掺杂分布造成的内置E场抵制少数载流子电子注入，这趋向于减少在功率转换器工作期间，在开关事件期间，所注入的少数载流子电子的总数，因此，减少Qrr的量值(其减少反向恢复时间)，提高LDMOS器件的开关效率和SOA。
步骤101包括提供具有在其上的p外延层115的衬底110。P外延层115可以是约15μm到40μm厚。过程能够包括在衬底上形成第一外延层，形成覆盖式(blanket)n+埋层(NBL)111，并且然后在NBL111上形成第二外延层。衬底110一般是p+或p-衬底，通常硼掺杂从1x1016cm-3到1x1019cm-3，并且p外延层115能够具有从3x1014cm-3到3x1016cm-3的掺杂水平。衬底110和p外延层115能够都包括硅，并且还能够包括其它材料。
所公开的LDMOS器件能够包括隔离结构。例如，能够以几种方式形成外部n型罐(tank)。深沟槽(DT)是具有可选的电介质衬里和NBL，DEEPN和NBL，DNWELL和NBL，或浅n阱(shallow nwell，SNW)、BISO和NBL的一个示例。BISO是在NBL的边缘处的第二外延过程(在两个外延过程)之前(但是在将NBL更深地扩散到Si中的NBL炉驱动之后)实行的磷注入。BISO向上扩散到第二p外延中，例如，使得能够与SNW建立n罐连接，由此避免使用有时期望的DEEPN。在所有这些情况下，NBL形成n型罐的底部，并且其它元件(DT、DEEPN等)形成向上连接到顶部表面的n罐的垂直壁，此类顶部表面具有n+(来自NSD)、硅化物和接触。
步骤102包括形成包括在p外延层115内的NDRIFT离子注入的ndrift(NDRIFT)区域120。有用于NDRIFT驱动过程的选项。NDRIFT区域120提供用于如图2A中所示的LDMOS器件200的漏极扩展区域。对于LDMOS器件200，局部氧化过程随后形成LOCOS层137。然而，如图3中所示的，在其它实施例中，LDMOS器件是缺乏LOCOS层137的“平面型”器件。
步骤103包括将NDRIFT区域120的侧部的p外延层115的一部分注入包括至少第一阱离子注入，以形成DWELL(深阱)区域(DWELL)130，至少第一阱离子注入包括p型掺杂物(一般被描述为硼(硼DWELL离子注入))。然而，除硼之外，p型掺杂物能够是铟。相对于硼，为相对重原子的铟(In)具有低扩散系数的优点。在硼注入的情况下，DWELL硼注入在能量上能够类似于在BiCMOS过程中的PSD和PLDD2步骤，并且所使用的剂量一般应该足以横向形成沟道，并且抑制主体NPN效果。例如，可以使用具有20keV的能量、8x1013cm-2到3.0x1014cm-2(诸如1.5x1014cm-2)的剂量，以及小于5°的倾斜角度(诸如2°)的硼注入。
可选的DWELL n型掺杂物诸如砷或锑还能够通过以处于任何一个次序的砷和p型Dwell注入物，被添加到用于硼DWELL离子注入的相同的掩模。例如，具有剂量5x 1013cm-2到1.2x 1015cm-2(例如，8x 1014cm-2)、能量10keV到30keV(例如，15keV)以及15°离子注入倾斜角度的砷可以被用于DWELL n型掺杂物或以例如45度成角度(2或4旋转)的该注入中的一些或全部的一个特定实施例中。注入角度还能够是直的(处于0°)或0°到15°。大约15keV的砷能量能够允许砷穿透与栅极电极123相邻的栅极电介质122(例如，当5V氧化物被用于栅极电介质122时)，这通过反向掺杂减少净(net)掺杂浓度，以便减少栅极引起的寄生偏移。15°或像这样的砷注入角度能够减少沟道电压阈值(Vt)，而不会减少DWELL p型注入剂量，使得能够有Vt的同步改良并且控制寄生NPN的主体掺杂。
步骤104包括形成包括高能量p型注入的PBL(PBL注入)，以将掺杂添加到p外延层，以形成p主体区域。PBL注入能够包括处于400keV到3MeV的能量从1x1012cm-2到1x 1013cm-2的硼剂量。还可以使用如上面所提到的铟。对于低压LDMOs器件(例如，20V)，PBL注入能够是覆盖式注入，而对于更高的电压LDMOS器件(例如，＞30V)，PBL注入能够是掩膜式注入，以允许选择性的放置。
步骤105包括离子注入，以将浅p阱(SPW；SPW注入)形成在DWELL130中。步骤105能够包括都处于不同能量的两个或更多SPW注入。在图2A中被示出为SPW1 149的区域是SPW的一部分，并且能够来自BiCMOS过程，BiCMOS过程利用用于形成CMOS逻辑和5V NMOS主体扩散的常规浅p主体注入，CMOS逻辑和5V NMOS主体扩散都可以可选地被注入用于LDMOS器件，以形成用于LDMOS器件的深p主体掺杂区域。由SPW1 149提供的主体掺杂增加基极掺杂水平，以抑制由n+源极-p主体-n+漏极形成的寄生横向双极NPN。该寄生NPN限制用于LDMOS器件200的高电流工作，因为它形成安全工作区域(SOA)的边界。为可选的SNW被示出作为图2A中的SNWell155。
步骤106包括快速热处理，以首先对PBL注入、DWELL注入(如果之前没有可选地进行驱动)和SPW注入一起作活化处理。如本文中所使用的快速热处理(RTP)是指半导体制造过程，该半导体制造过程在小于5分钟(通常为几秒或更少)的时间标度上将半导体(例如，硅)晶片加热到高温(至少950℃)。在冷却期间，晶片温度缓慢降低，以防止由于热冲击而造成的错位和晶片破裂。常常通过高强度灯或激光器取得此类快速加热速率。快速热退火(RTA)是RTP的子集，并且闪光灯退火是RTP的示例。例如，在一个特定实施例中，在1到4分钟内大约1000℃处的RTA可以被用于步骤106。
步骤107包括形成栅极叠层，形成栅极叠层包括在p主体区域140上形成与p主体区域140和NDRIFT区域120之间的结的相应侧相邻的和在p主体区域140和NDRIFT区域120之间的结的相应侧上的栅极介电层122，然后在栅极介电层122上形成图案化的栅极电极123。栅极介电层122能够是包括二氧化硅的5V栅极电介质，其为大约10nm到15nm厚。还可能使用和3nm的二氧化硅一样薄的栅极电介质(或稍微更薄但具有比大约3.9的二氧化硅的介电常数更高的介电常数的氮氧化硅(SION)栅极电介质)。多晶硅是用于栅极电极123的一个示例栅极电极材料。然而，金属栅极或基于CMOS的替换栅极过程还能够被用于提供栅极电极123。
步骤108包括在栅极电极的侧壁上形成侧壁间隔物(spacer)138。间隔物材料的薄层还可选地被示出在栅极电极123的顶部上。在栅极电极123的顶部上的间隔物材料可以存在或可以不存在。前金属电介质(PMD)139被示出包括在间隔物138上。
在一个实施例中，侧壁间隔物包括氮化硅。步骤109包括在DWELL 130中形成源极区域148，并且在NDRIFT区域120中形成漏极区域145。一般跟随着接触(例如，可选的硅化物、前金属电介质和通孔)和金属化处理。
一般有三种不同类型的LDMOS器件用于功率转换器应用，诸如用于在一个特定应用中的半桥降压DC/DC转换器。低侧LDMOS晶体管具有连接到接地的源极和主体区域，所以此类LDMOS器件能够在p外延115中工作而不用任何隔离(即，没有深沟槽(DT)、没有NBL，并且没有DEEPN沉降片(sinker))。另一个LDMOS器件是构建于n型罐中的ISO LDMOS晶体管。ISO端子为n罐，并且其能够与源极/背栅极区域和漏极分开偏压。然而类似于ISO LDMOS晶体管，构建用于高侧应用的另一个LDMOS器件，但是ISO和漏极(往往通过金属1(MET1))被电连接在一起。对于这些类型的LDMOS器件中的每个，一般需要增加开关频率，以减少外部无源部件(诸如电感器)的尺寸，同时维持在集成功率FET中的低功率消耗。这涉及减少功率FET的开关寄生Q栅极和C漏极，并且减少了导通状态电阻RSP，由所公开的LDMOS器件提供。
图2A是根据一个示例实施例的示出具有渐变主体掺杂分布的示例LDMOS器件的横截面图。图2B是根据一个示例实施例的具有渐变主体掺杂分布的示例LDMOS器件200’的顶视图，其中栅极电极处于跑道式配置中。隔离罐240被示出做LDMOS器件200’的框架，LDMOS器件200’如上所述能够包括与提供将p外延115的顶部表面联接到NBL 111的垂直壁的n+沉降片一起的NBL。在背栅极/主体接触142下面的背栅极/主体接触区域142a是集成的背栅极接触，其在DWELL 130的表面处。背栅极/主体接触区域142a能够通过添加用于CMOS部分的p+SD(PSD)注入，被形成在DWELL 130内，CMOS部分被非常重地掺杂(p+，硼)。为了与源极148低阻抗接触，通过NSD注入覆盖没有覆盖有PSD的源极/背栅极区域的面积，在常规几何形状上，一个布置具有多个背栅极PSD条纹或正方形。背栅极/主体接触区域142a允许p型主体区域(DWELL 130和p主体140)通过硅化物层欧姆短接到n+源极148。在图2A中还示出源极接触143、漏极接触144和栅极接触147。
图3根据一个示例实施例示出具有渐变主体掺杂分布的所公开的LDMOS器件(没有图2A中所示的LOCOS层137)的平面版本。对于LDMOS器件300，在栅极电极123下面的栅极电介质122的电介质厚度本质上是恒定的。用于CMOS电路的p型源极-漏极注入(PSD)可以可选地被图案化，以提供形成为与NSD+DWELL区域相邻的背栅极/主体接触，以减少寄生NPN的p主体的基极电阻，进一步抑制主体NPN动作。DWELL掩模可以可选地延伸跨过背栅极/主体接触142a，或其可以停止与PSD边缘相邻。PLDD2(被用于形成5V PMOS的纯p型SD延伸注入)还可以可选地被添加到背栅极/主体接触142a，可选地部分地延伸到图2A中的n型DWELL 135中，以加强p型主体掺杂，因此进一步抑制主体NPN动作。
示例
通过以下具体示例进一步例示了所公开的实施例，以下具体示例不应该被解释为以任何方式限制本公开的范围或内容。
图4示出作为开始于用于具有常规主体掺杂分布的已知的LDMOS器件的NDRIFT区域的顶部硅表面在垂直方向上的距离的函数的掺杂，以及根据一个示例实施例的作为开始于在垂直方向上具有渐变主体掺杂分布的所公开的LDMOS器件的NDRIFT区域的顶部硅表面在垂直方向上的距离的函数的掺杂。能够看到用于已知的LDMOS器件的PBL区域中的掺杂是几乎恒定的，同时能够看到用于所公开的LDMOS器件的PBL区域中的掺杂为相对剧烈渐变。例如，接近PBL峰值，能够看到用于所公开的LDMOS器件的掺杂物梯度在大约PBL峰值的1μm范围内接近10X。
图5A和图5B分别示出来自用于具有常规大致平坦的主体掺杂分布的已知的LDMOS器件和具有渐变主体掺杂分布的所公开的LDMOS器件的反向恢复事件的时间序列仿真的结果。仿真的正偏电流被注入到每个LDMOS器件(每个LDMOS器件用少数载流子电子充满p主体区域)中，然后，每个LDMOS器件被突然切断。在切断正偏注入电流之后，随着p主体中的电子朝向漏极扩散回去且跨过pn结，反向电流开始流动。这是由I_漏极证明的二极管恢复电流，该二极管恢复电流的时间积分被称为反向恢复电荷Qrr。能够看到具有渐变主体掺杂的所公开的LDMOS器件提供显著降低的恢复电流，并且因此与已知的LDMOS器件相比，提高Qrr性能，与所公开的LDMOS器件相比，已知的LDMOS器件的Qrr是显著地更慢出现。
所公开的实施例能够被用于形成半导体晶片，半导体晶片可以被集成在各种组装流程中，以形成各种不同的器件和相关的产品。半导体晶片可以包括在其中的各种元件和/或在其上的层，包括阻挡层、介电层、器件结构、有源元件和无源元件，无源元件包括源极区域、漏极区域、位线、基极、发射极、集电极、导电线、导电通孔等。而且，能够由各种过程(包括双极性、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS和MEMS)形成半导体晶片。
本公开相关的领域中的这些技术人员将理解，在所要求保护的范围内，很多其它实施例和实施例的变化是可能的，并且在不脱离本公开的范围的情况下，可以对所描述的实施例作出另外的添加、删除、替换和修改。

Claims (19)

1.一种形成横向扩散金属氧化物半导体器件即LDMOS器件的方法，包括：
在衬底上的p型层中形成第一n型区域；
在形成所述第一n型区域之后，通过以下步骤形成具有垂直渐变掺杂的p主体区域：
用第一p型注入物注入所述p型层的在所述第一n型区域侧部的第一部分，以形成DWELL区域；
用第二p型注入物注入所述p型层的第二部分，所述第二部分包括所述第一部分；以及
用第三p型注入物注入到所述DWELL区域中，以在所述p主体区域中在所述DWELL区域下方形成p阱区域；
快速热处理即RTP用于首先对所述第一p型注入物、所述第二p型注入物和所述第三p型注入物一起作活化处理；
形成栅极叠层，所述形成栅极叠层包括在所述p主体区域的一部分上方形成与所述第一n型区域的结的相应侧相邻的和在所述第一n型区域的结的相应侧上的栅极介电层，并且然后在所述栅极介电层上形成图案化的栅极电极；
在所述栅极电极的侧壁上形成侧壁间隔物；
在所述DWELL区域内形成源极区域，并且在所述第一n型区域内形成漏极区域，
其中所述p主体区域包括为至少一个0.5μm宽的一部分，所述一部分具有高于所述p型层的掺杂水平的净p型掺杂水平和至少5倍/μm的净p型掺杂分布梯度。
2.根据权利要求1所述的方法，其中在形成所述栅极叠层之前形成所述DWELL区域。
3.根据权利要求1所述的方法，其中所述第二p型注入物包括处于从400KeV到3MeV的能量、从1x1012cm-2到1x1013cm-2的剂量的硼。
4.根据权利要求1所述的方法，还包括将n型掺杂物注入到所述DWELL区域中，以形成n型DWELL区域。
5.根据权利要求1所述的方法，其中所述第二p型注入物包括铟注入物即In注入物。
6.根据权利要求4所述的方法，其中注入所述n型掺杂物包括具有从10KeV到30KeV的能量和从3x1013cm-2到1.2x1015cm-2的剂量的砷。
7.根据权利要求1所述的方法，其中所述RTP包括快速热退火即RTA。
8.根据权利要求1所述的方法，还包括形成隔离罐，所述形成隔离罐包括在形成所述第一n型区域之前在所述p型层中形成n+埋层即NBL，以及提供将所述p型层的顶部表面联接到所述NBL的垂直壁的n+沉降片。
9.根据权利要求1所述的方法，还包括在所述第一n型区域的一部分上方形成局部氧化层即LOCOS层，其中所述栅极电极在所述LOCOS层的一部分上。
10.根据权利要求1所述的方法，其中所述第二p型注入物是覆盖式注入物。
11.一种横向扩散金属氧化物半导体器件即LDMOS器件，包括：
衬底，所述衬底具有在其上的p型层；
p主体区域，所述p主体区域在所述p型层中；
n型区域，所述n型区域在所述p主体区域内，以提供漏极扩展区域；
栅极叠层，所述栅极叠层包括在所述p主体区域的一部分上方的与所述n型区域的结的相应侧相邻的和在所述n型区域的结的相应侧上的栅极介电层，以及在所述栅极介电层上的图案化的栅极电极；
DWELL区域，所述DWELL区域在所述p主体区域内；
p型阱区域，所述p型阱区域在所述p主体区域中在所述DWELL区域下方；
侧壁间隔物，所述侧壁间隔物在所述栅极电极的侧壁上，以及
源极区域和漏极区域，所述源极区域在所述DWELL区域内，所述漏极区域在所述n型区域内，
其中所述p主体区域包括具有至少5倍/μm的净p型掺杂分布梯度的一部分。
12.根据权利要求11所述的LDMOS器件，其中所述衬底包括硅。
13.根据权利要求11所述的LDMOS器件，其中所述p主体区域的所述一部分包括铟即In。
14.根据权利要求11所述的LDMOS器件，其中所述栅极介电层包括二氧化硅或氧氮化硅即SiON，并且所述栅极电极包括多晶硅。
15.根据权利要求11所述的LDMOS器件，还包括隔离罐，所述隔离罐包括在所述p型层中的n+埋层即NBL和提供将所述p型层的顶部表面联接到所述NBL的垂直壁的n+沉降片。
16.根据权利要求11所述的LDMOS器件，还包括在所述n型区域的一部分上方的局部氧化层即LOCOS层，其中所述栅极电极在所述LOCOS层的一部分上。
17.根据权利要求11所述的LDMOS器件，其中所述LDMOS器件是平面型器件。
18.根据权利要求11所述的LDMOS器件，其中所述栅极电极是被布局为跑道式几何形状的栅极。
19.根据权利要求11所述的LDMOS器件，还包括在所述DWELL区域的表面处的集成背栅极/主体接触区域。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9825128B2 (en) 2015-10-20 2017-11-21 Maxpower Semiconductor, Inc. Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings
US9887288B2 (en) * 2015-12-02 2018-02-06 Texas Instruments Incorporated LDMOS device with body diffusion self-aligned to gate
US9905688B2 (en) 2016-01-28 2018-02-27 Texas Instruments Incorporated SOI power LDMOS device
US10424647B2 (en) * 2017-10-19 2019-09-24 Texas Instruments Incorporated Transistors having gates with a lift-up region
US11094806B2 (en) * 2017-12-29 2021-08-17 Texas Instruments Incorporated Fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region
JP7129408B2 (ja) * 2018-04-16 2022-09-01 ヌヴォトンテクノロジージャパン株式会社 半導体装置
US10461182B1 (en) 2018-06-28 2019-10-29 Texas Instruments Incorporated Drain centered LDMOS transistor with integrated dummy patterns
US11374124B2 (en) 2018-06-28 2022-06-28 Texas Instruments Incorporated Protection of drain extended transistor field oxide
US11152505B2 (en) 2018-06-28 2021-10-19 Texas Instruments Incorporated Drain extended transistor
TWI673880B (zh) * 2018-11-21 2019-10-01 新唐科技股份有限公司 橫向擴散金氧半導體裝置
US11322609B2 (en) * 2019-11-29 2022-05-03 Taiwan Semiconductor Manufacturing Company Ltd. High voltage device
CN111640786B (zh) * 2020-06-12 2021-11-23 电子科技大学 一种具有多沟槽的ligbt器件
US11437466B2 (en) * 2020-08-11 2022-09-06 Taiwan Semiconductor Manufacturing Company Limited Avalanche-protected transistors using a bottom breakdown current path and methods of forming the same
US11721779B2 (en) 2021-04-30 2023-08-08 Texas Instruments Incorporated Photodetector and optical sensing system
US11594630B2 (en) * 2021-05-25 2023-02-28 Texas Instruments Incorporated Rugged LDMOS with reduced NSD in source

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6593621B2 (en) 2001-08-23 2003-07-15 Micrel, Inc. LDMOS field effect transistor with improved ruggedness in narrow curved areas
US7125777B2 (en) * 2004-07-15 2006-10-24 Fairchild Semiconductor Corporation Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)
US8692324B2 (en) * 2005-07-13 2014-04-08 Ciclon Semiconductor Device Corp. Semiconductor devices having charge balanced structure
TWI347675B (en) * 2006-12-07 2011-08-21 Vanguard Int Semiconduct Corp Laterally diffused metal oxide semiconductor transistors
US7713825B2 (en) 2007-05-25 2010-05-11 Texas Instruments Incorporated LDMOS transistor double diffused region formation process
US7736983B2 (en) 2008-01-10 2010-06-15 Texas Instruments Incorporated High threshold NMOS source-drain formation with As, P and C to reduce damage
US8174071B2 (en) 2008-05-02 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage LDMOS transistor
US8159029B2 (en) * 2008-10-22 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage device having reduced on-state resistance
CN102088030B (zh) * 2009-12-04 2012-10-10 无锡华润上华半导体有限公司 横向双扩散金属氧化物半导体场效应管及其制造方法
US20110241113A1 (en) * 2010-03-31 2011-10-06 Zuniga Marco A Dual Gate LDMOS Device with Reduced Capacitance
US8304830B2 (en) * 2010-06-10 2012-11-06 Macronix International Co., Ltd. LDPMOS structure for enhancing breakdown voltage and specific on resistance in biCMOS-DMOS process
US8575692B2 (en) * 2011-02-11 2013-11-05 Freescale Semiconductor, Inc. Near zero channel length field drift LDMOS
US8716791B1 (en) * 2011-08-11 2014-05-06 Maxim Integrated Products, Inc. LDMOS with corrugated drift region
US9111992B2 (en) * 2011-09-13 2015-08-18 Globalfoundries Singapore Pte. Ltd. Semiconductor device including an n-well structure
US9236472B2 (en) * 2012-04-17 2016-01-12 Freescale Semiconductor, Inc. Semiconductor device with integrated breakdown protection
CN102790088A (zh) * 2012-07-20 2012-11-21 昆山华太电子技术有限公司 一个击穿电压可以调整rf-ldmos器件
US8772870B2 (en) * 2012-10-31 2014-07-08 Freescale Semiconductor, Inc. LDMOS device with minority carrier shunt region
US9245997B2 (en) * 2013-08-09 2016-01-26 Magnachip Semiconductor, Ltd. Method of fabricating a LDMOS device having a first well depth less than a second well depth
US20150048452A1 (en) * 2013-08-16 2015-02-19 Macronix International Co., Ltd. Ultra-high voltage semiconductor having an isolated structure for high side operation and method of manufacture
US9312380B2 (en) * 2014-03-19 2016-04-12 Macronix International Co., Ltd. Semiconductor device having deep implantation region and method of fabricating same
US9460926B2 (en) * 2014-06-30 2016-10-04 Alpha And Omega Semiconductor Incorporated Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions
CN204651326U (zh) * 2015-06-05 2015-09-16 杭州士兰微电子股份有限公司 高压半导体器件

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US20170179260A1 (en) 2017-06-22

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