CN106885929B - Measuring device with double-ring ALC circuit - Google Patents
Measuring device with double-ring ALC circuit Download PDFInfo
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- CN106885929B CN106885929B CN201510939882.2A CN201510939882A CN106885929B CN 106885929 B CN106885929 B CN 106885929B CN 201510939882 A CN201510939882 A CN 201510939882A CN 106885929 B CN106885929 B CN 106885929B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention provides a measuring device with a dual-loop ALC circuit, comprising: the input end of the second adjustable radio frequency attenuator is the input end of the double-loop ALC circuit, and the output end of the second adjustable radio frequency attenuator is connected with the input end of the first adjustable radio frequency attenuator; the output end of the first adjustable radio frequency attenuator is connected with the input end of the power divider; two output ends of the power divider are respectively connected with the output end of the double-loop ALC circuit and the input end of the detector; the output end of the detector is connected with the input end of the ADC module; the output end of the analog-to-digital conversion module is connected with the input end of the digital chip; two output ends of the digital chip are respectively connected with input ends of the first DAC module and the second DAC module; the output end of the first DAC module is connected with the adjusting end of the first adjustable radio frequency attenuator; and the output end of the second DAC module is connected with the adjusting end of the second adjustable radio frequency attenuator. The invention can meet the requirements of large adjustable range, high resolution and low jitter of the signal source ALC.
Description
Technical Field
The invention relates to the technical field of signal testing and measuring, in particular to a measuring device with a double-ring ALC circuit.
Background
The radio frequency signal source is a common device in the field of measurement and test. The radio frequency signal source is mainly used for generating a radio frequency signal with a certain frequency range and amplitude range and used as excitation or reference of the device to be tested. And can also output various Modulation signals, such as FM (Frequency Modulation), AM (amplitude Modulation), PM (Phase Modulation), IQ, Pulse, etc., which provide a basis for debugging communication equipment. The amplitude accuracy, the locking time and the stability of the output signal of the radio frequency signal source are one of the important indexes of the radio frequency signal source, and these indexes are generally realized by an ALC circuit (Automatic Level Control). In addition, the output signal phase noise and spurs are also important indicators of the rf signal source, and noise (or jitter) in the ALC loop may also affect this performance. The amplitude of the output signal of the device also needs to be properly adjusted, and the amplitude of the signal inside the signal source also changes within a certain range. The range and minimum resolution that ALC can lock are also important components of ALC performance.
Most ALCs consist of one complete loop, with mainly 3 blocks "detect", "compare", and "adjust". And during normal operation (ALC on), the ALC on detects the amplitude of the output signal in real time, compares the detected result with a set amplitude value, and dynamically adjusts the attenuation (or gain) of the loop according to the comparison result until the amplitude of the output signal is equal to the set value. Noise (or jitter) in the ALC loop will cause the output attenuation of the "adjustment" block to jitter within a certain range, and this jitter will be superimposed on the input signal in the form of noise or spurs, causing a certain change in the phase noise or spurs of the final output signal.
The ALC loop has two realization modes of analog and digital, and the analog ALC loop has high speed and low noise but is not intelligent enough in control; the operability and the function expansion capability of the digital ALC loop are strong, but the noise is high, and the running speed is low (the locking time is long).
Patent CN201020696938.9 describes a combined analog and digital dual loop ALC system that adds a digital regulation circuit between the analog ALC loop "detection" and "comparison" blocks, in order to desirably utilize the advantages of both the analog ALC loop and the digital ALC loop. The digital analog-to-digital converter is mainly designed to convert the output of a detection module (a level detection circuit) into digital quantity while simulating the normal operation of an ALC (adaptive logic level) loop, and adjust the reference voltage of a comparison module according to the parameter. The scheme takes analog ALC as a main body, and the capacity of adjusting the reference voltage according to the detection voltage is increased.
For most analog ALC loops, analog devices with low enough noise can be selected, so that nearby noise or stray introduced by ALC is small enough, and the performance of an output signal is not affected basically. For digital ALC, the jitter of the "tuning" block is large due to the limitation of the resolution of the digital-to-analog conversion DAC, the jitter frequency is related to the bandwidth of the ALC loop and is difficult to be eliminated by using a filter, and the most direct method for solving the problem is to improve the resolution of the DAC and reduce the jitter amplitude to an acceptable range. For most ALCs, the lock time of the loop is another important criterion, and the update speed of the ADC and DAC directly affects the lock time of the loop. Shorter locking time requires faster updating speed, but the DAC with fast updating speed and high resolution has higher cost, and the high-speed DAC which can meet the adjustable range and precision requirement of the signal source ALC is difficult to find; the use of multiple high-speed DAC cascades increases resolution but adds additional cost and may have switching point jitter problems due to control signal asynchrony.
Disclosure of Invention
The embodiment of the invention provides a measuring device with a double-loop ALC circuit, which can meet the requirements of a signal source ALC on large adjustable range, high resolution and low jitter.
The dual-loop ALC circuit includes a first ALC circuit and a second ALC circuit; the first ALC circuit comprises a first adjustable radio frequency attenuator, a power divider 102, a detector 103, an analog-to-digital conversion module 104, a digital chip 105 and a first digital-to-analog conversion module 106; the second ALC circuit comprises a power divider 102, a detector 103, an analog-to-digital conversion module 104, a digital chip 105, a second adjustable radio frequency attenuator and a second digital-to-analog conversion module 108;
the input end of the second adjustable radio frequency attenuator is used as the input end of the double-loop ALC circuit, and the output end of the second adjustable radio frequency attenuator is connected with the input end of the first adjustable radio frequency attenuator and is used for attenuating the amplitude of the input radio frequency signal 1A;
the output end of the first adjustable radio frequency attenuator is connected with the input end of the power divider 102, and is used for further attenuating the amplitude of the input radio frequency signal 1A;
the power divider 102 divides the input radio frequency signal 1A after twice amplitude decay into a first output radio frequency signal 1B and a second output radio frequency signal; a first output end of the power divider 102 is used as an output end of the dual-loop ALC circuit, and is used for outputting a first output radio frequency signal 1B; a second output end of the power divider 102 is connected with an input end of the detector 103, and is used for outputting a second output radio frequency signal to the detector 103;
the output end of the detector 103 is connected with the input end of the analog-to-digital conversion module 104, and is used for detecting the second output radio frequency signal to obtain a detection voltage;
the output end of the analog-to-digital conversion module 104 is connected with the input end of the digital chip 105, and is used for performing analog-to-digital conversion on the detection voltage to obtain a digitized detection voltage;
a first output end of the digital chip 105 is connected with an input end of a first digital-to-analog conversion module 106, and a second output end is connected with an input end of a second digital-to-analog conversion module 108;
the digital chip 105 is used for determining the control voltage of the adjustable radio frequency attenuator according to the digitized detection voltage, and when the control voltage of the adjustable radio frequency attenuator is determined, the first ALC circuit works; when the control voltage of the second adjustable radio frequency attenuator is determined, the second ALC circuit works;
the output end of the first digital-to-analog conversion module 106 is connected to the adjusting end of the first adjustable radio frequency attenuator, and is configured to perform digital-to-analog conversion on the control voltage of the first adjustable radio frequency attenuator;
the output end of the second digital-to-analog conversion module 108 is connected to the adjusting end of the second adjustable rf attenuator, and is configured to perform digital-to-analog conversion on the control voltage of the second adjustable rf attenuator.
In one embodiment, the digital chip 105 includes a comparison module 201, an error determination module 202, a first comparison integrator 203, and a second comparison integrator 205;
the input end of the comparison module 201 is used as the input end of the digital chip 105, and the output end of the comparison module 201 is connected with the input end of the error judgment module 202, and is used for comparing the digitized detection voltage with the reference voltage to obtain the current error voltage;
a first output end of the error judgment module 202 is connected with an input end of the first comparison integrator 203, a second output end of the error judgment module 202 is connected with an input end of the second comparison integrator 205, and the error judgment module is used for judging the magnitude of the current error voltage and outputting the current error voltage to the first comparison integrator 203 if the current error voltage is greater than a preset error value; if the current error voltage is smaller than the preset error value, the current error voltage is output to the second comparator-integrator 205;
the output end of the first comparison integrator 203 is used as the first output end of the digital chip 105, and is used for integrating the current error voltage;
the output terminal of the second comparator-integrator 205 serves as a second output terminal of the digital chip 105, and is used for integrating the current error voltage.
In one embodiment, the digital chip 105 further comprises a zero module 301 and a first logarithmic amplifier 302;
the input end of the zero module 301 serves as the input end of the digital chip 105, and the output end of the zero module 301 is connected with the input end of the first logarithmic amplifier 302 and is used for calibrating the zero point of the digitized detection voltage;
the output end of the first logarithmic amplifier 302 is connected to the input end of the comparison module 201, and is used for logarithmically amplifying the digitized detection voltage after zero calibration.
In one embodiment, the digital chip 105 further comprises a zero module 301, a linearity compensation module 402, a sampling filter module 403, and a square-on-square module 404;
the input end of the zero module 301 serves as the input end of the digital chip 105, and the output end of the zero module 301 is connected with the input end of the linearity compensation module 402, and is used for calibrating the zero point of the digitized detection voltage;
the output end of the linearity compensation module 402 is connected to the input end of the sampling filter module 403, and is configured to compensate for nonlinearity of the digitized detection voltage after zero calibration;
the output end of the sampling filter module 403 is connected to the input end of the square-on-square module 404, and is configured to perform oversampling on the digitized detection voltage after the nonlinear compensation is performed;
the output end of the square-on-square module 404 is connected to the input end of the comparison module 201, and is used for reducing the oversampled detected voltage from power amplitude to voltage amplitude.
In one embodiment, the first and second comparison integrators 203, 205 each comprise an amplifier and an accumulator;
the input end of the amplifier is connected with the output end of the error judgment module 202 and is used for amplifying the current error voltage;
the input end of the accumulator is connected with the output end of the amplifier, and the output end of the accumulator is used as the output end of the digital chip 105 and used for accumulating the amplified current error voltage to obtain the final error voltage.
In one embodiment, the digital chip 105 further comprises a first processing module 204 and a second processing module 206;
the input end of the first processing module 204 is connected to the output end of the first comparison integrator 203, and the output end of the first processing module 204 is used as the first output end of the digital chip, and is used for performing corresponding processing on the final error voltage integrated by the first comparison integrator 203;
the input end of the second processing module 206 is connected to the output end of the second comparison integrator 205, and the output end of the second processing module 206 serves as the second output end of the digital chip, and is used for performing corresponding processing on the final error voltage integrated by the second comparison integrator 205.
In one embodiment, the first processing module 204 includes a first switch 308, an error voltage module 309, a preset voltage module 310, a first adder, and a voltage conversion module 311;
when the ALC circuitry is operating normally, the first switch 308 is closed; when the ALC circuit operates open-loop, the first switch 308 is open;
the error voltage module 309 is configured to store a preset error voltage or a final error voltage integrated by the first comparing integrator 203;
the preset voltage module 310 is used for storing preset voltage;
the first adder is used for adding the final error voltage and the preset voltage to obtain the control voltage of the first adjustable radio frequency attenuator;
the input end of the voltage conversion module 311 is connected to the output end of the adder, and is configured to modify the nonlinearity between the attenuation of the first adjustable rf attenuator and the control voltage.
In one embodiment, the first processing module 204 further comprises a second logarithmic amplifier 413;
the input end of the second logarithmic amplifier 413 is connected to the output end of the first adder, and the output end of the second logarithmic amplifier 413 is connected to the input end of the voltage conversion module 311, and is configured to perform logarithmic amplification on the control voltage of the first adjustable radio frequency attenuator.
In one embodiment, the second processing module 206 includes a second switch 314, a second adder, and an optional switch 317;
the error voltage integrated by the first comparator-integrator 203 is added to the test voltage 315 through the second switch 314 and then is used as the input of the selectable switch 317; when the double-loop ALC normally operates, the selectable switch 317 is connected with the second ALC circuit, and the control voltage of the second adjustable radio frequency attenuator is output; when the AM is on, the second adjustable radio frequency attenuator is used to implement AM modulation.
In one embodiment, the comparison module 201 employs a subtractor.
In the embodiment of the invention, two sets of integration modules are built inside a digital chip to form two ALC circuits: the first ALC circuit uses a first adjustable radio frequency attenuator to carry out preliminary adjustment on the amplitude of an output signal, so that the amplitude error of the output signal is kept in a small range; the second digital ALC loop further corrects the residual amplitude of the output signal by using a second adjustable radio frequency attenuator, so that lower error jitter is realized, and the requirements of a signal source ALC on large adjustable range, high resolution and low jitter are met.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of a measurement apparatus with dual-loop ALC circuits according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an internal structure of a digital chip according to an embodiment of the present invention;
FIG. 3 is a diagram of the internal hardware connection of a log-mode dual-ring ALC digital chip according to an embodiment of the present invention;
FIG. 4 is a diagram of the internal hardware connection of a linear-mode dual-loop ALC digital chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
In the radio frequency signal source, the AM function is mostly required to be realized. AM may be implemented independently of ALC using additional attenuators and control units to increase control flexibility and improve AM and ALC performance. Typically, the AM attenuator is in an idle state when the AM is off. At this time, the characteristic that the attenuation amount of the AM attenuator changes slowly can be utilized to construct a double-loop digital ALC, so that the resolution of the attenuation amount of the equipment is improved, and the DAC resolution of the ALC is equivalently improved.
The invention provides a measuring device of a double-loop ALC circuit, which aims at the problem that digital ALC has high requirements on DAC update rate and resolution and combines the characteristics of a radio frequency signal source. The scheme uses two independent attenuators to construct two ALC loops, wherein the adjustable range of one attenuator is larger so as to meet the requirement of the ALC adjustable range; and the other attenuator has higher adjustable attenuation resolution and is used for meeting the requirements of high resolution and low jitter of the ALC.
FIG. 1 is a schematic diagram of a measurement apparatus having a dual-loop ALC circuit according to an embodiment of the present invention, as shown in FIG. 1, the dual-loop ALC circuit includes a first ALC circuit and a second ALC circuit; the first ALC circuit comprises a first adjustable radio frequency attenuator 101, a power divider 102, a detector 103, an analog-to-digital conversion module 104, a digital chip 105 and a first digital-to-analog conversion module 106; the second ALC circuitry includes a power splitter 102, a detector 103, an analog-to-digital conversion block 104, a digital chip 105, a second adjustable radio frequency attenuator 107, and a second digital-to-analog conversion block 108.
The input end of the second adjustable radio frequency attenuator 107 is used as the input end of the dual-loop ALC circuit, and the output end of the second adjustable radio frequency attenuator 107 is connected with the input end of the first adjustable radio frequency attenuator 101, and is used for attenuating the amplitude of the input radio frequency signal 1A;
the output end of the first adjustable radio frequency attenuator 101 is connected with the input end of the power divider 102, and is used for further attenuating the amplitude of the input radio frequency signal 1A;
the power divider 102 divides the input radio frequency signal 1A after twice amplitude decay into a first output radio frequency signal 1B and a second output radio frequency signal; a first output end of the power divider 102 is used as an output end of the dual-loop ALC circuit, and is used for outputting a first output radio frequency signal 1B; a second output end of the power divider 102 is connected with an input end of the detector 103, and is used for outputting a second output radio frequency signal to the detector 103;
the output end of the detector 103 is connected with the input end of the analog-to-digital conversion module 104, and is used for detecting the second output radio frequency signal to obtain a detection voltage;
the output end of the analog-to-digital conversion module 104 is connected with the input end of the digital chip 105, and is used for performing analog-to-digital conversion on the detection voltage to obtain a digitized detection voltage;
a first output end of the digital chip 105 is connected with an input end of a first digital-to-analog conversion module 106, and a second output end is connected with an input end of a second digital-to-analog conversion module 108;
the digital chip 105 is used for determining the control voltage of the adjustable radio frequency attenuator according to the digitized detection voltage, and when the control voltage of the first adjustable radio frequency attenuator 101 is determined, the first ALC circuit works; when determined as the control voltage for the second adjustable radio frequency attenuator 107, the second ALC circuitry operates;
the output end of the first digital-to-analog conversion module 106 is connected to the adjusting end of the first adjustable radio frequency attenuator 101, and is configured to perform digital-to-analog conversion on the control voltage of the first adjustable radio frequency attenuator 101;
the output end of the second digital-to-analog conversion module 108 is connected to the adjusting end of the second adjustable rf attenuator 107, and is configured to perform digital-to-analog conversion on the control voltage of the second adjustable rf attenuator 107.
In particular, the first adjustable rf attenuator 107 and the second adjustable rf attenuator 101 may be used, that is, the positions of the first adjustable rf attenuator and the second adjustable rf attenuator may be interchanged, so that the operation of the dual-loop ALC circuit is not affected.
In specific implementation, the working principle of the dual-loop ALC circuit is as follows:
the input rf signal 1A passes through two adjustable rf attenuators 107 and 101 and the power divider 102 in sequence, and then outputs an rf signal 1B. Wherein the power divider 102 divides a small portion of the rf signal to the detector 103 for extracting the amplitude information of the output rf signal 1B. The output signal of the detector 103 is digitized by the ADC104 and enters the digital chip 105, and the digital chip calculates the control voltages 1D and 1E of the two attenuators, and controls the corresponding adjustable rf attenuators 101 and 107 after being output by the DACs 106 and 108, respectively. The adjustable attenuation range of the adjustable radio frequency attenuator 101 is large, but the minimum step is also large; the adjustable range of the adjustable radio frequency attenuator 107 is smaller, but the minimum step size is also smaller. The two adjustable radio frequency attenuators can be attenuators with different structures or types, and can also be attenuators with the same structures but different working points.
Fig. 2 is a schematic diagram of an internal structure of a digital chip according to an embodiment of the present invention, and as shown in fig. 2, the digital chip 105 includes a comparing module 201, an error determining module 202, a first comparing integrator 203, a second comparing integrator 205, a first processing module 204, and a second processing module 206;
wherein, the input end of the comparing module 201 is used as the input end of the digital chip 105, and the output end of the comparing module 201 is connected with the input end of the error judging module 202; a first output end of the error judgment module 202 is connected with an input end of the first comparison integrator 203, and a second output end of the error judgment module 202 is connected with an input end of the second comparison integrator 205; the input end of the first processing module 204 is connected to the output end of the first comparison integrator 203, the output end of the first processing module 204 serves as the first output end of the digital chip, the input end of the second processing module 206 is connected to the output end of the second comparison integrator 205, and the output end of the second processing module 206 serves as the second output end of the digital chip.
The working principle of the digital chip is as follows:
the digitized detection voltage is compared with a set reference DAC through a comparison module 201 to obtain an error voltage; the error judgment module 202 judges the current error voltage, the larger current error enters the first comparison integrator 203 for accumulation, the integrated output is output after being subjected to other processing such as nonlinear compensation and the like by the first processing module 204, and the first adjustable radio frequency attenuator 101 is controlled; the smaller current error enters another second comparison integrator 205 for accumulation, and the integrated output is output after being subjected to other processing such as nonlinear compensation by a second processing module 206, so as to control the second adjustable radio frequency attenuator 107.
The error determination module 202 may divide the current error into two paths for output in real time, or may send all the errors within a certain time range to a specific channel according to the detected error rule. The larger current error and the smaller current error are determined according to actual conditions.
The first processing module 204 and the second processing module 206 are associated with specific circuitry, and may not be present in practice. At this time, the output terminal of the first comparison integrator 203 is used as the first output terminal of the digital chip 105; the output of the second comparator-integrator 205 serves as a second output of the digital chip 105.
In specific implementation, the double-loop ALC uses two adjustable attenuators, and two sets of integration modules are built inside a digital chip to form two ALC loops. One of the ALC loops (coarse ALC loop) uses the first adjustable radio frequency attenuator 101 with large adjustable range and low adjustable precision to primarily adjust the amplitude of the output signal, so that the amplitude error of the output signal is kept in a small range. The other ALC loop (fine-tuning ALC loop) uses the second adjustable radio frequency attenuator 107 with small adjusting range and high resolution to further correct the residual amplitude error and realize lower error jitter. The two ALC loops can operate simultaneously or in different time periods according to the error voltage distribution condition. When the ALC just starts to operate or is out of lock, the deviation of the amplitude of the output signal and the set value is large, and the operation of the ALC loop is roughly adjusted. When the amplitude error is smaller than a certain degree, a small error smaller than the judgment condition occurs, and the fine-tuning ALC loop starts to operate. When the amplitude error is small, the detected error basically enters the fine-tuning ALC loop, and the output voltage of the coarse-tuning ALC loop may remain unchanged for a long time. The error determination mode may also be set so that the output of one loop of the two ALC loops remains unchanged while the other loop is operating. When the double loops work simultaneously, the alternative conditions of the loops are not needed to be set, but the locking ranges and the adjusting rates of the two ALC loops are needed to be designed, so that the oscillation caused by the fact that the two loops run in opposite directions simultaneously is avoided. When the double loops work alternately, the oscillation problem between the two loops is not worried, but the loop switching condition and the matching mode need to be designed well, so that the oscillation type switching between the two loops is avoided.
The ALC using the logarithmic mode can realize a dual-loop ALC, the internal hardware connection of the logarithmic mode dual-loop ALC digital chip is shown in fig. 3, and the digital chip 105 can include a zero-point module 301 and a first logarithmic amplifier 302; the input end of the zero point module 301 is used as the input end of the digital chip 105, and the output end of the zero point module 301 is connected with the input end of the first logarithmic amplifier 302; the output of the first logarithmic amplifier 302 is connected to the input of the comparison block 304.
In particular, the zero module 301 is used to calibrate the zero of the digitized detected voltage 1C, so that when the detected signal amplitude is small (smaller than the minimum measured signal by a certain range), the result of entering the subsequent module is a set reference value (e.g., "0" or "1"). The reason why this module is needed is that the reference values of the analog detector and the digitizing circuit are not necessarily the same as the reference values of the digital scheme after being digitized in the design of the scheme, or the reference values of different devices are somewhat deviated due to factors such as the batch consistency error of analog devices.
In specific implementation, the first comparison integrator 203 and the second comparison integrator 205 in the digital chip 105 each include an amplifier and an accumulator; the input end of the amplifier is connected with the output end of the error judgment module 202 and is used for amplifying the current error voltage; the input end of the accumulator is connected with the output end of the amplifier, and the output end of the accumulator is used as the output end of the digital chip 105, and is used for accumulating the amplified current error voltage to obtain the final error voltage. Wherein the first comparison integrator 203 comprises a first stage amplifier 306 (of the form K2 x + b2) and an accumulator 307; the second comparator-integrator 205 comprises a second stage amplifier 312 (of the form k x) and an accumulator 313.
In specific implementation, the first processing module 204 in the digital chip 105 includes a first switch 308, an error voltage module 309, a preset voltage module 310, a first adder, and a voltage conversion module 311;
when the ALC circuitry is operating normally, the first switch 308 is closed; when the ALC circuit operates open-loop, the first switch 308 is open;
the error voltage module 309 is configured to store a preset error voltage or a final error voltage integrated by the first comparing integrator 203;
the preset voltage module 310 is used for storing preset voltage;
the first adder is used for adding the final error voltage and the preset voltage to obtain a control voltage of the first adjustable radio frequency attenuator 101;
the input terminal of the voltage conversion module 311 is connected to the output terminal of the adder, and is used for correcting the nonlinearity between the attenuation of the first adjustable rf attenuator 101 and the control voltage.
In particular, the second processing module 206 in the digital chip 105 includes a second switch 314, a second adder, and an optional switch 317;
the final error voltage integrated by the first comparator-integrator 203 is added to the test voltage 315 through the second switch 314 and then is used as the input of the optional switch 317; when the dual-loop ALC normally operates, the selectable switch 317 is connected with the second ALC circuit to output the control voltage of the second adjustable radio frequency attenuator 107; when the AM is on, the second adjustable radio frequency attenuator 107 is used to achieve AM modulation.
The working principle of the log-mode double-ring ALC digital chip is as follows:
after entering the digital chip, the digitized detection voltage 1C is first subtracted from the zero module 301, passes through the logarithmic amplifier 302, and is compared (subtracted) with the reference voltage DAC 304. If the current error is larger, the selectable switch 305 is connected with the coarse adjustment ALC loop, the current error enters the first-stage amplifier 306, and the current error is accumulated through the accumulator 307 after being amplified. The accumulated output is configured to enter the error voltage block 309 through the first switch 308, and together with the preset voltage block 310, the ALC on, ALC off, and ALC hold functions are realized. The error voltage and the preset voltage are added by the first adder and output as the control voltage 1D of the first adjustable rf (coarse) attenuator 101 after passing through the voltage converting module 311. If the current error is small, the selectable switch 305 is connected with the fine-tuning ALC loop, and the current error enters the second-stage amplifier 312, is amplified and then is accumulated through the accumulator 313. The summed input is passed through the second (switchable) switch 314 and added to the test voltage DAC315 as input to the selectable switch 317. When the dual-loop ALC operates normally, the selectable switch 317 is connected to the fine-tuning ALC loop, outputting the control voltage 1E of the second tunable rf (fine-tuning) attenuator 107. When the AM is turned on, the selectable switch 317 is turned on with the AM control voltage block 316, ALC uses single loop control, and fine-tuning the ALC attenuator is used to implement AM modulation, i.e., the input of the selectable switch 317 is used as the control voltage of the AM.
The selectable (error toggle) switch 305 can operate in real-time mode, enabling dual ring simultaneous operation; and the double-ring alternate work can be realized by switching in different time periods.
The ALC using the linear mode can also realize a dual-loop ALC, the internal hardware connection of the linear mode dual-loop ALC digital chip is shown in fig. 4, and the digital chip 105 may further include a zero-point module 401, a linearity compensation module 402, a sampling filter module 403, and a square-on-square module 404;
the input end of the zero module 401 is used as the input end of the digital chip 105, and the output end is connected with the input end of the linearity compensation module 402; the output end of the linearity compensation module 402 is connected with the input end of the sampling filter module 403; the output end of the sampling filter module 403 is connected with the input end of the square-open module 404; the output terminal of the square-on module 404 is connected to the input terminal of the comparing module 201, and is used for reducing the oversampled detected voltage from power amplitude to voltage amplitude.
In particular, the zero module 401 has the same function as the zero module 301.
The linearity compensation module 402 functions to compensate for the non-linearity of the detector (diode detector, etc.). In the original ALC, a specially designed logarithmic amplifier (dual-slope logarithmic amplifier) is mostly used for simultaneously realizing logarithmic amplification and linearity compensation functions, and the ALC needs to be separately designed and can be realized by using a quadratic function.
The sampling filter module 403 is mainly used to oversample the detected voltage (i.e. to sample the input signal with a frequency much higher than the nyquist sampling frequency) to increase the effective number of bits of the detected voltage at the cost of reducing the effective sampling rate, and this module does not work when the AM is turned on. The sampling filter is switchable to enable the oversampling function when the resolution requirement is high and the speed requirement is not very high (ALC operation); the oversampling function is turned off when the speed requirement is high and the resolution requirement is not very high (auxiliary AM).
Linear mode ALC error comparison and integration is in volts (V) as the fundamental unit, and attenuator control is still implemented in dB; it is convenient to match with AM but has high requirements on ADC. The signal flow of linear mode ALC is substantially equivalent to log mode ALC, and the difference part is described below. The digitized detected voltage is not logarithmically amplified before being compared to the reference voltage DAC406, but instead a linearity compensation module 402, a switchable sample filter module 403, and a square-on-square module 404 are used. The second logarithmic amplifier 413 is placed after the error voltage is added to the preset voltage to realize the logarithmic mode control of the attenuator.
The error determination module 407 may adopt a real-time working mode, or may adopt a time-sharing switching mode, so as to implement dual-ring switching work or dual-ring alternate work.
Illustrating the benefits that can be obtained using the dual-loop ALC circuit of the present invention:
the single-ring mode uses 2MHz update rate and 14bit DAC to realize an ALC adjustable range of-20-10 dBm (including 9 kHz-3 GHz frequency and 0-50 ℃ temperature compensation), and when the output amplitude of the ALC is small, large noise signals or stray signals are probabilistically generated in a deviation signal 100 Hz-100 kHz interval. The noise signal can reach-110 dBc/Hz, and the stray signal is reflected as an obvious peak on the phase noise curve of the radio frequency signal. With dual loop ALC, the noise is below-120 dBc/Hz, and the spur is below the phase noise.
In summary, the invention constructs two sets of integration modules inside the digital chip to form two ALC circuits: the first ALC circuit uses a first adjustable radio frequency attenuator to carry out preliminary adjustment on the amplitude of an output signal, so that the amplitude error of the output signal is kept in a small range; the second digital ALC loop further corrects the residual amplitude of the output signal by using a second adjustable radio frequency attenuator, so that lower error jitter is realized, and the requirements of an adjustable range, high resolution and low jitter of a signal source ALC are met.
An amplitude adjusting device such as an amplifier and a fixed attenuator can be arranged between the adjustable radio frequency attenuators 101 and 107 or between the adjustable radio frequency attenuator 101 (or 107) and the power divider 102.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A measurement device having a dual loop ALC circuit, wherein the dual loop ALC circuit includes a first ALC circuit and a second ALC circuit; the first ALC circuit comprises a first adjustable radio frequency attenuator, a power divider (102), a detector (103), an analog-to-digital conversion module (104), a digital chip (105) and a first digital-to-analog conversion module (106); the second ALC circuit comprises a power divider (102), a detector (103), an analog-to-digital conversion module (104), a digital chip (105), a second adjustable radio frequency attenuator and a second digital-to-analog conversion module (108);
the input end of the second adjustable radio frequency attenuator is used as the input end of the double-loop ALC circuit, and the output end of the second adjustable radio frequency attenuator is connected with the input end of the first adjustable radio frequency attenuator and is used for attenuating the amplitude of the input radio frequency signal (1A);
the output end of the first adjustable radio frequency attenuator is connected with the input end of the power divider (102) and is used for further attenuating the amplitude of the input radio frequency signal (1A);
the adjustable attenuation range of the first adjustable radio frequency attenuator is larger than that of the second adjustable radio frequency attenuator, the minimum step of the first adjustable radio frequency attenuator is larger than that of the second adjustable radio frequency attenuator, the requirement of an ALC (adaptive logic level) adjustable range is met, and the adjustable attenuation resolution of the second adjustable radio frequency attenuator is larger than that of the first adjustable radio frequency attenuator, and the requirement of high resolution and low jitter of the ALC is met;
the power divider (102) divides the input radio frequency signal (1A) after two amplitude decays into a first output radio frequency signal (1B) and a second output radio frequency signal; a first output end of the power divider (102) is used as an output end of the double-loop ALC circuit and is used for outputting a first output radio frequency signal (1B); a second output end of the power divider (102) is connected with an input end of the detector (103) and is used for outputting a second output radio frequency signal to the detector (103);
the output end of the detector (103) is connected with the input end of the analog-to-digital conversion module (104) and is used for detecting the second output radio frequency signal to obtain a detection voltage;
the output end of the analog-to-digital conversion module (104) is connected with the input end of the digital chip (105) and is used for performing analog-to-digital conversion on the detection voltage to obtain digitized detection voltage;
a first output end of the digital chip (105) is connected with an input end of a first digital-to-analog conversion module (106), and a second output end of the digital chip is connected with an input end of a second digital-to-analog conversion module (108);
the digital chip (105) is used for determining the control voltage of the adjustable radio frequency attenuator according to the digitized detection voltage, and when the control voltage of the first adjustable radio frequency attenuator is determined, the first ALC circuit works; when the control voltage of the second adjustable radio frequency attenuator is determined, the second ALC circuit works;
the output end of the first digital-to-analog conversion module (106) is connected with the adjusting end of the first adjustable radio frequency attenuator and is used for performing digital-to-analog conversion on the control voltage of the first adjustable radio frequency attenuator;
the output end of the second digital-to-analog conversion module (108) is connected with the adjusting end of the second adjustable radio frequency attenuator and is used for performing digital-to-analog conversion on the control voltage of the second adjustable radio frequency attenuator.
2. The measurement arrangement with dual-loop ALC circuit of claim 1, characterized in that the digital chip (105) comprises a comparison block (201), an error determination block (202), a first comparison integrator (203) and a second comparison integrator (205);
the input end of the comparison module (201) is used as the input end of the digital chip (105), and the output end of the comparison module (201) is connected with the input end of the error judgment module (202) and used for comparing the digitized detection voltage with the reference voltage to obtain the current error voltage;
a first output end of the error judgment module (202) is connected with an input end of the first comparison integrator (203), a second output end of the error judgment module (202) is connected with an input end of the second comparison integrator (205) and is used for judging the magnitude of the current error voltage, and if the current error voltage is greater than a preset error value, the current error voltage is output to the first comparison integrator (203); if the current error voltage is smaller than the preset error value, outputting the current error voltage to a second comparison integrator (205);
the output end of the first comparison integrator (203) is used as the first output end of the digital chip (105) and is used for integrating the current error voltage;
the output end of the second comparison integrator (205) is used as a second output end of the digital chip (105) and used for integrating the current error voltage.
3. The measurement device with dual-loop ALC circuit of claim 2, characterized in that the digital chip (105) further comprises a zero block (301) and a first logarithmic amplifier (302);
the input end of the zero point module (301) is used as the input end of the digital chip (105), and the output end of the zero point module (301) is connected with the input end of the first logarithmic amplifier (302) and is used for calibrating the zero point of the digitized detection voltage;
the output end of the first logarithmic amplifier (302) is connected with the input end of the comparison module (201) and is used for carrying out logarithmic amplification on the digitized detection voltage after zero calibration.
4. The measurement device with dual loop ALC circuit of claim 2, characterized in that the digital chip (105) further comprises a zero block (301), a linearity compensation block (402), a sampling filtering block (403), and a square-on block (404);
the input end of the zero point module (301) is used as the input end of the digital chip (105), and the output end of the zero point module (301) is connected with the input end of the linearity compensation module (402) and is used for calibrating the zero point of the digitized detection voltage;
the output end of the linearity compensation module (402) is connected with the input end of the sampling filter module (403) and is used for compensating the nonlinearity of the digitized detection voltage after zero point calibration;
the output end of the sampling filter module (403) is connected with the input end of the square-on module (404) and is used for oversampling the digitized detection voltage after nonlinear compensation;
the output end of the square-on module (404) is connected with the input end of the comparison module (201) and used for reducing the oversampled detection voltage from power amplitude to voltage amplitude.
5. The measurement device with dual loop ALC circuit of claim 2, characterized in that the first comparison integrator (203) and the second comparison integrator (205) each comprise an amplifier and an accumulator;
the input end of the amplifier is connected with the output end of the error judgment module (202) and is used for amplifying the current error voltage;
the input end of the accumulator is connected with the output end of the amplifier, and the output end of the accumulator is used as the output end of the digital chip (105) and used for accumulating the amplified current error voltage to obtain the final error voltage.
6. The measurement device with dual loop ALC circuit of claim 2, characterized in that the digital chip (105) further comprises a first processing block (204) and a second processing block (206);
the input end of the first processing module (204) is connected with the output end of the first comparison integrator (203), and the output end of the first processing module (204) is used as the first output end of the digital chip and is used for correspondingly processing the final error voltage integrated by the first comparison integrator (203);
the input end of the second processing module (206) is connected with the output end of the second comparison integrator (205), and the output end of the second processing module (206) is used as the second output end of the digital chip and is used for correspondingly processing the final error voltage integrated by the second comparison integrator (205).
7. The measurement device with dual loop ALC circuit of claim 6, characterized in that the first processing block (204) includes a first switch (308), an error voltage block (309), a preset voltage block (310), a first summer and a voltage conversion block (311);
when the ALC circuitry is operating normally, the first switch (308) is closed; when the ALC circuit is operated in an open loop mode, the first switch (308) is opened;
the error voltage module (309) is used for storing a preset error voltage or a final error voltage integrated by the first comparison integrator (203);
the preset voltage module (310) is used for storing preset voltage;
the first adder is used for adding the final error voltage and the preset voltage to obtain the control voltage of the first adjustable radio frequency attenuator (101);
the input end of the voltage conversion module (311) is connected with the output end of the adder and is used for correcting nonlinearity between the attenuation of the first adjustable radio frequency attenuator and the control voltage.
8. The measurement device with dual loop ALC circuitry of claim 7, wherein the first processing block (204) further includes a second log amplifier (413);
the input end of the second logarithmic amplifier (413) is connected with the output end of the first adder, and the output end of the second logarithmic amplifier (413) is connected with the input end of the voltage conversion module (311) and used for carrying out logarithmic amplification on the control voltage of the first adjustable radio frequency attenuator.
9. The measurement device with dual loop ALC circuit of claim 6, characterized in that the second processing block (206) includes a second switch (314), a second summer, and an optional switch (317);
the final error voltage integrated by the first comparison integrator (203) is added with the test voltage (315) through the second switch (314) and then is used as the input of the optional switch (317); when the double-ring ALC normally operates, the selectable switch (317) is connected with the second ALC circuit, and the control voltage of the second adjustable radio frequency attenuator is output; when the AM is on, the second adjustable radio frequency attenuator is used to implement AM modulation.
10. The measurement arrangement with dual-loop ALC circuit of claim 2, characterized in that the comparison block (201) employs a subtractor.
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| CN111181601B (en) * | 2019-11-22 | 2021-06-29 | 北京麦克斯韦科技有限公司 | Control system of quick response automatic level control loop |
| CN113541621A (en) * | 2020-04-21 | 2021-10-22 | 中兴通讯股份有限公司 | ALC circuit, signal source output power control method and storage medium |
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