CN106888000B - Measuring device with ALC circuit - Google Patents
Measuring device with ALC circuit Download PDFInfo
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Abstract
The present invention provides a measuring apparatus having an ALC circuit, the ALC circuit including: the output end of the adjustable radio frequency attenuator is connected with the input end of the power distribution unit; the output end of the power distribution unit is connected with the input end of the detector; the output end of the detector is connected with the input end of the analog-to-digital converter; the output end of the analog-to-digital converter is connected with the input end of the digital chip; the output end of the digital chip is connected with the input end of the digital-to-analog converter; the digital chip comprises a zero module, a comparison integrator, an ALC open-loop control module and a logarithmic amplifier, wherein the output end of the zero module is connected with the input end of the comparison integrator; the output end of the comparison integrator is connected with the input end of the ALC open-loop control module; the output end of the ALC open-loop control module is connected with the input end of the logarithmic amplifier, and the logarithmic amplifier is arranged behind the comparison integrator, so that the problem of periodic distortion of the AM under partial modulation frequency is greatly reduced.
Description
Technical Field
The invention relates to the technical field of signal measurement and test, in particular to a measuring device with an ALC circuit.
Background
The radio frequency signal source is a common device in the field of measurement and test. The radio frequency signal source is mainly used for generating a radio frequency signal with a certain frequency range and amplitude range and used as excitation or reference of the device to be tested. And can also output various Modulation signals, such as FM (Frequency Modulation), AM (amplitude Modulation), PM (Phase Modulation), IQ, Pulse, etc., which provide a basis for debugging communication equipment. Amplitude accuracy and stability of an output signal of a radio frequency signal source are one of important indexes of the radio frequency signal source, AM is also an important measurement parameter of performance of the radio frequency signal source, and the indexes are generally realized by or closely related to an ALC (Automatic Level Control) circuit.
The ALC is a feedback loop, which is mainly composed of 3 blocks of "detection", "comparison", and "adjustment". And during normal operation (ALC on), the ALC on detects the amplitude of the output signal in real time, compares the detected result with a set amplitude value, and dynamically adjusts the attenuation (or gain) of the loop according to the comparison result until the amplitude of the output signal is equal to the set value. Depending on the practical use, ALC will mostly provide an open loop mode (ALC off or ALC hold) in which the control parameters of the adjustable module are fixed and the output signal amplitude is no longer dynamically adjusted. In addition, many ALCs also provide a lock-indication function, indicating whether the output signal amplitude has stabilized. In the radio frequency signal source, ALC also participates in AM and plays an important role.
The CN201310721663.8 patent describes a common analog ALC circuit (not introducing open loop mode and lock indication, etc.), as shown in fig. 1.
The radio frequency signal 1A passes through the adjustable radio frequency attenuator 101, the fixed amplifier 103 and the coupler 104 and then outputs 1F. The coupler 104 is operative to feed a portion of the radio frequency signal to the detector 112, and amplitude information of the output radio frequency signal 1F is obtained by the detector 112. The resistor 102 is required for the coupler to work normally, so that the coupler works in a set state. The log amplifier 110 acts to logarithmically amplify the amplitude signal, extending the range of amplitude signals that the ALC is capable of handling. The reference signal 1G represents the amplitude of the desired output of the ALC, and the AM baseband signal 1H has zero amplitude (1I is also zero) when the AM is not on. The detected amplitude information of the output rf signal 1F is compared with the amplitude information 1G expected to be output by the ALC after passing through the log amplifier 110, and the error between the two is integrated. The comparison and integration process is performed by an integrator formed by an operational amplifier 108 and a capacitor 107. The integrated voltage is amplified by the exponential amplifier 105 and used as a control signal of the adjustable radio frequency attenuator 101 to adjust the attenuation amount. The effect of the exponential amplifier 105 is to adjust the non-linearity of the control voltage 1C of the adjustable rf attenuator 101, making the adjustable rf attenuator 101 more controllable. When the amplitude of the output radio frequency signal 1F is not equal to the set amplitude 1G, the output voltage of the integrator will change continuously, and further the attenuation of the adjustable radio frequency attenuator 101 is changed until the amplitude of the output radio frequency signal 1F is equal to the expected amplitude 1G of the ALC. Specifically, when the amplitude of the output radio frequency signal 1F is smaller than the set amplitude 1G, the attenuation of the adjustable radio frequency attenuator 101 is continuously decreased, so that the amplitude of the output radio frequency signal 1F is gradually increased until the two amplitudes are equal to each other; and vice versa. (when the amplitudes are equal, the attenuation is kept constant). The AM baseband signal 1H passes through a logarithmic amplifier 111 and is simultaneously superposed before and after an integrator, and the superposition in front of the integrator is realized through a superposition device 109 in order to realize AM by means of the function of automatic amplitude control (ALC); the superposition by the superimposer 106 after the integrator is due to the insufficient ability of the ALC to control the amplitude (when the AM modulation frequency is high) and the need to directly control the adjustable rf attenuator 101.
Devices such as a logarithmic amplifier, an exponential amplifier and the like in the analog ALC circuit mostly use a diode or a triode as a core device, and the volt-ampere characteristic curves of the diode and the triode change along with the temperature change, so that the temperature stability is poor. In addition, the analog circuit mostly needs a relatively complex design to realize functions such as an open-loop mode and a lock indication, and the expandability is not strong.
In contrast to analog ALC circuits, patent CN201310721663.8 proposes a digital ALC circuit, which is shown in fig. 2 as a schematic diagram.
The rf signal 2A passes through the adjustable rf attenuator 201 and the power distribution module 202 to output a signal 2B. The power distribution module 202 divides the input rf signal 2A into two parts of signals 2B and 2C according to a certain ratio, and uses 2C to reflect the amplitude information of the output signal 2B in real time. The detector 203 converts the input rf signal 2C into a collimated stream signal proportional to its amplitude, which is digitized by the ADC205 and then 2D into the digital chip 204. After the digital chip 204 finishes the calculation, the digital chip outputs a signal 2E, and outputs the control voltage of the adjustable radio frequency attenuator 201 through the DAC206, so as to adjust the attenuation.
As shown in fig. 3, the input signal 2D is subtracted from the zeroing module 306, and then enters the logarithmic amplifying module 301 or the linear amplifying module 307 (selected by the switch 308 and the switch 309). The amplified signal is converted by the linear amplification block 310, compared with the set amplitude signal V1 (inverted and added), and the error between the two (inverted and added) is fed to the integrator 303. The ALC state control block 311 determines the ALC mode of operation (ALC on, ALC off, ALC hold), and the integrator 303 outputs in normal operation (ALC on) are summed with the preset voltage as a preliminary control signal for the adjustable rf attenuator 201. The voltage conversion module 304 is mainly used for adjusting the control voltage according to the characteristics of the adjustable radio frequency attenuator 201, so that the attenuator is convenient to control.
Patent CN201310721663.8 also proposes an implementation of AM in a radio frequency signal source, and the structural block diagram is shown in fig. 4. The ALC section is composed of an adjustable radio frequency attenuator 401, a power divider 402, a detector 403, and a data processing module 404. The AM is composed of a modulation signal generation unit 406, a data processing module 407 and an adjustable radio frequency attenuator 405. The ALC part and the AM are independently controlled, so that the relevance between the AM and the ALC is reduced, the design difficulty is reduced, and the performance is improved.
The digital ALC scheme main body is derived from an analog ALC scheme, and compared with the analog ALC scheme, the digital ALC scheme has the advantages of high temperature stability, strong expandability and the like. However, the structure of the digital ALC circuit in the digital chip is still the analog ALC scheme, which is not considered much for AM. The listed AM implementation, while considering the independence of both the ALC portion and the AM from a hardware perspective, does not account for the relationship of the two within the hardware or digital chip. When the signal source realizes the AM, the requirement on the amplitude stability of the modulated signal (carrier signal) is not reduced, and ALC is required to normally control the amplitude of the carrier. The ALC is used for keeping the amplitude of the output signal unchanged; AM requires that the output signal amplitude is changed according to the amplitude of the modulation signal (baseband signal) and the amplitude of the modulated signal (carrier signal) is not changed; whereas conventional ALC has no capability to distinguish between a modulated signal (carrier signal) and a modulated signal (AM output signal). Therefore, if the ALC in this scheme is not further processed, AM is applied to the ALC inside the chip or a hardware circuit is used, and this AM scheme will hardly achieve good AM modulation.
In general, referring to an analog ALC scheme, an AM modulation signal (baseband signal) is logarithmically amplified and then added to an ALC reference voltage V1. Digital circuits, however, differ from analog circuits in that using separate data points instead of a continuous analog curve, discards information between adjacent data points. If there is no continuous change in the information between two data points, discarding the intermediate information will not have a significant impact on the overall result. However, due to the characteristics of the AM and the logarithmic amplifier, when the AM modulation depth is high, the logarithmically amplified modulation signal will change dramatically at the negative peak. Digitization processes have difficulty accurately processing rapidly changing signals, especially when the frequency of the signal is continuously changing, which can produce large deviations at AM negative peaks. This deviation is related to the AM modulation frequency, and the actual modulation signal (baseband signal) of the modulated signal is periodically distorted to a large extent around a part of the modulation frequency.
Disclosure of Invention
The embodiment of the invention provides a measuring device with an ALC circuit, a processing scheme of the ALC for AM signals is added and optimized in a digital chip, and the periodic distortion of the AM under partial modulation frequency is greatly reduced. The ALC circuit comprises an adjustable radio frequency attenuator 201, a power distribution unit 202, a detector 203, an analog-to-digital converter 205, a digital chip 204 and a digital-to-analog converter 206;
the input end of the adjustable radio frequency attenuator 201 is the input end of the ALC circuit, and the output end of the adjustable radio frequency attenuator 201 is connected with the input end of the power distribution unit 202;
a first output end of the power distribution unit is used as an output end of the ALC circuit, and a second output end of the power distribution unit is connected with an input end of the detector 203;
the output end of the detector 203 is connected with the input end of the analog-to-digital converter 205;
the output end of the analog-to-digital converter 205 is connected with the input end of the digital chip 204;
the output end of the digital chip 204 is connected with the input end of the digital-to-analog converter 206;
the output end of the digital-to-analog converter 206 is connected with the adjusting end of the adjustable radio frequency attenuator 201;
the digital chip 204 comprises a zero module 501, a comparison integrator 503, an ALC open-loop control module 504 and a logarithmic amplifier 505;
the input end of the zero module 501 is used as the input end of the digital chip 204, is connected to the output end of the analog-to-digital converter 205, and is used for calibrating the zero of the digitized detection voltage 2D;
the input end of the comparison integrator 503 is connected to the output end of the zero point module 501, and is configured to compare the digitized detection voltage 2D after zero point calibration with a set reference voltage to obtain a final error voltage;
the input end of the ALC open-loop control module 504 is connected to the output end of the comparison integrator 503, and is configured to add the final error voltage to a preset voltage to obtain a control voltage;
the input end of the logarithmic amplifier 505 is connected to the output end of the ALC open-loop control module 504, and the output end of the logarithmic amplifier 505 is used as the output end of the digital chip 204, and is connected to the input end of the digital-to-analog converter 206, and is used for logarithmically amplifying the control voltage.
In one embodiment, the digital chip 204 further includes a squaring module 502;
the input end of the square-on module 502 is connected to the output end of the zero module 501, and the output end of the square-on module 502 is connected to the input end of the comparator-integrator 503, so as to reduce the zero-point-calibrated digitized detection voltage from power amplitude to voltage amplitude, thereby obtaining a first detection voltage.
In one embodiment, the digital chip 204 further includes a linearity compensation module 702 and a sampling filter module 703;
the input end of the linearity compensation module 702 is connected to the output end of the zero point module 501, and is configured to compensate for nonlinearity of the digitized detection voltage 2D after zero point calibration;
the input end of the sampling filter module 703 is connected to the output end of the linearity compensation module 702, and the output end of the sampling filter module 703 is connected to the input end of the comparison integrator 503, so as to perform oversampling on the digitized detection voltage after nonlinear compensation;
the input end of the square-on-square module 502 is connected to the output end of the sampling filter module 703.
In one embodiment, the digital chip 204 further includes a temperature compensation module for performing temperature compensation on the ALC circuit.
In one embodiment, the comparison integrator 503 includes a subtractor 511, an accumulator 512, and a linear amplifier 715;
the input end of the subtractor 511 is connected to the output end of the square-on module 502, and is configured to subtract the first detection voltage from the set reference voltage to obtain a current error voltage;
the input end of the linear amplifier 715 is connected with the output end of the subtracter 511, and is used for adjusting the multiplying power of the current error voltage;
the input end of the accumulator 512 is connected to the output end of the linear amplifier 715, and the output end of the accumulator 512 is connected to the input end of the ALC open-loop control module 504, so as to accumulate the current error voltage after the magnification adjustment, and obtain the final error voltage.
In one embodiment, the ALC open-loop control module 504 includes a switch 513, an error voltage module 514, a preset voltage module 515, and a summer 516;
when the ALC circuitry is operating normally, the switch 513 is closed; when the ALC circuit operates open-loop, the switch 513 is opened;
the error voltage module 514 is configured to store a preset error voltage or an error voltage integrated by the comparator-integrator 503;
the preset voltage module 515 is configured to store a preset voltage;
the adder 516 is used for adding the error voltage and the preset voltage to obtain the control voltage.
In one embodiment, the digital chip 204 further comprises a voltage conversion module 506;
the input end of the voltage conversion module 506 is connected to the output end of the logarithmic amplifier 505, and is used for correcting the nonlinearity between the attenuation of the adjustable rf attenuator 201 and the control voltage.
In one embodiment, the voltage conversion module 506 includes a first stage linear amplifier 601 and a wavetable module 602;
the input end of the first-stage linear amplifier 601 is connected with the output end of the logarithmic amplifier 505 and is used for linearly changing the attenuation error;
the input end of the wavetable module 602 is connected to the output end of the first-stage linear amplifier 601, and is configured to record a nonlinear curve between the attenuation of the adjustable radio frequency attenuator 201 and the control voltage.
In one embodiment, the voltage conversion module 506 further comprises a second stage linear amplifier 603;
the input end of the second-stage linear amplifier 603 is connected to the output end of the wavetable module 602, and the output end of the second-stage linear amplifier 603 is used as the output end of the digital chip 204, and is connected to the input end of the digital-to-analog converter 205, and is used for performing nonlinear change on the attenuation error.
In the embodiment of the invention, in a digital chip, a logarithmic amplifier is placed behind a comparison integrator, and in the comparison integrator, after the digitized detection voltage subjected to zero calibration is compared (subtracted) with a set reference voltage, the obtained error value is far smaller than the directly acquired detection voltage, and the condition that the frequency of a modulation signal is rapidly changed basically cannot occur even if the digital amplifier is subjected to logarithmic conversion, so that the problem of periodic distortion of an AM under partial modulation frequency is greatly reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of an analog ALC circuit architecture according to an embodiment of the present invention;
FIG. 2 is a diagram of a digital ALC circuit hardware connection provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of an internal structure of a digital chip of the digital ALC circuit according to the present invention;
fig. 4 is a schematic diagram of a circuit structure for implementing an AM in a radio frequency signal source according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a circuit structure of an AM improvement of digital ALC provided by an embodiment of the present invention;
fig. 6 is a schematic diagram of an optimized structure of a voltage conversion module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a specific digital ALC-AM modification circuit structure provided by an embodiment of the present invention;
fig. 8 is a schematic diagram of a modulation signal result before AM optimization by a digital ALC according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating an effect of a linear transformation module according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
For the problem that the AM has periodic distortion under partial modulation frequency by the digital ALC joint implementation, the invention mainly adopts an amplitude linear error accumulation scheme (linear ALC), adds and optimizes the processing scheme of the ALC on the AM signal in a digital chip, and changes the position of an error comparison module (107, 108 and 109 in an analog ALC loop and 302 and 303 in a digital ALC loop) in an ALC loop from a logarithmic amplifier to the front of the logarithmic amplifier.
Specifically, the digital ALC circuit of FIG. 2 is optimized for the digital chip, and the working principle of the digital ALC circuit is as follows:
the rf signal 2A passes through the adjustable rf attenuator 201 and the power distribution module 202 to output a signal 2B. The power distribution module 202 divides the input rf signal 2A into two parts of signals 2B and 2C according to a certain ratio, and uses 2C to reflect the amplitude information of the output signal 2B in real time. The detector 203 converts the input rf signal 2C into a collimated stream signal proportional to its amplitude, which is digitized by the ADC205 and then 2D into the digital chip 204. After the digital chip 204 finishes the calculation, the digital chip outputs a signal 2E, and outputs the control voltage of the adjustable radio frequency attenuator 201 through the DAC206, so as to adjust the attenuation.
Fig. 5 is a diagram showing an internal structure of the improved digital chip. The digital chip 204 includes a zero module 501, a comparison integrator 503, an ALC open-loop control module 504, and a logarithmic amplifier 505;
the input end of the zero module 501 is used as the input end of the digital chip 204, and is connected with the output end of the analog-to-digital converter 205; the input end of the comparison integrator 503 is connected with the output end of the zero module 501; the input end of the ALC open-loop control module 504 is connected with the output end of the comparison integrator 503; the input end of the logarithmic amplifier 505 is connected with the output end of the ALC open-loop control module 504, and the output end of the logarithmic amplifier 505 is used as the output end of the digital chip 204.
In specific implementation, the zero module 501 is used to calibrate the zero of the digitized detected voltage 2D, so that when the detected signal amplitude is small (smaller than the minimum measured signal by a certain range), the result entering the subsequent module is a set reference value (e.g., "0" or "1"). The reason why this module is needed is that the reference values of the analog detector and the digitizing circuit are not necessarily the same as the reference values of the digital scheme after being digitized in the design of the scheme, or the reference values of different devices are somewhat deviated due to factors such as the batch consistency error of analog devices.
In specific implementation, if the AM baseband signal 508 entering the comparison integrator 503 can be represented by 1+ m × sin (w × t) (m is modulation depth, w is modulation angular frequency), the detected power amplitude needs to be reduced to a voltage amplitude before entering the comparison integrator 503, and the function can be performed by the square-on module 502, that is, the digital chip 204 can further include the square-on module 502, where an input end of the square-on module 502 is connected to an output end of the zero module 501, and an output end of the square-on module 502 is connected to an input end of the comparison integrator 503, so as to reduce the digitized detected voltage after zero calibration from the power amplitude to the voltage amplitude, thereby obtaining the first detected voltage.
If the AM baseband signal 508 entering the comparator integrator 503 is already able to use (1+ m sin (w t))2It is shown that it may not be necessary to restore the detected power amplitude to the voltage amplitude, i.e. it is said that the squaring module 502 may also be eliminated depending on the actual situation.
In a specific implementation, the comparison integrator 503 may include a subtractor 511 and an accumulator 512; the input end of the subtractor 511 is connected to the output end of the square-on module 502, and is configured to subtract the first detection voltage from the set reference voltage to obtain a current error voltage; the input end of the accumulator 512 is connected to the output end of the subtractor 511, and the output end is connected to the input end of the ALC open-loop control module 504, so as to accumulate the current error voltage to obtain a final error voltage.
In specific implementation, the ALC open-loop control module 504 includes a switch 513, an error voltage module 514, a preset voltage module 515, and an adder 516; the error voltage module 514 is used for storing a preset error voltage or a final error voltage integrated by the comparator-integrator 503; the preset voltage module 515 is used for storing a preset voltage; the adder 516 is used for adding the final error voltage and the preset voltage to obtain the control voltage.
The working principle of the AM optimized digital ALC circuit is as follows:
the digitized detection voltage 2D is added (or subtracted) with a zero value through a zero module 501, mainly the zero of the digitized detection voltage 2D is calibrated, the calibrated result passes through a squaring module 502 and then enters a comparison integrator 503, the comparison integrator 503 subtracts the digitized detection voltage 2D after zero calibration from a set reference voltage DAC510 through a subtractor 511, the difference (current error voltage) between the two is entered into an accumulator 512, and the accumulated result (final error voltage) is the output of the comparison integrator 503. The accumulated result is fed into the ALC open loop control block 504, and when ALC is operating normally (ALC on), switch 513 is closed and the output of comparator integrator 503 is used to update the error voltage stored in error voltage block 514 in real time. At this time, the final error voltage is stored in the error voltage module 514, the final error voltage is added to the preset voltage through the adder 516, and the added result (control voltage) is output by the open-loop control module; when the ALC is in open-loop operation (ALC off or ALC hold), switch 513 is opened and the error voltage remains constant (ALC hold) or zero (ALC off). The output of the ALC open-loop control module 504 passes through a log amplifier 505 and finally outputs a signal 2E. The set reference voltage DAC510 is obtained by multiplying the reference DAC0507 and the AM baseband signal 508 by the multiplier 509.
In summary, in the new digital ALC scheme, special processing is performed for AM. The most important point is that the logarithmic amplifier 505 is placed behind the comparison integrator 503, so that the direct logarithmic amplification of the AM signal is avoided, and the logarithmic amplification is performed by using an error signal with small change amplitude, so that the digitization distortion is avoided.
To cope with the change in the position of the logarithmic amplifier, there is an appropriate change in the module from the signal input 2D to the logarithmic amplifier. After the digitized detection voltage 2D is adjusted by the zero module 501, it is first squared to convert the carrier amplitude information from watt (W) to volt (V), and then enters the comparison and integration module. As a further parameter of comparison (reference DAC) it is obtained by multiplying the carrier amplitude information in volts (V) (reference DAC0) by the AM modulation signal coefficients (AM baseband signal). The AM modulation coefficient (AM baseband signal) can be expressed by formula 1+ m × sin (w × t). After the actual signal amplitude (output of the square-on-square module) in volt form is compared (subtracted) with the amplitude (reference DAC0, in volt form) set by the user, the obtained error value will be much smaller than the directly acquired detection voltage, and even if the calculation result is subjected to logarithmic transformation, the situation that the calculation result is rapidly changed will not occur basically. The error calculation result is positive or negative, so that it is not suitable for direct logarithmic transformation. The accumulated result is also positive or negative, so that the logarithmic amplifier is placed after the preset voltage block. Since the result of the addition of the accumulator to the preset voltage is the control voltage of the attenuator, normally a positive number. In AM, the actual modulated signal envelope (post-detector signal) has less error from the user-set modulated signal (baseband signal) even at a larger modulation depth from the viewpoint of linear amplitude.
In addition, the conventional digital chip 204 further includes a voltage conversion module, an input end of which is connected to an output end of the logarithmic amplifier 505, and which is used for correcting the nonlinearity between the attenuation of the adjustable rf attenuator and the control voltage. Although the voltage conversion module is included, a detailed structure of the voltage conversion module is not described in detail, and the detailed structure thereof is yet to be further designed.
Due to the characteristics of the PIN diode, severe nonlinearity exists between the attenuation of the attenuator built by using the PIN diode and the control voltage, and the nonlinearity changes with the difference of the frequency of the radio-frequency signal. In general, the current-voltage characteristic of the PN junction may use an exponential correlation function (y ═ e)x) To describe, the non-linearity of the PIN diode can also be approximated using an exponential function. In an analog circuit, an exponential function (y ═ e) is used(m*x+n)) The nonlinearity between the attenuation and the control voltage curve at each frequency is approximated, and nonlinear compensation is performed using an exponential amplifier. The exponents (m, n) of the exponential function differ when the frequency changes, corresponding to the use of different (adjustable) reference currents for the exponential amplifier.
Generally, the voltage conversion module can be designed as an exponential amplifier by following an analog circuit, but the exponential amplifier is an analog approximation of the nonlinearity of the adjustable radio frequency attenuator, and has a certain difference with the real nonlinearity of the adjustable radio frequency attenuator. In the digital circuit, a wavetable can be used for recording a nonlinear curve between the attenuation and the control voltage, and the nonlinearity of the adjustable radio frequency attenuator is well approximated. The digital circuit may also simulate the exponential adjustment function of the exponential amplifier when the frequency changes. The digital circuit can add a linear amplification module (y-k 1 x + b1) before the wave table to achieve the similar function as the analog circuit (y-e)(k1*x+b1)) And realizing frequency compensation. Its non-linearity does not affect the final accuracy of the ALC when operating, but reduces the ALC lock-in time. If ALC does not have high requirements on locking time, the methodBlocks can also be cancelled according to the actual situation. However, the compensation effect is poor by using the method, and the compensation still has larger nonlinearity and still has room for improvement. Function y ═ e(k1*x+b1)Can be deformed into y-eb1*ek1*x＝P*ek1*xIt can be seen that this function can adjust the exponent and the magnification of the exponential function. PIN attenuators are sensitive to parasitic parameters of the device, especially when the frequency of the rf signal is high. The characteristics of the actual circuit and the PN junction are different, and a good approximation cannot be made by using e as a base number.
It is also possible to attempt to perform a wavetable scan for each frequency point (the frequency interval is small enough) and separately record the nonlinearity of the attenuator at each frequency, thereby achieving frequency compensation. However, this method requires a large amount of data to be stored, requires a wave table to be called in accordance with the frequency of the attenuator when used, and requires a large amount of data to be changed when the frequency is changed. If the speed of switching the frequency of the user is high, the data transmission quantity is large, and even the device cannot respond in time.
In view of the above problems, the present invention optimizes a voltage conversion module, and an optimized structure of the voltage conversion module is shown in fig. 6, where the voltage conversion module 506 includes a first-stage linear amplifier 601, a wave table module 602, and a second-stage linear amplifier 603, the attenuation information 6A to be output is subjected to first-stage linear amplification and then subjected to table lookup 602 in an amplitude dimension, and a table lookup result is output after second-stage linear amplification.
A second stage linear amplifier 603 is added after the wavetable to further adjust the non-linearity of the attenuator. Similar to the exponential amplifier, the added amplifier can adjust the base (e) of the exponential function, and the adjusted structure can use the function y (k 2e + b2)(k1*x+b1)And (4) showing.
The voltage conversion module consists of a first-stage wavetable and a two-stage linear amplifier, and is equivalent to adding a second-stage amplifier behind the wavetable compared with an analog exponential amplifier compensation scheme. This solution realizes the form as y ═ e (k2 × e + b2)(k1*x+b1)The calculation method has more flexibility. The first-stage amplifier corrects the index to achieve attenuation error (attenuation and attenuation set before the voltage conversion module)The actual amount of attenuation of the subtractor) is linearly varied. The second stage amplifier can carry out nonlinear change on the attenuation error, thereby achieving the purpose of further compensating the attenuation. The influence of the specific second-stage amplifier coefficient on the attenuation error can be estimated by adopting a method of function fitting and equation solving, and the estimation involves more parameters and processes, which are not described in detail here. The coefficient of the second-stage amplifier can also be adjusted by adopting a test method, and the variation of the attenuation error is tested at the same time, so that a proper compensation coefficient is obtained.
In particular, if the attenuation of the adjustable attenuator used in the ALC varies linearly with the control voltage (e.g., a well-designed or compensated commercial attenuator), the voltage conversion module 506 may be eliminated as appropriate.
In specific implementation, the digital chip 204 further includes a linearity compensation module 702 and a sampling filter module 703, as shown in fig. 7, an input end of the linearity compensation module 702 is connected to an output end of the zero module 701; the input end of the sampling filter module 703 is connected with the output end of the linearity compensation module 702, and the output end of the sampling filter module 703 is connected with the input end of the comparison integrator 705; the input end of the squaring module is connected to the output end of the sampling filter module 703.
In particular implementations, the linearity compensation module 702 functions to compensate for non-linearities of the detector (e.g., diode detector). In the original ALC, a specially designed logarithmic amplifier (dual-slope logarithmic amplifier) is mostly used for simultaneously realizing logarithmic amplification and linearity compensation functions, and the ALC needs to be separately designed and can be realized by using a quadratic function.
The sampling filter module 703 is mainly used to oversample the detected voltage (sample the input signal with a frequency much greater than the nyquist sampling frequency) to raise the effective number of bits of the detected voltage at the expense of reducing the effective sampling rate. The sampling filter is switchable to enable the oversampling function when the resolution requirement is high and the speed requirement is not very high (ALC operation); the oversampling function is turned off when the speed requirement is high and the resolution requirement is not very high (auxiliary AM).
In specific implementation, the comparison integrator 705 further includes a linear amplifier 715 in addition to the subtractor 714 and the accumulator 716, the linear amplifier is disposed between the subtractor 714 and the accumulator 716, and is used for adjusting the multiplying factor of the current error voltage, and the ALC lock time and the overshoot can be balanced to a proper range by configuring proper coefficients. When the sample filter module 703 switches, the amplifier coefficients typically need to be modified accordingly. For an ALC loop without sample filtering, the coefficients may not need to be switched, and if the logic is then reasonable in design for subtractor 714 and accumulator 716 in comparator-integrator 705, this block may be eliminated as appropriate.
The switch 706 functions to allow the ALC to perform an open loop (ALC off, ALC hold) function. When the ALC is operating normally, the switch is closed and the result of the accumulator is provided to the error voltage block 707 in real time. If the ALC is open-loop, the switch is open, and the value of error voltage block 707 remains constant (ALC hold) or goes to zero (ALC off).
The preset voltage block 708 is a control voltage that the ALC designer estimates based on circuit characteristics, and has many different values at different carrier frequencies and amplitudes. When the ALC is operating in open-loop mode, the ALC attenuator is controlled directly using the preset voltage (ALC off) or the preset voltage and a fixed error voltage (ALC hold).
The log amplifier 710 is a generic log transform, as opposed to a specially designed dual slope log amplifier, because the detector nonlinearity has been corrected by the linearity compensation module 702.
The working principle of the AM optimized digital ALC circuit is as follows:
the digitized detected voltage 7A is first added (or subtracted) with a zero value by a zero module 701, and then enters a comparison integrator 705 after passing through a linearity compensation module 702, a sampling filter module 703 and a square-on module 704. The comparison integrator 705 subtracts (compares) the output of the square-open module 704 from the set reference voltage DAC713, the difference (the current error voltage) between the two goes through the linear amplifier 715 and then enters the accumulator 716, the accumulated result (the final error voltage) goes through the switch 706 and then is added to the set preset voltage, and the sum of the two goes through the logarithmic amplifier module 710 and the voltage conversion module 711 to finally output the signal 7C.
The set reference voltage DAC713 is obtained by multiplying the reference voltage DAC0712 by the AM baseband signal 7B, where the reference voltage DAC0712 represents the carrier amplitude set by the user and the AM baseband signal 7B is converted into a scaling factor.
The digital chip also comprises a temperature compensation module which is used for carrying out temperature compensation on the ALC loop and mainly aims at improving the stability performance of the ALC temperature.
As shown in fig. 8, before the ALC is not optimized for AM, the AM modulation frequency is around a plurality of frequencies such as 77kHz and 35kHz, and when the modulation depth is set to about 95% or more, the actually modulated signal is seen to be severely distorted after demodulation. Specifically, the modulation signal is set to a sinusoidal signal having a fixed amplitude, and the amplitude (amplitude) of the demodulated baseband signal changes periodically. Similar to adding another amplitude modulation at a low frequency on the basis of the original baseband signal, the higher the modulation depth, the more significant the distortion. The normal result should be a sinusoidal signal with a fixed amplitude and should not have fluctuations.
When the ALC scheme is changed, the phenomenon basically disappears, and the demodulated signal is recovered to be normal and is approximately equivalent to the original sinusoidal signal. The effect diagram of the linear transformation module is shown in fig. 9:
Illustratively, an amplitude adjusting device such as a radio frequency amplifier, a fixed amplifier, etc. may be disposed between the adjustable radio frequency attenuator 201 and the power distribution unit 202, which does not affect the protection scope of the present invention.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A measuring apparatus having an ALC circuit, the ALC circuit comprising an adjustable radio frequency attenuator (201), a power distribution unit (202), a detector (203), an analog-to-digital converter (205), a digital chip (204) and a digital-to-analog converter (206);
the input end of the adjustable radio frequency attenuator (201) is the input end of the ALC circuit, and the output end of the adjustable radio frequency attenuator (201) is connected with the input end of the power distribution unit (202);
the first output end of the power distribution unit is used as the output end of the ALC circuit, and the second output end of the power distribution unit is connected with the input end of the detector (203);
the output end of the detector (203) is connected with the input end of the analog-to-digital converter (205);
the output end of the analog-to-digital converter (205) is connected with the input end of the digital chip (204);
the output end of the digital chip (204) is connected with the input end of the digital-to-analog converter (206);
the output end of the digital-to-analog converter (206) is connected with the adjusting end of the adjustable radio frequency attenuator (201);
the digital chip (204) is characterized by comprising a zero module (501), a comparison integrator (503), an ALC open-loop control module (504) and a logarithmic amplifier (505);
the input end of the zero point module (501) is used as the input end of the digital chip (204), is connected with the output end of the analog-to-digital converter (205), and is used for calibrating the zero point of the digitized detection voltage (2D);
the input end of the comparison integrator (503) is connected with the output end of the zero point module (501) and is used for comparing the digitized detection voltage (2D) after zero point calibration with a set reference voltage to obtain a final error voltage;
the input end of the ALC open-loop control module (504) is connected with the output end of the comparison integrator (503) and is used for adding the final error voltage and the preset voltage to obtain a control voltage;
the input end of the logarithmic amplifier (505) is connected with the output end of the ALC open-loop control module (504), the output end of the logarithmic amplifier (505) is used as the output end of the digital chip (204), and is connected with the input end of the digital-to-analog converter (206) and used for carrying out logarithmic amplification on control voltage;
the digital chip (204) also comprises a square-opening module (502);
the input end of the square-on module (502) is connected with the output end of the zero point module (501), the output end of the square-on module (502) is connected with the input end of the comparison integrator (503), and the square-on module is used for reducing the digital detection voltage after zero point calibration from power amplitude to voltage amplitude to obtain a first detection voltage;
the comparison integrator (503) comprises a subtracter (511), an accumulator (512) and a linear amplifier (715);
the input end of the subtracter (511) is connected with the output end of the square-open module (502) and used for subtracting a first detection voltage from a set reference voltage to obtain a current error voltage;
the input end of the linear amplifier (715) is connected with the output end of the subtracter (511) and used for adjusting the multiplying power of the current error voltage;
the input end of the accumulator (512) is connected with the output end of the linear amplifier (715), and the output end of the accumulator (512) is connected with the input end of the ALC open-loop control module (504) and used for accumulating the current error voltage after multiplying power adjustment to obtain the final error voltage.
2. The measurement arrangement with ALC circuitry of claim 1, characterized in that the digital chip (204) further comprises: a linearity compensation module (702) and a sampling filter module (703);
the input end of the linearity compensation module (702) is connected with the output end of the zero point module (501) and is used for compensating the nonlinearity of the digitized detection voltage (2D) after zero point calibration;
the input end of the sampling filter module (703) is connected with the output end of the linearity compensation module (702), and the output end of the sampling filter module (703) is connected with the input end of the comparison integrator (503) and is used for oversampling the digitized detection voltage after nonlinear compensation;
the input end of the square-opening module (502) is connected with the output end of the sampling filter module (703).
3. The measurement arrangement having an ALC circuit of claim 1, wherein the digital chip (204) further includes a temperature compensation block therein for temperature compensating the ALC circuit.
4. The measurement arrangement with ALC circuitry of claim 1, characterized in that the ALC open loop control block (504) includes a switch (513), an error voltage block (514), a preset voltage block (515), and an adder (516);
when the ALC circuit is working normally, the switch (513) is closed; when the ALC circuit works in an open loop mode, the switch (513) is opened;
the error voltage module (514) is used for storing a preset error voltage or a final error voltage integrated by the comparison integrator (503);
the preset voltage module (515) is used for storing preset voltage;
the adder (516) is used for adding the final error voltage and the preset voltage to obtain the control voltage.
5. The measurement arrangement with ALC circuitry of claim 1, wherein the digital chip (204) further includes a voltage conversion block (506);
the input end of the voltage conversion module (506) is connected with the output end of the logarithmic amplifier (505) and is used for correcting nonlinearity between the attenuation of the adjustable radio frequency attenuator (201) and the control voltage.
6. The measurement arrangement with ALC circuitry of claim 5, wherein the voltage conversion block (506) includes a first stage linear amplifier (601) and a wavetable block (602);
the input end of the first-stage linear amplifier (601) is connected with the output end of the logarithmic amplifier (505) and is used for linearly changing the attenuation error;
the input end of the wavetable module (602) is connected with the output end of the first-stage linear amplifier (601) and is used for recording a nonlinear curve between the attenuation of the adjustable radio frequency attenuator (201) and the control voltage.
7. The measurement arrangement with ALC circuitry of claim 6, wherein the voltage conversion block (506) further comprises a second stage linear amplifier (603);
the input end of the second-stage linear amplifier (603) is connected with the output end of the wavetable module (602), and the output end of the second-stage linear amplifier (603) is used as the output end of the digital chip (204) and is connected with the input end of the digital-to-analog converter (206) for carrying out nonlinear change on the attenuation error.
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| CN109088648A (en) * | 2017-09-26 | 2018-12-25 | 南京正銮电子科技有限公司 | A kind of high speed Larger Dynamic fixed amplitude circuit |
| CN110543205A (en) * | 2019-08-07 | 2019-12-06 | 中电科仪器仪表有限公司 | method for improving dynamic range of vector network analyzer source under wide temperature condition |
| CN111181601B (en) * | 2019-11-22 | 2021-06-29 | 北京麦克斯韦科技有限公司 | Control system of quick response automatic level control loop |
| CN113848380B (en) * | 2021-10-22 | 2023-10-20 | 深圳市兆驰数码科技股份有限公司 | Power detection circuit and method, and direct current and phase detection system and method |
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