CN109088648A - A kind of high speed Larger Dynamic fixed amplitude circuit - Google Patents
A kind of high speed Larger Dynamic fixed amplitude circuit Download PDFInfo
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- CN109088648A CN109088648A CN201710888384.9A CN201710888384A CN109088648A CN 109088648 A CN109088648 A CN 109088648A CN 201710888384 A CN201710888384 A CN 201710888384A CN 109088648 A CN109088648 A CN 109088648A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Abstract
The embodiment of the invention discloses a kind of high speed Larger Dynamic fixed amplitude circuits.It include: FPGA module, several 30 decibels of fixed ampllitude units；Real-time rectified signal is input to the numerical-control attenuator by amplifier, and the power distribution module, the output of part rectified signal are input to after being decayed；Part rectified signal exports supreme dynamic cymoscope by power distribution module, high dynamic wave detector exports after carrying out detection to the rectified signal of input to A/D conditioner, A/D conditioner is input to A/D sampler after changing the rectified signal of input into computer receptible digital signal, and rectified signal is input to FPGA module after A/D sampler samples and is handled.The present invention is applicable in the demand of the quick fixed ampllitude gain control of receiver system internal closed loop, can enhance receiver adaptability, reduce microwave radar systems complexity.
Description
Technical field
The present invention relates to electronic engineering field more particularly to a kind of high speed Larger Dynamic fixed amplitude circuits.
Background technique
Dynamic range is frequently encountered in receiver system to expand and the unstable problem of reception gain.General solution
It is the operating mode combined using " sensitivity-frequency control " (STC) and " automatic growth control " (AGC).
STC working principle is after emitting pulse every time, to generate the control voltage gradually to go to zero at any time an of negative polarity,
The controlled stage of variable gain amplifier is supplied to realize sensitivity control.But control signal generally by signal processing system according to
The demand of machine system provides after specific aim is handled, its advantage is that extendable range is wide, but bad adaptability, control is multiple
It is miscellaneous.And agc circuit system suitability is strong, control is simple, but extendable narrow range under normal circumstances.
The circuit constituted mode that the present invention is combined using high dynamic detecting circuit and high speed, highly sensitive sample circuit,
With reasonable level mix proportion scheme, a closed loop High-speed Control network is formed inside receiver, is opened up to reach high dynamic
Exhibition, the effect of high speed controlling of amplitude.The method can enhance the adaptability of receiver, reduce the complexity of microwave receiving system.
Summary of the invention
The embodiment of the present invention provides a kind of high speed Larger Dynamic fixed amplitude circuit, can enhance the adaptability of receiver, reduces
The complexity of microwave receiving system.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
The method that the embodiment of the present invention provides, comprising: FPGA module, several 30 decibels of fixed ampllitude units；Described 30 decibels
Fixed ampllitude unit includes communication interface module, amplifier, numerical-control attenuator, power distribution module, high dynamic wave detector, A/D conditioning
Circuit, A/D sample circuit；
Real-time rectified signal is input to the numerical-control attenuator by the amplifier, is declined by the numerical-control attenuator
The power distribution module is input to after subtracting, a part of rectified signal is exported through the power distribution module；A part of detection letter
Number exported by the power distribution module to the high dynamic wave detector, the high dynamic wave detector to the rectified signal of input into
To the A/D conditioner, the A/D conditioner changes the rectified signal of input into computer receptible number for output after row detection
It is input to the A/D sampler after word signal, rectified signal is input to FPGA module after the A/D sampler samples and is divided
Analysis and processing export best parallel control signal by the communication interface modules to the numerical-control attenuator, reconcile institute in real time
State the attenuation of numerical-control attenuator.
Further, the rectified signal is analyzed and is handled using 3 30 decibels of fixed ampllitude units, utilize three road A/
D sample circuit realizes that the control of fixed ampllitude module passes through setting wherein different threshold values is respectively set in the A/D sample circuit
Decision logic realizes classification controlling of amplitude.
Further, the workflow of the FPGA are as follows:
1) A/D1 sampled value is detected, when A/D1 sampled value is less than lower threshold value, then attenuator 1 corresponding to A/D1 is unattenuated,
Jump directly to A/D2；When A/D1 sampled value is greater than lower threshold value, by comparing A/D calibration data base, control attenuator 1 is decayed,
After the completion of equal attenuators, A/D2 is skipped to；
2) A/D2 sampled value is detected, when A/D2 sampled value is less than lower threshold value, then attenuator 2 corresponding to A/D2 is unattenuated,
Jump directly to A/D3；When A/D2 sampled value is greater than lower threshold value, by comparing A/D calibration data base, control attenuator 2 is decayed,
After the completion of equal attenuators, A/D3 is skipped to；
3) A/D3 sampled value is detected, when A/D3 sampled value is less than lower threshold value, then attenuator 3 corresponding to A/D3 is unattenuated,
Jump directly to A/D1；When A/D3 sampled value is greater than lower threshold value, by comparing A/D calibration data base, control attenuator 3 is decayed,
After the completion of equal attenuators, A/D1 is skipped to；
4) above three step is repeated with this, completes fixed ampllitude overall process in real time.
Further, the A/D calibration data base include the upper threshold values of three A/D sample circuits, lower threshold value and
A/D detection data corresponds to the pad value of attenuator.
Further, the three road A/D decision logics are as follows:
1) it (is skipped if being no more than lower threshold value) after the detection of A/D1 sampled value is more than lower threshold value, indicates there is signal in A/D1
2us (bell signal of removal wave detector rising edge) is prolonged in input immediately；
2) it A/D1 multi collect data and is averaged, while compared with the A/D calibration data base of A/D1, controls corresponding
Attenuator 1 is decayed, and records average value at this time；
3) it repeats above-mentioned two step and is respectively completed the decaying that A/D2, A/D3 correspond to attenuator 2 and attenuator 3, work as completion
Afterwards, A/D1 is jumped to；
4) when the mean variation of the input signal average value of A/D1 and previous periodic recording is less than 1dB at this time for detection
When, keep No. three attenuator pad values not change；
5) when the input signal of A/D1 changes more than 1dB, the decaying of attenuator 1, attenuator 2 and attenuator 3 is removed
Value, and step 1 is repeated to 3 processes；
6) above-mentioned steps are repeatedly performed.
Further, the lower threshold value is the attenuator by the minimum attenuation thresholding calibrated, and works as input signal values
Attenuator is unattenuated when less than or equal to lower threshold value；
The upper threshold value is that the attenuator passes through the highest attenuation threshold calibrated, under input signal values are more than or equal to
Attenuator decaying is maximum when threshold value；
A/D calibration data base is when A/D value is between upper threshold value and lower threshold value, and the A/D value that is formed by calibration is in declining
Subtract the A/D calibration data base of device pad value corresponding relationship.
The utility model has the advantages that the present invention is to guarantee the accuracy of micro- wave control signal, using high dynamic detecting circuit as signal
Acquisition Circuit；By the reasonable disposition to level Acquisition Circuit, the interception acquisition optimal amplitude range of signal sensitivity is examined
Wave sampling, sample circuit is with high speed, high-precision A/D sampling A/D chip, and sampling resolution height is (to the electricity of 0.05V when practical application
Buckling has response), reaction speed is fast, and the data-signal after sampling is analyzed by high speed fpga chip, converted and normalized
Processing, exports best parallel control signal, and control signal adjusts numerical-control attenuator attenuation in real time, realizes entire control circuit
Quickly accurate fixed ampllitude output.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is circuit structure block diagram provided by the invention；
Fig. 2 is AGC unit schematic diagram provided by the invention；
Fig. 3 is fixed ampllitude module frame chart provided by the invention；
Fig. 4 is logarithmic amplification detecting circuit functional block diagram provided by the invention；
Fig. 5 is logafier test result provided by the invention；
Fig. 6 is that controlling of amplitude provided by the invention realizes block diagram.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, with reference to the accompanying drawing and specific embodiment party
Present invention is further described in detail for formula.Embodiments of the present invention are described in more detail below, the embodiment is shown
Example is shown in the accompanying drawings, and in which the same or similar labels are throughly indicated same or similar element or has identical or class
Like the element of function.It is exemplary below with reference to the embodiment of attached drawing description, for explaining only the invention, and cannot
It is construed to limitation of the present invention.Those skilled in the art of the present technique are appreciated that unless expressly stated, odd number shape used herein
Formula " one ", "one", " described " and "the" may also comprise plural form.It is to be further understood that specification of the invention
Used in wording " comprising " refer to that there are the feature, integer, step, operation, element and/or component, but it is not excluded that
In the presence of or add other one or more features, integer, step, operation, element, component and/or their group.It should be understood that
When we say that an element is " connected " or " coupled " to another element, it can be directly connected or coupled to other elements, or
There may also be intermediary elements.In addition, " connection " used herein or " coupling " may include being wirelessly connected or coupling.Here make
Wording "and/or" includes one or more associated any cells for listing item and all combinations.The art
Technical staff is appreciated that unless otherwise defined all terms (including technical terms and scientific terms) used herein have
Meaning identical with the general understanding of the those of ordinary skill in fields of the present invention.It should also be understood that such as general
Those terms, which should be understood that, defined in dictionary has a meaning that is consistent with the meaning in the context of the prior art, and
Unless defined as here, it will not be explained in an idealized or overly formal meaning.
The embodiment of the present invention provides a kind of high speed Larger Dynamic fixed amplitude circuit, as illustrated in fig. 1 and 2, comprising: if FPGA module,
Do 30 decibels of fixed ampllitude units；30 decibels of fixed ampllitude units include communication interface module, amplifier, numerical-control attenuator, power point
With module, high dynamic wave detector, A/D conditioning circuit, A/D sample circuit；Real-time rectified signal is input to by the amplifier
The numerical-control attenuator is input to the power distribution module, a part of detection letter after being decayed by the numerical-control attenuator
It number is exported through the power distribution module；A part of rectified signal is exported by the power distribution module to the high dynamic detection
Device, output to the A/D conditioner, the A/D improves after the high dynamic wave detector carries out detection to the rectified signal of input
Device is input to the A/D sampler, the A/D sampling after changing the rectified signal of input into computer receptible digital signal
Rectified signal is input to FPGA module after device sampling to be analyzed and handled, exports best parallel control signal by described logical
Believe that interface module to the numerical-control attenuator, reconciles the attenuation of the numerical-control attenuator in real time.
There are higher dynamic range, stabilizing output level in reception system of the invention.In order to guarantee the dynamic of receiving channel
State range uses AGC (automatic gain control circuit) in design, and circuit includes controllable attenuator circuit, coupling circuit, detection electricity
Road, controlling of amplitude circuit, realization principle such as Fig. 2.
1) controllable attenuation circuit design
Main device of the 6 numerical-control attenuator chips of HITTITE company as high dynamic AGC unit circuit is selected in design
Part, chip 0.5dB are basic decaying stepping, and maximum control attenuation is 31.5dB.
2) detecting circuit designs
In order to guarantee to stablize output in system large dynamic range, need to propose detecting circuit linear under Larger Dynamic
Wide dynamic logarithmic detector circuit is selected in detection requirement for requiring, in design.
Fig. 3 is logarithmic amplification detecting circuit functional block diagram.In order to realize the fixed ampllitude linear convergent rate of system high dynamic, need
It receives internal system and realizes multiple AGC control (each Regime during recession 0dB~25dB), by AGC control unit rational deployment, so that
Rectified signal control reduces detection error in linear zone, and the linearity of the receiving channel in Larger Dynamic adjustment is effectively ensured.
In order to guarantee to stablize output in system large dynamic range, need to propose detecting circuit linear under Larger Dynamic
Wide dynamic logarithmic detector circuit is selected in detection requirement for requiring, in design.Fig. 4 is logarithmic amplification detecting circuit principle frame
Figure.
Fig. 5 is the test result of test specimen, and circuit has preferably in -45dBm~-10dBm input in actual use
Dynamic characteristic, increase filter circuit in rf inputs mouth, reduce in-band noise and miscellaneous influence of the spectrum to sensitivity, improve dynamic
State range.
Fig. 6 is controlling of amplitude circuit, is acquired using the AD9226 of A/DI sample circuit as the data of controlling of amplitude circuit
Device controls A/D by the FPGA of INTEL and carries out data acquisition, controls attenuator circuit again finally by data analysis and realizes fixed ampllitude
Function.
For the precision and efficiency for guaranteeing fixed ampllitude, we are repeated calibration fixed amplitude circuit by instrument, finally establish amplitude
With the database of adjustable attenuation code.
It is found after calibration, (the detecting circuit amplitude output signal variation when input signal changes a detection stepping
30mv-40mv), the quantized values of A/D change about 80 units, therefore fixed ampllitude precision can be realized the variation of detection stepping.
For the reaction rate for guaranteeing controlling of amplitude circuit, FPGA work uses 40MHz clock, it is discovered by experiment that when outer
The amplitude of portion's input rectified signal is when changing, and when amplitude of variation is greater than 30mv, fixed ampllitude function acts in 1us, sufficiently
It ensure that the fast reaction of controlling of amplitude circuit.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for equipment reality
For applying example, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to embodiment of the method
Part explanation.The above description is merely a specific embodiment, but protection scope of the present invention is not limited to
This, anyone skilled in the art in the technical scope disclosed by the present invention, the variation that can readily occur in or replaces
It changes, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claim
Subject to enclosing.
Claims (6)
1. a kind of high speed Larger Dynamic fixed amplitude circuit characterized by comprising FPGA module, several 30 decibels of fixed ampllitude units；It is described
30 decibels of fixed ampllitude units include communication interface module, amplifier, numerical-control attenuator, power distribution module, high dynamic wave detector, A/
D conditioning circuit, A/D sample circuit；
Real-time rectified signal is input to the numerical-control attenuator by the amplifier, after being decayed by the numerical-control attenuator
It is input to the power distribution module, a part of rectified signal is exported through the power distribution module；A part of rectified signal by
The power distribution module is exported to the high dynamic wave detector, and the high dynamic wave detector examines the rectified signal of input
To the A/D conditioner, the A/D conditioner, which changes the rectified signal of input into computer receptible number, to be believed for output after wave
Be input to the A/D sampler after number, after the A/D sampler samples by rectified signal be input to FPGA module carry out analysis and
Processing, exports best parallel control signal by the communication interface modules to the numerical-control attenuator, number described in real-time control
Control the attenuation of attenuator.
2. a kind of high speed Larger Dynamic fixed amplitude circuit according to claim 1, which is characterized in that use 3 30 decibels of fixed ampllitude lists
Member is analyzed and is handled to the rectified signal, and the control of fixed ampllitude module is realized using three road A/D sample circuits, wherein described
Different threshold values is respectively set in A/D sample circuit, realizes classification controlling of amplitude by the decision logic of setting.
3. a kind of high speed Larger Dynamic fixed amplitude circuit according to claim 1, which is characterized in that the workflow of the FPGA
Are as follows:
1) A/D1 sampled value is detected, when A/D1 sampled value is less than lower threshold value, then attenuator 1 corresponding to A/D1 is unattenuated, directly
Skip to A/D2；When A/D1 sampled value is greater than lower threshold value, by comparing A/D calibration data base, control attenuator 1 decays, waits and decline
After the completion of subtracting device, A/D2 is skipped to；
2) A/D2 sampled value is detected, when A/D2 sampled value is less than lower threshold value, then attenuator 2 corresponding to A/D2 is unattenuated, directly
Skip to A/D3；When A/D2 sampled value is greater than lower threshold value, by comparing A/D calibration data base, control attenuator 2 decays, waits and decline
After the completion of subtracting device, A/D3 is skipped to；
3) A/D3 sampled value is detected, when A/D3 sampled value is less than lower threshold value, then attenuator 3 corresponding to A/D3 is unattenuated, directly
Skip to A/D1；When A/D3 sampled value is greater than lower threshold value, by comparing A/D calibration data base, control attenuator 3 decays, waits and decline
After the completion of subtracting device, A/D1 is skipped to；
4) above three step is repeated with this, completes fixed ampllitude overall process in real time.
4. a kind of high speed Larger Dynamic fixed amplitude circuit according to claim 3, which is characterized in that the A/D calibration data base packet
The upper threshold value, lower threshold value and A/D detection data for including three A/D sample circuits correspond to the pad value of attenuator.
5. a kind of high speed Larger Dynamic fixed amplitude circuit according to claim 1, which is characterized in that the three road A/D judgement is patrolled
Volume are as follows:
1) it after the detection of A/D1 sampled value is more than lower threshold value, is skipped if being no more than lower threshold value, indicates there is signal input in A/D1,
Prolong 2us immediately, removes the bell signal of wave detector rising edge；
2) it A/D1 multi collect data and is averaged, while compared with the A/D calibration data base of A/D1, controlling corresponding decaying
Device 1 is decayed, and records average value at this time；
3) it repeats above-mentioned two step and is respectively completed the decaying that A/D2, A/D3 correspond to attenuator 2 and attenuator 3, when after the completion, jump
Go to A/D1；
4) it when the mean variation of the input signal average value of A/D1 and previous periodic recording is less than 1dB at this time for detection, protects
No. three attenuator pad values are held not change；
5) when the input signal of A/D1 changes more than 1dB, the pad value of attenuator 1, attenuator 2 and attenuator 3 is removed, and
Step 1 is repeated to 3 processes；
6) above-mentioned steps are repeatedly performed.
6. according to a kind of high speed Larger Dynamic fixed amplitude circuit of claim 3 or 5, which is characterized in that the lower threshold value is institute
Attenuator is stated by the minimum attenuation thresholding calibrated, attenuator is unattenuated when input signal values are less than or equal to lower threshold value；
The upper threshold value is that the attenuator passes through the highest attenuation threshold calibrated, when input signal values are more than or equal to lower threshold value
When attenuator decaying it is maximum；
A/D calibration data base is when A/D value is between upper threshold value and lower threshold value, and the A/D value formed by calibration is in attenuator
The A/D calibration data base of pad value corresponding relationship.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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