CN214480520U - Circuit for alpha and beta pulse signal digital processing - Google Patents
Circuit for alpha and beta pulse signal digital processing Download PDFInfo
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- CN214480520U CN214480520U CN202120716615.XU CN202120716615U CN214480520U CN 214480520 U CN214480520 U CN 214480520U CN 202120716615 U CN202120716615 U CN 202120716615U CN 214480520 U CN214480520 U CN 214480520U
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Abstract
A circuit for digital processing of alpha and beta pulse signals relates to the technical field of radionuclide measurement and comprises an analog signal regulating unit, an ADC module and a digital processing unit; the analog signal adjusting unit comprises a charge sensitive preamplifier, a zero cancellation circuit, a signal amplifier and a base line restorer which are sequentially connected; the digital processing unit comprises a forming module, an accumulation judging module and an amplitude measuring module, wherein the forming module comprises a fast forming module and a slow forming module, the fast forming module is connected with the accumulation judging module, and the slow forming module and the accumulation judging module are both connected with the amplitude measuring module; the output end of the baseline restorer is connected with the input end of the ADC module, and the output end of the ADC module is respectively connected with the input ends of the fast forming module and the slow forming module. Compared with the traditional discrimination circuit, the circuit has the advantages of real-time performance, miniaturization and high stability.
Description
Technical Field
The utility model relates to a radionuclide measures technical field, in particular to a circuit that is used for alpha, beta pulse signal digital processing.
Background
The traditional alpha and beta signal Analog screening method is mainly realized by an Analog electronic circuit, triggering is completed by a pulse amplitude analyzer and a clock pulse generator, measurement is completed by an ADC (Analog-to-Digital Converter) and a shaper, all processes can be completed by manual repeated debugging, the new particle Digital screening method can complete measurement of energy and time and triggering and waveform recording only by a system front end, the waveform screening process can be performed by related software, and manual interference is not needed in the whole process. Therefore, the traditional analog pulse waveform discrimination method has more and more obvious limitation, and the digital nuclear pulse waveform discrimination technology is an effective way for solving the problem and is widely concerned by people.
The digital screening technology for alpha and beta particles integrates an algorithm into a digital processing module, and different particles are screened out according to different characteristics (amplitude, waveform and the like) of signals after the output signals of a detector are subjected to digital processing.
SUMMERY OF THE UTILITY MODEL
To the defect that exists among the above-mentioned prior art simulation pulse waveform discriminates, the to-be-solved technical problem of the utility model is to provide a circuit that is used for alpha, beta pulse signal digital processing, have real-time, miniaturized, advantage that stability is high.
In order to solve the technical problem, the utility model discloses a technical scheme as follows: a circuit for digital processing of alpha and beta pulse signals comprises an analog signal conditioning unit, an ADC module and a digital processing unit.
Further, the analog signal adjusting unit comprises a charge sensitive preamplifier, a zero cancellation circuit, a signal amplifier and a baseline restorer which are sequentially connected, wherein the charge sensitive preamplifier is externally connected with a detector.
Further, the digital processing unit comprises a forming module, an accumulation judging module and an amplitude measuring module, wherein the forming module comprises a fast forming module and a slow forming module, the fast forming module is connected with the accumulation judging module, and the slow forming module and the accumulation judging module are both connected with the amplitude measuring module.
Further, the output end of the baseline restorer is connected with the input end of the ADC module, and the output end of the ADC module is respectively connected with the input ends of the fast forming module and the slow forming module.
Further, the alpha and beta pulse signals input into the analog signal adjusting unit are adjusted by the charge sensitive amplifier, the zero-pole cancellation circuit and the baseline restorer and then output to the ADC module, and the ADC module performs analog-to-digital conversion and then inputs into the digital processing unit for digital processing.
Preferably, the ADC module uses a chip with model AD9235 as a core chip.
Preferably, the charge sensitive preamplifier is formed by connecting a JFET (junction field effect transistor) with the model number of 2N4416, a triode with the model number of 2N2904, two triodes with the model number of 2N1711, a resistor and a capacitor;
preferably, the chip model of the signal amplifier is AD8065 ART.
Preferably, the model of the chip adopted by the digital processing unit is EP4CE10E22C 8.
Preferably, the power input end of the charge sensitive preamplifier is externally connected with a high-voltage power supply module of the detector.
Further, the signal output end of the detector is connected with the analog signal regulating unit through the input end of the chip 2N4416, the output end of the analog signal regulating unit is connected with the ADC module through the VIN + pin of the chip AD9235BRU-65, and the output pins D1-D11 of the ADC module are connected with the digital processing unit through the I/O interface of the chip EP4CE10E22C 8.
Furthermore, the charge sensitive preamplifier is externally connected with a detector and used for converting the output current pulse signal into an exponential voltage pulse signal, the exponential voltage pulse signal is subjected to undershoot removal through a zero-pole cancellation circuit and then is input into a signal amplifier for signal amplification and filtering forming, and a baseline restorer tracks the change of a baseline and is used for obtaining the input signal level of the ADC module through recording and processing the baseline level before and after the signal arrives; the signal level is converted into a digital pulse signal through an ADC module; the digital pulse signal is input into the digital processing unit and divided into two paths of signals, one path of signal is input into the accumulation judging module through the fast forming module, the accumulation judging module is used for extracting the time information of the pulse and generating a control signal to be input into the amplitude measuring module, and the control signal is used for controlling the amplitude measuring module to realize baseline acquisition, peak acquisition and amplitude measurement; and the other path of signal is input into an amplitude measuring module through a slow forming module, and the amplitude measuring module is used for measuring and outputting an amplitude value according to a base line value and a peak value.
The utility model discloses the beneficial effect who gains lies in: the signal output by the detector is processed by an exponential voltage signal output by a charge sensitive preamplifier in an analog signal regulating unit, then the exponential voltage signal is converted into a digital pulse signal by an ADC module, and finally the digital pulse signal is input into a digital processing unit to be processed to measure the amplitude; different particles are screened according to different amplitudes of signals by combining a pulse amplitude screening method in the prior art, so that the digital processing screening analysis and measurement of alpha and beta pulse signals are realized; compared with the traditional discrimination circuit, the circuit has the advantages of real-time performance, miniaturization and high stability.
Drawings
Fig. 1 is a schematic block diagram of signal processing of the present embodiment;
FIG. 2 is a diagram of a charge sensitive preamplifier in the analog signal conditioning unit of the present embodiment;
FIG. 3 is a circuit diagram of an analog signal conditioning unit in the present embodiment;
FIG. 4 is a circuit diagram of an ADC module according to the present embodiment;
FIG. 5 is a circuit diagram of a digital processing unit according to the present embodiment;
FIG. 6 is a circuit diagram of a power supply configuration of the digital processing unit in this embodiment
Fig. 7 is a circuit diagram of the high-voltage power module in this embodiment.
Detailed Description
In order to facilitate understanding of those skilled in the art, the present invention will be further described with reference to the following examples and drawings, which are not intended to limit the present invention.
As shown in FIG. 1, a circuit for digital processing of alpha and beta pulse signals comprises an analog signal conditioning unit, an ADC module and a digital processing unit.
Specifically, the analog signal conditioning unit functions to amplify the amplitude of the signal output from the detector, adjust the baseline, and convert the signal into a signal that satisfies the requirements of the subsequent ADC and digital forming circuit. The analog signal adjusting unit comprises a charge sensitive preamplifier, a zero cancellation circuit, a signal amplifier and a base line restorer which are sequentially connected; the signal output by the charge sensitive preamplifier is prone to accumulation and undershoot. In order to eliminate the phenomenon, a polar-zero cancellation circuit and a baseline restorer are adopted to improve the waveform, undershoot and the like generated by an RC (Resistor-capacitor) circuit are eliminated, and a signal baseline is set so that the signal meets the requirement of the ADC on the baseline.
Specifically, the ADC module is a module that is necessary before the signal passes through the analog signal conditioning unit and enters the digital processing unit. The nuclear pulse signal output from the analog signal regulating unit is sampled into a digital signal to form a digital pulse signal, and then the digital pulse signal is input to the digital processing unit for digital processing.
Specifically, the digital processing unit comprises a forming module, an accumulation judging module and an amplitude measuring module, wherein the forming module comprises a fast forming module and a slow forming module, the fast forming module is connected with the accumulation judging module, and the slow forming module and the accumulation judging module are both connected with the amplitude measuring module; the fast forming module is used for extracting the time information of the pulse when the forming parameter is small, and converting the index signal into a narrower trapezoidal pulse signal, so that the anti-noise capability is weak; the slow forming module has large forming parameters, is mainly used for extracting the peak values of the base line and the trapezoidal flat top, converts the index signal into a wider trapezoidal pulse signal and has stronger anti-noise capability.
The present invention will be further explained by using the specific embodiment of discriminating the α and β pulse signals.
Specifically, the α and β signal discrimination is mainly performed based on the difference between signals output after different incident particles enter a detector. The alpha and beta signal discrimination mainly comprises two methods of pulse amplitude discrimination and pulse shape discrimination.
In this embodiment, the PIPS detector is selected as the detector, because the difference between the waveforms of the α and β signals output by the PIPS detector in the pulse shape is not large, and the PIPS detector is a detector with high energy spectrum resolution, particularly at the high energy end, the α particle is a high energy particle with a positive charge, and therefore the counting rate of the α particle during α and β measurement is easily measured. Therefore, in this embodiment, the α and β signals are distinguished by using a pulse amplitude discrimination method.
Specifically, energy difference between an alpha signal and a beta signal is utilized, the alpha signal and the beta signal are converted into an exponential voltage signal through an analog signal regulating unit, the exponential voltage signal is converted into a digital signal through an ADC module, the digital signal is input into a digital processing unit for signal processing and amplitude determination, and amplitude discrimination is carried out.
Dividing the measured pulse signal into equal parts according to amplitude rangenThe amplitude intervals, which are divided into 1024 amplitude intervals in the amplitude processing in this embodiment, are then measured for the number of pulses in each "amplitude interval" to finally obtain the pulse amplitude distribution curve of the input signal. Because the pulse amplitude of the alpha signal is larger and the pulse amplitude of the beta signal is smaller, the alpha and beta particles can be distinguished on a pulse amplitude distribution curve obtained after the pulse signals of the alpha and beta particles are subjected to pulse amplitude analysis.
In particular, the PIPS detector outputs a small charge signal that is highly susceptible to interference from electromagnetic fields, and long distance transmission over the line will produce a large amount of electronic noise interference, which may be much greater in magnitude than the detector itselfA signal; therefore, a charge sensitive preamplifier needs to be added near the PIPS detector to perform primary processing on the detector signal, so that the probability of detector signal loss can be reduced. The charge sensitive preamplifier is mainly formed by connecting and building a JFET tube with the model number of 2N4416, a triode with the model number of 2N2904, two triodes with the model number of 2N1711, a resistor and a capacitor, as shown in figure 2. The JFET tube is used as the first stage of amplification, the input impedance is large, and the drain current isI DSS The maximum energy can reach 10mA, and the low-frequency transconductance is 7500uS at most.
As shown in fig. 3, a chip of model AD8065ART was selected as a chip of the signal amplifier. AD8065ART is FET input amplifier, and can be known from its product manual, its bandwidth is 145Hz, the slew rate is 180V/S, the common mode rejection ratio is-100 dB, the power consumption of each amplifier is 6.4mA, have advantages such as small in noise, high speed and low power consumption of input impedance. The exponential voltage signal output by the charge sensitive preamplifier is amplified and filtered and shaped by the signal amplifier, so that the amplitude range of the signal meets the sampling range of an ADC in a subsequent circuit. The output signal amplitude of the signal amplifier should be proportional to the input signal with good linearity and gain stability.
Since the signal output from the charge sensitive preamplifier is an exponentially decaying pulse signal, and is not a step signal, such a signal is likely to accumulate, and it is necessary to differentiate the signal in order to reduce the accumulation. After passing through the differentiating circuit, the waveform of an exponentially decaying pulse signal generates an undershoot phenomenon. Undershoot can cause the blocking of the amplifier and thus cannot be counted during the recovery time; it is desirable to improve the output waveform by removing waveform undershoot phenomena through a pole-zero cancellation circuit.
Specifically, the baseline restorer functions to eliminate baseline shifts and fluctuations. After the pulse signal is amplified and filtered, a tail part with delayed attenuation is generated due to the impact response of the system, and the tail part accumulation can cause baseline shift. The baseline restorer records the baseline level before and after the signal reaches by tracking the change of the baseline, and the signal level which can be input into the ADC module is obtained by processing.
Specifically, the nulling circuit and the baseline restorer are common technical means for analog signal processing, and are not described in detail in this embodiment.
In the present invention, the ADC module is an important component, and therefore, the selection of the ADC module chip is very important. Before data processing, the digital signal processing circuit needs to discretize the signal output from the analog signal conditioning unit to form a digitized pulse signal and then process the digitized pulse signal. The device selection of the ADC module directly affects the sampling speed and accuracy of digital signal processing. In order to avoid aliasing signals after sampling by the ADC module, a high-speed ADC core element needs to be used to increase the sampling frequency and completely retain high-frequency information in the signals as much as possible, so that the ADC module in this embodiment uses a chip with a model number of AD9235 as a core chip. A12-bit AD9235 chip has a sampling rate of 20MSPS, and can sample 40 points when the pulse width of a nuclear pulse signal is 2 mus. The schematic circuit diagram of the ADC module in this embodiment is shown in fig. 4.
Particularly, the utility model provides a digital processing unit has advantages such as the integrated level is high, logic design ability is strong, parallel processing is fast, the low power dissipation, carries out the burden that nuclear pulse signal processing algorithm can make the treater with digital processing unit and alleviates greatly, and system dead time reduces, and the count through rate of system improves. The digital processing unit is used for carrying out signal digital processing, and the digital pulse signal obtained by sampling of the ADC module is finally measured and an amplitude value is output.
The signal input into the digital processing unit is divided into two paths of signals, one path of signal is input into the accumulation judging module through the fast forming module, the accumulation judging module is input into the amplitude measuring module through generating a control signal for controlling the amplitude measuring module to realize baseline acquisition, peak acquisition and amplitude measurement, the other path of signal is input into the amplitude measuring module through the slow forming module, the other path of signal is used for extracting a baseline value and peak value measuring amplitude through the amplitude measuring module, and the amplitude is output by the amplitude measuring module and is input into the PC end through the communication module.
Specifically, the fast shaping module and the slow shaping module may be a fast shaping circuit and a slow shaping circuit, which belong to the prior art and are not described in detail in this embodiment.
Preferably, the digital processing unit employs an EP4CE10E22C8 chip that requires peripheral circuitry, including: as shown in fig. 5 and 6, those skilled in the art know that the chip can be used only after being programmed and packaged, and therefore, details thereof are not repeated in this embodiment.
In this embodiment, the power input terminal of the charge sensitive preamplifier is externally connected with the high voltage power supply module of the detector, and the power supply affects the stability of the whole system, and has the advantages of stability, reliability, high precision and small ripple. In an alpha and beta particle signal measuring system, the indexes such as sensitivity, counting rate, signal-to-noise ratio and the like are greatly influenced by the precision and ripple of a power supply. In the embodiment, the high voltage of the PIPS detector is selected to be +70V, so that the capability resolution is favorably improved, and a stable power supply is the basis for normal operation of the system. In order to obtain better detection results, the power supply high-voltage module needs very low ripple, so the integrated high-voltage module is selected and added with a multi-stage filter circuit on the basis of the integrated high-voltage module to ensure that the ripple noise and the power supply disturbance are reduced to a small enough range and the performance of the PIPS detector is exerted as high as possible.
The detector signal is very weak, and the charge sensitive preamplifier is required to have very high amplification factor, and the very high amplification factor can also amplify the power supply disturbance at the same time, so that the power supply for supplying power to the charge sensitive preamplifier is required to be as stable as possible, and the ripple wave is required to be very small. In view of this, the very low noise regulator chip with a wide input voltage, a small volume, easy integration, and low regulated noise, which is the model number TPS7a3001 and TPS7a4901, is selected as the core chip in the present embodiment. The circuit diagram of the detector high voltage module is shown in fig. 7.
The charge sensitive preamplifier is externally connected with a detector and used for converting a signal output by the detector into an exponential voltage signal, then processing the exponential voltage signal, converting the exponential voltage signal into a digital pulse signal through an ADC (analog to digital converter) module, and finally inputting the digital pulse signal into a digital processing unit for processing and measuring the amplitude; compared with the traditional discrimination circuit, the circuit has the advantages of real-time performance, miniaturization and high stability.
The above embodiments are preferred implementations of the present invention, and the present invention can be implemented in other ways without departing from the spirit of the present invention.
Some of the drawings and descriptions of the present invention have been simplified to facilitate the understanding of the improvements over the prior art by those skilled in the art, and some other elements have been omitted from this document for the sake of clarity, and it should be appreciated by those skilled in the art that such omitted elements may also constitute the subject matter of the present invention.
Claims (8)
1. A circuit for digitizing α, β pulse signals, comprising: the device comprises an analog signal adjusting unit, an ADC module and a digital processing unit;
the analog signal adjusting unit comprises a charge sensitive preamplifier, a zero cancellation circuit, a signal amplifier and a baseline restorer which are sequentially connected, wherein the charge sensitive preamplifier is externally connected with a detector;
the digital processing unit comprises a forming module, an accumulation judging module and an amplitude measuring module, wherein the forming module comprises a fast forming module and a slow forming module, the fast forming module is connected with the accumulation judging module, and the slow forming module and the accumulation judging module are both connected with the amplitude measuring module;
the output end of the baseline restorer is connected with the input end of the ADC module, and the output end of the ADC module is respectively connected with the input ends of the fast forming module and the slow forming module;
the alpha and beta pulse signals input into the analog signal adjusting unit are adjusted by a charge sensitive amplifier, a zero cancellation circuit and a baseline restorer and then output to an ADC module, and the ADC module performs analog-to-digital conversion and then inputs into a digital processing unit for digital processing.
2. The circuit for the digital processing of α, β pulse signals according to claim 1, wherein: the ADC module adopts a chip with the model number of AD9235 as a core chip.
3. The circuit for the digital processing of α, β pulse signals according to claim 1, wherein: the charge sensitive preamplifier is formed by connecting a JFET (junction field effect transistor) tube with the model number of 2N4416, a triode with the model number of 2N2904, two triodes with the model number of 2N1711, a resistor and a capacitor.
4. The circuit for the digital processing of α, β pulse signals according to claim 1, wherein: the chip model of the signal amplifier is AD8065 ART.
5. The circuit for the digital processing of α, β pulse signals according to claim 1, wherein: the model of the chip adopted by the digital processing unit is EP4CE10E22C 8.
6. The circuit for the digital processing of α, β pulse signals according to claim 1, wherein: and the power supply input end of the charge sensitive preamplifier is externally connected with a high-voltage power supply module of the detector.
7. The circuit for the digital processing of α, β pulse signals according to any of claims 1-6, wherein: the signal output end of the detector is connected with an analog signal adjusting unit through the input end of a chip 2N4416, the output end of the analog signal adjusting unit is connected with an ADC module through a VIN + pin of a chip AD9235BRU-65, and output pins D1-D11 of the ADC module are connected with a digital processing unit through an I/O interface of a chip EP4CE10E22C 8.
8. The circuit for the digital processing of α, β pulse signals according to any of claims 1-6, wherein:
the charge sensitive preamplifier is externally connected with a detector and used for converting a current pulse signal output by the detector into an exponential voltage pulse signal, the exponential voltage pulse signal is subjected to undershoot removal through a zero-cancellation circuit and then is input into a signal amplifier for signal amplification and filtering forming, and a baseline restorer tracks the change of a baseline and is used for obtaining the input signal level of the ADC module through recording and processing the baseline level before and after the signal arrives;
the signal level is converted into a digital pulse signal through an ADC module;
the digital pulse signal is input into the digital processing unit and divided into two paths of signals, one path of signal is input into the accumulation judging module through the fast forming module, the accumulation judging module is used for extracting pulse time information and generating a control signal to be input into the amplitude measuring module, and the control signal is used for controlling the amplitude measuring module to realize baseline acquisition, peak acquisition and amplitude measurement; and the other path of signal is input into an amplitude measuring module through a slow forming module, and the amplitude measuring module is used for measuring and outputting an amplitude value according to a baseline value and a peak value.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117749130A (en) * | 2023-11-30 | 2024-03-22 | 西安朗弘核仪器有限公司 | Nuclear pulse fast attenuation circuit device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117749130A (en) * | 2023-11-30 | 2024-03-22 | 西安朗弘核仪器有限公司 | Nuclear pulse fast attenuation circuit device |
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