CN112737534B - Ionization chamber charge signal reading method - Google Patents
Ionization chamber charge signal reading method Download PDFInfo
- Publication number
- CN112737534B CN112737534B CN202011536817.2A CN202011536817A CN112737534B CN 112737534 B CN112737534 B CN 112737534B CN 202011536817 A CN202011536817 A CN 202011536817A CN 112737534 B CN112737534 B CN 112737534B
- Authority
- CN
- China
- Prior art keywords
- circuit
- charge
- integrator
- voltage
- dac
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000005070 sampling Methods 0.000 claims abstract description 47
- 230000010354 integration Effects 0.000 claims abstract description 43
- 238000007599 discharging Methods 0.000 claims abstract description 42
- 230000006641 stabilisation Effects 0.000 claims abstract description 4
- 238000011105 stabilization Methods 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 25
- 238000012937 correction Methods 0.000 claims description 21
- 230000000630 rising effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/70—Charge amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
Abstract
The invention provides an ionization chamber charge signal reading method, which comprises the following steps: automatic circuit calibration of zero input zero output mode before integration begins; based on automatic integral sampling in the voltage stabilization domain after circuit calibration; the negative and positive charges are offset to finish automatic discharge by loading reverse voltage; the ADC re-enters the integration sample from the next sampling period. The invention overcomes the traditional prejudice that the integrator must be sampled and discharged by disconnecting the relevant circuit. The automatic discharging process of the integrator utilizes the principle of applying forward current and reverse current to the input end of the integrator, so that positive and negative charges formed by positive and negative currents are mutually offset, and the problem of dead time of the integrator due to charge loss caused by sampling circuit breaking and discharging short circuit is solved through an automatic calibration circuit and an automatic discharging circuit.
Description
Technical Field
The invention belongs to the field of accelerators, and particularly relates to an ionization chamber charge signal reading method.
Background
Digital readout of weak signals typically uses three methods: the first method is current-voltage real-time conversion+ADC, which can analyze the specific details of the signal, but has large data size, high cost and complex system; the second method is a current frequency conversion + counter, which is a time period processing method for converting current into pulse output, wherein a single pulse represents a fixed charge amount, and the method has low implementation cost but large technical difficulty; the third approach is to gate the integrator + ADC. The charge integrator integrates the charge signal directly into the integrating capacitance in the circuit using the concept of virtual ground of the amplifier input, so that the output of the amplifier is the output of the sum of all the charge amounts.
The third approach, while currently commonly employed, is still undesirable: the integrator, when in a hold state or discharge state, can create a "dead time" that causes inaccurate readout of the ionization chamber charge signal.
The "dead time" generated by the integrator sampling phase: any electronic amplifier itself has a bias voltage and bias current, and the integrating capacitor itself has a leakage current, which both causes errors in charge conversion. Such errors will only occur during the integrator operating conditions. The prior art solves the problems that: when the total output of the charges needs to be measured, the integrator stops working: the integrator is deactivated by opening the path between the integrating capacitor and the input charge, so that the voltage across the integrator stabilizes and a charge reading is accurately performed. However, the source of the charge is not pinched off during the hold state of the integrator, and the charge simply flows not to the integrator but elsewhere, and the charge is leaked by the integrator during the period of time, which is called the "dead time" when the integrator is in the hold state.
The "dead time" generated by the integrator discharge phase: as shown in fig. 1, when the integrator discharges, S1 is turned on, S2 is turned off, and after S2 is turned off, the capacitor is shorted to generate a discharge, but the integrator discharges for a period of time, but the source of the charge input is not turned off, but the branch of the charge to the integrator is opened by S1, but because the source of the charge is not turned off, the charge does not flow to the integrator but flows to other branches (other branches are not labeled in fig. 1), and the charge for this period of time is leaked by the integrator, which is called "dead time" when the integrator is in a discharge state.
To sum up, the "dead time" of the integrator in the hold state is because when the total output of the charges needs to be measured, the integrator is stopped, the path between the capacitor and the charges is disconnected, and the charges flow to other branches to generate the "dead time"; the "dead time" of the integrator in the discharge state is because when a discharge of charge is required, the charge branch circuit to the integrator is cut off, causing charge to flow to the other branches, creating a "dead time".
Disclosure of Invention
The invention provides an ionization chamber charge signal reading method for solving the problems existing in the prior art, and aims to solve the problems that in the prior art, a charge integrating circuit has dead time in a holding state or a discharging state of an integrator, and the ionization chamber charge signal reading is inaccurate.
The invention provides the following technical proposal for solving the technical problems
An ionization chamber charge signal reading method, which is based on an ionization chamber charge signal reading device, the device comprises a charge integration circuit and an analog converter ADC arranged at the output end of the charge integration circuit, and is characterized in that: a discharging circuit for realizing automatic discharging, a calibration circuit for calibrating a difference value and a DSP control unit for controlling the discharging circuit and the calibration circuit are also arranged between the input end and the output end of the charge integration circuit, and the DSP control unit is arranged on the same side as the output end of the charge integration circuit;
the method is characterized in that: the method comprises the following steps:
step one, calibrating an automatic circuit in a zero input and zero output mode before integration begins;
step two, automatic integral sampling in a voltage stabilization domain based on circuit calibration;
thirdly, the negative charge and the positive charge are offset to finish automatic discharge by loading reverse voltage;
and step four, the ADC starts to enter the integration sampling again from the next integration period.
The specific process of the first step is as follows:
1) The signal of the input end of the current integrating circuit is set to be zero;
2) The DSP detects whether the signal of the output end of the current integrating circuit is zero;
if the difference value is not zero, continuing to perform the process 3), and if the difference value is zero, ending without circuit calibration;
3) The DSP gives a calibration digital signal to the DAC;
4) The DAC outputs a correction voltage signal to the correction resistor R to form correction current;
5) The correction current is returned to the integrator signal input;
6) And when the input end has no signal input and the output end integral voltage output is zero, the calibration is completed.
The specific process is as follows:
1) The charge source inputs charges to the integrator;
2) Integrating voltage sampling by an integrator;
3) The DSP judges whether sampling is carried out for 3 times continuously;
if less than 3 times return to process 2), if equal to 3 times, enter the discharge process of step three.
The specific process is as follows:
1) The DSP sends a reverse voltage signal to the DAC after the 3 rd sampling period of one integration period is completed, and the amplitude of the reverse voltage signal is set according to the sampling value of the integrated voltage of the previous three times;
2) The DAC applies reverse voltage to the discharge resistor;
3) The positive and negative charges on the integrator capacitor cancel to complete automatic discharge.
The DAC outputs a reverse voltage to the discharge resistor to form a reverse current, and the reverse current forms a reverse charge under the pulse action of a certain pulse width, and the reverse charge and the forward charge on the integrator are mutually counteracted.
The specific process is as follows:
1) After the positive and negative charges are counteracted, the ADC waits for entering the first sampling period of the next integration period;
2) The ADC starts integrating voltage sampling on the rising edge of the first sampling period of the next integration period.
Advantageous effects of the invention
The invention overcomes the traditional prejudice that the integrator must be sampled and discharged by disconnecting the relevant circuit. The automatic discharging process of the integrator utilizes the principle that forward current and reverse current are input to two ends of the integrator, so that positive and negative charges formed by positive and negative currents are mutually offset, automatic discharging is completed under the condition of uninterrupted charge of an input end, and the next integration is automatically started from zero after the automatic discharging is completed. The automatic calibration circuit and the automatic discharging circuit replace a sampling break switch of an integrator and a discharging break switch of the integrator in the prior art, and solve the problem of dead time of the lost charge of the integrator caused by sampling break and discharging break.
Drawings
FIG. 1 is a schematic diagram of a prior art charge integration circuit;
FIG. 2 is a diagram of an ionization chamber charge signal read-out apparatus of the present invention;
FIG. 3 is a partial enlarged view of a MUX multiplexer application;
FIG. 4 is a flow chart of the ionization chamber charge signal read-out of the present invention;
FIG. 5 is an integration and discharge timing diagram of the present invention;
Detailed Description
Design principle of the invention
1. The invention is different from the prior art: fig. 1 is a schematic diagram of a charge integrating circuit in the prior art, and fig. 2 is a diagram of an ionization chamber charge signal readout device after modification of the present invention, wherein two switches S1 and S2 are removed, and a discharging circuit, a correction circuit, and a DSP for controlling the discharging circuit and the correction circuit are added. The high voltage module is not an essential feature of the present invention.
2. The correction circuit and automatic sampling of the present invention are used to replace the prior art integrator hold samples. The correction circuit comprises a discharge resistor R, MUX, DAC, DSP from left to right, the ideal integration circuit should have zero output voltage when the signal at the input end is zero, but the integration voltage has a tiny value due to bias current, leakage current and the like in the circuit, when the DSP detects that the difference value exists between the signal at the output end of the integrator and the theoretical value zero, a digital signal is given to the DAC, the DAC outputs a voltage signal to load on the correction resistor R to form correction current, and the current returns to the signal input end of the integrator to finish correction, so that the output of the integration voltage is zero when no signal is input at the input end. Since the corrected state is maintained for a long period of time after correction once without any change, the integrator is usually required to be corrected once a day before operation. After the correction is completed, the integrator can realize automatic sampling under the condition that the paths between the capacitor and the charge are always connected, and the integrator can sample without disconnecting the paths between the capacitor and the charge before sampling and putting the integrator into a holding state because the error problem of the input end and the output end does not exist for a quite long time. The dead time of the hold phase occurs just because the path between the capacitor and the charge is disconnected, at which point the source of the charge is not turned off and the charge is no longer flowing to the integrator but is flowing elsewhere, the integrator losing charge for a period of time called the dead time. After the invention is improved, the sampling of the integrator is not required to be broken, so that the dead time problem of the sampling stage of the integrator is radically eliminated.
3. The discharge circuit of the invention replaces the integrator of the prior art to break the discharge. The dead time of the discharge phase is because the branch circuit with the input connected to the integrator is open, and the source of charge is not closed, so that during the period from when the branch circuit is open to when the discharge is completed, a portion of the charge flows elsewhere and is lost by the integrator, which is referred to as the dead time. The input end of the discharging circuit is not provided with the switch S1, the charge flow from the charge source to the integrator during discharging is always in one forward direction and one reverse direction, and the charge at the input end is in the forward direction if the charge discharged by the integrator is in the reverse direction, and the discharging is completed when positive and negative counteractions are generated. Assuming that the integrator accumulates 100 charges and should discharge 100 charges, when the discharge is required, the DSP gives the DAC of the discharge circuit a digital signal of a reverse voltage, and the DAC outputs a reverse voltage to the discharge resistor to form a reverse current, and the reverse current forms a reverse charge under the pulse action of a certain pulse width, where the reverse voltage is a voltage opposite to the capacitor voltage of the integrator. When positive and negative 100 charges generated by the two voltages cancel each other, the discharging is completed, then the input end starts to input positive charges to the integrator again from 101 charges, and the discharging is continued again and repeatedly until the integrator accumulates 100 charges. The input end of the discharging process is not broken, and the method of respectively adding the forward voltage and the reverse voltage at the two ends of the capacitor is utilized, so that the problem of charge loss is solved, and the problem of dead time is also solved.
4. Ionization chamber charge signal readout device: as shown in fig. 2 and 3, the ionization chamber charge signal readout device comprises a charge integration circuit and an analog converter ADC arranged at the output end of the charge integration circuit, and is characterized in that: between the input end and the output end of the charge integration circuit, a discharging circuit for realizing automatic discharging, a calibration circuit for calibrating a difference value and a DSP control unit for controlling the discharging circuit and the calibration circuit are also arranged, and the DSP control unit is arranged on the same side as the output end of the charge integration circuit.
Supplementary explanation:
the charge integrator integrates the charge signal directly into the integrating capacitance in the circuit using the concept of virtual ground of the amplifier input, so that the output of the amplifier is the output of the sum of all the charge amounts. The integration of current over time over a period of time is the amount of charge:for an integrating circuit, the relationship between the output voltage and the amount of charge is u=q/C. For the present invention, the amount of charge measured and the average current measured in the two readings are:
Q＝k(ADCend-ADCstart)
i＝Q/t
where k is the gain factor and t is the sampling time interval.
After one sampling is completed, the integrating capacitor needs to be charged reversely according to the measured signal value, in order to maintain the electric quantity of the capacitor to the original state before integration, the discharged electric quantity should be equal to the previous integrated electric quantity, namely qdis=q, the discharging process is realized by the pulse voltage applied on the discharging resistor, one end of the discharging resistor is connected with the discharging pulse, the other end is connected with the input end of the integrating circuit, the pulse width of the discharging pulse is fixed and unchanged to be T, the amplitude U is equivalently set by the DSP according to the measured input signal value, and finally
Qdis＝Q＝U*T/R
T＝Tdis＝TADC/3
The calibration circuit comprises a digital-to-analog converter DAC, a precision resistor, a high insulation impedance relay and a switch control circuit thereof; the precision resistor and the digital-to-analog converter DAC are respectively arranged on the side of the input end of the calibration circuit, which is close to the charge integration circuit, and the side of the output end of the calibration circuit, which is close to the charge integration circuit.
The calibrated parameters are stored in an EEPROM; the DAC is bipolar and has more than 16 bits, and because the calibration current needs to be very accurate, a precise resistor is needed, and the precision is more than 1 percent; the high insulation resistance relay is required to have an insulation resistance of 10gΩ or more.
The discharging circuit comprises a single-pole double-throw selection Switch SPDT Switch, a digital-to-analog converter DAC and a discharging resistor, wherein the discharging resistor is arranged at the side close to the input end of the operational amplifier, the DAC is arranged at the side close to the output end of the operational amplifier and is connected with a DSP control unit, the DSP control unit controls the DAC in two paths, one path controls the amplitude of the DAC input, and the other path controls the pulse width of the DAC input.
The DAC requires more than 16 bits of bipolar, SPDT Switch charges are injected within 1pC, and leakage current is within 100 pA.
The charge integration circuit includes: the charge signal input interface, the operational amplifier, the integrating capacitor and the divider resistor; one end of the integrating capacitor is connected with the charge signal input interface, and the other end of the integrating capacitor is connected with the output port of the operational amplifier; the integral capacitor is required to be NP0 capacitor and is insensitive to temperature change; the high-insulation-resistance relay has an insulation resistance of more than 10G omega. The analog converter ADC is used for realizing the digitization of the integral voltage, and requires a minimum of 16 bits, and the sampling rate is more than 250 k.
The ionization chamber charge signal reading device also comprises a high-voltage module, wherein the high-voltage module comprises a high-voltage power supply and an output adjusting mechanism-adjustable potentiometer; in addition, the high-voltage read-back circuit is further provided, voltage read-back is realized by utilizing a voltage dividing resistor, and high-voltage read-back value sampling and digital reading are realized through an ADC. The high voltage module is required to be able to output voltages up to 2 kV.
Based on the principle of the invention and the ionization chamber charge signal reading device, the invention designs an ionization chamber charge signal reading method, which comprises the following steps:
step one, calibrating an automatic circuit in a zero input and zero output mode before integration begins;
the specific process is as follows:
1) The signal of the input end of the current integrating circuit is set to be zero;
2) The DSP detects whether the signal of the output end of the current integrating circuit is zero;
if the difference value is not zero, continuing to perform the process 3), and if the difference value is zero, ending without circuit calibration;
3) The DSP gives a calibration digital signal to the DAC;
4) The DAC outputs a correction voltage signal to the correction resistor R to form correction current;
5) The correction current is returned to the integrator signal input;
6) And when the input end has no signal input and the output end integral voltage output is zero, the calibration is completed.
Step two, automatic integral sampling in a voltage stabilization domain based on circuit calibration;
the specific process is as follows:
1) The charge source inputs charges to the integrator;
2) Integrating voltage sampling by an integrator;
3) The DSP judges whether sampling is carried out for 3 times continuously;
if less than 3 times return to process 2), if equal to 3 times, enter the discharge process of step three.
Thirdly, the negative charge and the positive charge are offset to finish automatic discharge by loading reverse voltage;
the specific process is as follows:
1) The DSP sends a reverse voltage signal to the DAC after the 3 rd sampling period of one integration period is completed, and the amplitude of the reverse voltage signal is set according to the sampling value of the integrated voltage of the previous three times;
supplementary description
After the DSP finishes sampling the integrated voltage in the 3 rd sampling period in one integration period, sending a reverse voltage signal to the DAC, setting the amplitude of the DAC output reverse discharge voltage according to the integrated voltage value sampled three times before, forming a current by the discharge voltage through a discharge resistor, forming charges with the same sign and opposite sign as the charge quantity accumulated before the integrator under the pulse action of a certain pulse width, and thus, the positive charge and the negative charge are mutually offset to realize an automatic discharge process;
2) The DAC applies reverse voltage to the discharge resistor;
3) The positive and negative charges on the integrator capacitor cancel to complete automatic discharge.
Step four, the ADC starts to enter integral sampling again from the next sampling period;
the specific process is as follows:
1) After the positive and negative charges are counteracted, the ADC waits for entering the next clock period;
2) The ADC starts integrating the voltage sample on the rising edge of the next clock cycle.
Example 1
The signal reading device comprises an operational amplifier, an integrating capacitor, an analog-to-digital converter ADC, a discharging circuit, a DSP control unit, a high-voltage module, a calibration module and the like.
The integrating circuit can be realized by an operational amplifier and an integrating capacitor, and can also be realized by a special integrating circuit chip. The charge signal input interface realizes the input of signals, is connected with the input end of the integrating circuit, and the input end of the operational amplifier is connected with the integrating capacitor in parallel, so that the measurement of the input signals in a wider range can be realized in a mode of externally connecting a large capacitor in parallel; one end of the external capacitor is connected with the relay to realize on and off control, and the other end is connected with the parallel end; the integrated voltage output is sampled by Buffer to ADC.
The discharging circuit comprises a digital-to-analog converter DAC, a single-pole double-throw selection switch and a discharging resistor, wherein the DAC realizes the setting of the amplitude of a discharging pulse through the control of a DSP, and the pulse width is set to be 1/3 times of the sampling frequency after passing through the selection switch.
The calibration module comprises a digital-to-analog converter DAC, a precision resistor, a high insulation resistance relay and a switch control circuit thereof, the circuit can calculate the gain value of the integration circuit according to a standard current source, the actual value of the integration capacitor can be determined, and the calibrated parameters are stored in an EEPROM.
The high-voltage module comprises a high-voltage power supply and an output adjusting mechanism-an adjustable potentiometer; in addition, the high-voltage read-back circuit is further provided, voltage read-back is realized by utilizing a voltage dividing resistor, and high-voltage read-back value sampling and digital reading are realized through an ADC.
The DSP control unit comprises a digital signal processor DSP, an optical fiber communication module, a USB communication module, an EEPROM, JTAG and the like. The DSP controls the ADC to realize the digitization of the integral voltage and the readback of the high-voltage value; the control DAC realizes the calibration of the integrating circuit and the setting of the discharge pulse amplitude. The frequency of the discharge pulse is one third of the sampling frequency.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (2)
1. An ionization chamber charge signal reading method, which is based on an ionization chamber charge signal reading device, the device comprises a charge integration circuit and an analog converter ADC arranged at the output end of the charge integration circuit, and is characterized in that: a discharging circuit for realizing automatic discharging, a calibration circuit for calibrating a difference value and a DSP control unit for controlling the discharging circuit and the calibration circuit are also arranged between the input end and the output end of the charge integration circuit, and the DSP control unit is arranged on the same side as the output end of the charge integration circuit;
the discharging circuit comprises a single-pole double-throw selection Switch SPDT Switch, a digital-to-analog converter DAC and a discharging resistor, wherein the discharging resistor is arranged at the side close to the input end of the operational amplifier, the DAC is arranged at the side close to the output end of the operational amplifier and is connected with a DSP control unit, the DSP control unit controls the DAC in two paths, one path controls the amplitude of the DAC input, and the other path controls the pulse width of the DAC input;
after the DSP finishes sampling the integrated voltage in the 3 rd sampling period in one integration period, sending a reverse voltage signal to the DAC, setting the amplitude of the DAC output reverse discharge voltage according to the integrated voltage value sampled three times before, forming a current by the discharge voltage through a discharge resistor, forming charges with the same sign and opposite sign as the charge quantity accumulated before the integrator under the pulse action of a certain pulse width, and thus, the positive charge and the negative charge are mutually offset to realize an automatic discharge process;
the method is characterized in that: the method comprises the following steps:
step one, calibrating an automatic circuit in a zero input and zero output mode before integration begins;
step two, automatic integral sampling in a voltage stabilization domain based on circuit calibration;
the specific process is as follows:
1) The charge source inputs charges to the integrator;
2) Integrating voltage sampling by an integrator;
3) The DSP judges whether sampling is carried out for 3 times continuously; returning to the process 2) if the number of the discharge steps is less than 3, and entering the discharge process of the step three if the number of the discharge steps is equal to 3;
thirdly, the negative charge and the positive charge are offset to finish automatic discharge by loading reverse voltage;
the specific process is as follows:
1) The DSP sends a reverse voltage signal to the DAC after the 3 rd sampling period of one integration period is completed, and the amplitude of the reverse voltage signal is set according to the sampling value of the integrated voltage of the previous three times;
2) The DAC applies reverse voltage to the discharge resistor;
3) The positive and negative charges on the integrator capacitor are counteracted to finish automatic discharge; the DAC outputs a reverse voltage to the discharge resistor so as to form a reverse current, the reverse current forms a reverse charge under the pulse action of a certain pulse width, and the reverse charge and the forward charge on the integrator are mutually counteracted;
step four, the ADC starts to enter the integration sampling again from the next integration period;
the specific process is as follows:
1) After the positive and negative charges are counteracted, the ADC waits for entering the first sampling period of the next integration period;
2) The ADC starts integrating voltage sampling on the rising edge of the first sampling period of the next integration period.
2. The method of claim 1, wherein: the specific process of the first step is as follows:
1) The signal of the input end of the current integrating circuit is set to be zero;
2) The DSP detects whether the signal of the output end of the current integrating circuit is zero;
if the difference value is not zero, continuing to perform the process 3), and if the difference value is zero, ending without circuit calibration;
3) The DSP gives a calibration digital signal to the DAC;
4) The DAC outputs a correction voltage signal to the correction resistor R to form correction current;
5) The correction current is returned to the integrator signal input;
6) And when the input end has no signal input and the output end integral voltage output is zero, the calibration is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011536817.2A CN112737534B (en) | 2020-12-23 | 2020-12-23 | Ionization chamber charge signal reading method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011536817.2A CN112737534B (en) | 2020-12-23 | 2020-12-23 | Ionization chamber charge signal reading method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112737534A CN112737534A (en) | 2021-04-30 |
| CN112737534B true CN112737534B (en) | 2023-12-12 |
Family
ID=75604422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011536817.2A Active CN112737534B (en) | 2020-12-23 | 2020-12-23 | Ionization chamber charge signal reading method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112737534B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113702724A (en) * | 2021-09-10 | 2021-11-26 | 常州同惠电子股份有限公司 | Circuit and method for eliminating leakage current of charge test circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101277111A (en) * | 2007-03-30 | 2008-10-01 | 恩益禧电子股份有限公司 | Dither circuit and analog digital converter having dither circuit |
| CN105593701A (en) * | 2013-09-25 | 2016-05-18 | 模拟技术公司 | Hybrid photon counting data acquisition system |
| CN106953637A (en) * | 2017-03-09 | 2017-07-14 | 黄山学院 | Charge-domain range error calibrates circuit and the DDS circuit using the calibration circuit |
| CN110531404A (en) * | 2019-06-03 | 2019-12-03 | 中国科学技术大学 | Core pulse charge time translation method and system |
| CN110572157A (en) * | 2019-08-30 | 2019-12-13 | 中勍科技有限公司 | temperature compensation method for I/F conversion circuit board |
| CN110869722A (en) * | 2017-07-10 | 2020-03-06 | ams有限公司 | Optical sensor device and method for optical sensing |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002023729A1 (en) * | 2000-09-15 | 2002-03-21 | Radian Research, Inc. | Method and apparatus for analog-to-digital conversion |
| US20090251572A1 (en) * | 2008-04-02 | 2009-10-08 | Chi-Shao Lin | Efficient wide-range and high-resolution black level and offset calibration system |
-
2020
- 2020-12-23 CN CN202011536817.2A patent/CN112737534B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101277111A (en) * | 2007-03-30 | 2008-10-01 | 恩益禧电子股份有限公司 | Dither circuit and analog digital converter having dither circuit |
| CN105593701A (en) * | 2013-09-25 | 2016-05-18 | 模拟技术公司 | Hybrid photon counting data acquisition system |
| CN106953637A (en) * | 2017-03-09 | 2017-07-14 | 黄山学院 | Charge-domain range error calibrates circuit and the DDS circuit using the calibration circuit |
| CN110869722A (en) * | 2017-07-10 | 2020-03-06 | ams有限公司 | Optical sensor device and method for optical sensing |
| CN110531404A (en) * | 2019-06-03 | 2019-12-03 | 中国科学技术大学 | Core pulse charge time translation method and system |
| CN110572157A (en) * | 2019-08-30 | 2019-12-13 | 中勍科技有限公司 | temperature compensation method for I/F conversion circuit board |
Non-Patent Citations (2)
| Title |
|---|
| The Design of Magnetic Field Measurements System for CYCIAE-100;Junqing Zhong et al;《 IEEE Transactions on Applied Superconductivity》;第第20卷卷(第第3期期);第2019-2022页 * |
| 二维高集成高场不对称波形离子迁移谱;陈池来;《中国博士学位论文全文数据库》;第1-132页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112737534A (en) | 2021-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4082998A (en) | Dual slope integration circuit | |
| RU2280841C2 (en) | Commutation unit for capacitive pickup | |
| US20040051534A1 (en) | Battery pack voltage detection apparatus | |
| US4663586A (en) | Device with automatic compensation of an ac attenuator | |
| CN112737534B (en) | Ionization chamber charge signal reading method | |
| CN107395172B (en) | Analog switch circuit and inverter resistance welder secondary current detection system | |
| WO2021184740A1 (en) | Current calibration device for power supply channel in test system, and correction method therefor | |
| US7592819B2 (en) | Microprocessor-based capacitance measurement | |
| CN112671405B (en) | Ionization chamber charge signal reading device | |
| CN108021172A (en) | A kind of high bandwidth input isolation sampling and precision calibration circuit and method | |
| US8947142B2 (en) | Common mode trimming with variable duty cycle | |
| US3943506A (en) | Multiple ramp digitisers | |
| Pagkalos et al. | Charge-based time registers for z-1 implementation | |
| US5831423A (en) | Phase meter and method of providing a voltage indicative of a phase difference | |
| US11057047B2 (en) | Ratiometric gain error calibration schemes for delta-sigma ADCs with capacitive gain input stages | |
| US4908526A (en) | Pulse generator output voltage calibration circuit | |
| US11057048B2 (en) | Ratiometric gain error calibration schemes for delta-sigma ADCs with programmable gain amplifier input stages | |
| CN102801423A (en) | 2-phase threshold detector based circuits | |
| CN210442479U (en) | Operational amplifier test circuit | |
| CN110658715B (en) | TDC circuit based on tap dynamic adjustable carry chain fine time interpolation delay line | |
| Batrakov et al. | Precision digital signal integrators with accurate synchronization | |
| CN106885929B (en) | Measuring device with double-ring ALC circuit | |
| CN110838830A (en) | Radiation detection chip | |
| US4627268A (en) | Method for calibrating instruments for time interval measurements | |
| US20120001784A1 (en) | Integrating (SLOPE) DAC Architecture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |